1/* Copyright (c) 2015 The Linux Foundation. All rights reserved. 2 * 3 * Permission to use, copy, modify, and/or distribute this software for any 4 * purpose with or without fee is hereby granted, provided that the above 5 * copyright notice and this permission notice appear in all copies. 6 * 7 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 8 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 9 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 10 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 11 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 12 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 13 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * 15 */ 16#ifndef __QCOM_CLK_IPQ4019_H__ 17#define __QCOM_CLK_IPQ4019_H__ 18 19#define GCC_DUMMY_CLK 0 20#define AUDIO_CLK_SRC 1 21#define BLSP1_QUP1_I2C_APPS_CLK_SRC 2 22#define BLSP1_QUP1_SPI_APPS_CLK_SRC 3 23#define BLSP1_QUP2_I2C_APPS_CLK_SRC 4 24#define BLSP1_QUP2_SPI_APPS_CLK_SRC 5 25#define BLSP1_UART1_APPS_CLK_SRC 6 26#define BLSP1_UART2_APPS_CLK_SRC 7 27#define GCC_USB3_MOCK_UTMI_CLK_SRC 8 28#define GCC_APPS_CLK_SRC 9 29#define GCC_APPS_AHB_CLK_SRC 10 30#define GP1_CLK_SRC 11 31#define GP2_CLK_SRC 12 32#define GP3_CLK_SRC 13 33#define SDCC1_APPS_CLK_SRC 14 34#define FEPHY_125M_DLY_CLK_SRC 15 35#define WCSS2G_CLK_SRC 16 36#define WCSS5G_CLK_SRC 17 37#define GCC_APSS_AHB_CLK 18 38#define GCC_AUDIO_AHB_CLK 19 39#define GCC_AUDIO_PWM_CLK 20 40#define GCC_BLSP1_AHB_CLK 21 41#define GCC_BLSP1_QUP1_I2C_APPS_CLK 22 42#define GCC_BLSP1_QUP1_SPI_APPS_CLK 23 43#define GCC_BLSP1_QUP2_I2C_APPS_CLK 24 44#define GCC_BLSP1_QUP2_SPI_APPS_CLK 25 45#define GCC_BLSP1_UART1_APPS_CLK 26 46#define GCC_BLSP1_UART2_APPS_CLK 27 47#define GCC_DCD_XO_CLK 28 48#define GCC_GP1_CLK 29 49#define GCC_GP2_CLK 30 50#define GCC_GP3_CLK 31 51#define GCC_BOOT_ROM_AHB_CLK 32 52#define GCC_CRYPTO_AHB_CLK 33 53#define GCC_CRYPTO_AXI_CLK 34 54#define GCC_CRYPTO_CLK 35 55#define GCC_ESS_CLK 36 56#define GCC_IMEM_AXI_CLK 37 57#define GCC_IMEM_CFG_AHB_CLK 38 58#define GCC_PCIE_AHB_CLK 39 59#define GCC_PCIE_AXI_M_CLK 40 60#define GCC_PCIE_AXI_S_CLK 41 61#define GCC_PCNOC_AHB_CLK 42 62#define GCC_PRNG_AHB_CLK 43 63#define GCC_QPIC_AHB_CLK 44 64#define GCC_QPIC_CLK 45 65#define GCC_SDCC1_AHB_CLK 46 66#define GCC_SDCC1_APPS_CLK 47 67#define GCC_SNOC_PCNOC_AHB_CLK 48 68#define GCC_SYS_NOC_125M_CLK 49 69#define GCC_SYS_NOC_AXI_CLK 50 70#define GCC_TCSR_AHB_CLK 51 71#define GCC_TLMM_AHB_CLK 52 72#define GCC_USB2_MASTER_CLK 53 73#define GCC_USB2_SLEEP_CLK 54 74#define GCC_USB2_MOCK_UTMI_CLK 55 75#define GCC_USB3_MASTER_CLK 56 76#define GCC_USB3_SLEEP_CLK 57 77#define GCC_USB3_MOCK_UTMI_CLK 58 78#define GCC_WCSS2G_CLK 59 79#define GCC_WCSS2G_REF_CLK 60 80#define GCC_WCSS2G_RTC_CLK 61 81#define GCC_WCSS5G_CLK 62 82#define GCC_WCSS5G_REF_CLK 63 83#define GCC_WCSS5G_RTC_CLK 64 84#define GCC_APSS_DDRPLL_VCO 65 85#define GCC_SDCC_PLLDIV_CLK 66 86#define GCC_FEPLL_VCO 67 87#define GCC_FEPLL125_CLK 68 88#define GCC_FEPLL125DLY_CLK 69 89#define GCC_FEPLL200_CLK 70 90#define GCC_FEPLL500_CLK 71 91#define GCC_FEPLL_WCSS2G_CLK 72 92#define GCC_FEPLL_WCSS5G_CLK 73 93#define GCC_APSS_CPU_PLLDIV_CLK 74 94#define GCC_PCNOC_AHB_CLK_SRC 75 95 96#define WIFI0_CPU_INIT_RESET 0 97#define WIFI0_RADIO_SRIF_RESET 1 98#define WIFI0_RADIO_WARM_RESET 2 99#define WIFI0_RADIO_COLD_RESET 3 100#define WIFI0_CORE_WARM_RESET 4 101#define WIFI0_CORE_COLD_RESET 5 102#define WIFI1_CPU_INIT_RESET 6 103#define WIFI1_RADIO_SRIF_RESET 7 104#define WIFI1_RADIO_WARM_RESET 8 105#define WIFI1_RADIO_COLD_RESET 9 106#define WIFI1_CORE_WARM_RESET 10 107#define WIFI1_CORE_COLD_RESET 11 108#define USB3_UNIPHY_PHY_ARES 12 109#define USB3_HSPHY_POR_ARES 13 110#define USB3_HSPHY_S_ARES 14 111#define USB2_HSPHY_POR_ARES 15 112#define USB2_HSPHY_S_ARES 16 113#define PCIE_PHY_AHB_ARES 17 114#define PCIE_AHB_ARES 18 115#define PCIE_PWR_ARES 19 116#define PCIE_PIPE_STICKY_ARES 20 117#define PCIE_AXI_M_STICKY_ARES 21 118#define PCIE_PHY_ARES 22 119#define PCIE_PARF_XPU_ARES 23 120#define PCIE_AXI_S_XPU_ARES 24 121#define PCIE_AXI_M_VMIDMT_ARES 25 122#define PCIE_PIPE_ARES 26 123#define PCIE_AXI_S_ARES 27 124#define PCIE_AXI_M_ARES 28 125#define ESS_RESET 29 126#define GCC_BLSP1_BCR 30 127#define GCC_BLSP1_QUP1_BCR 31 128#define GCC_BLSP1_UART1_BCR 32 129#define GCC_BLSP1_QUP2_BCR 33 130#define GCC_BLSP1_UART2_BCR 34 131#define GCC_BIMC_BCR 35 132#define GCC_TLMM_BCR 36 133#define GCC_IMEM_BCR 37 134#define GCC_ESS_BCR 38 135#define GCC_PRNG_BCR 39 136#define GCC_BOOT_ROM_BCR 40 137#define GCC_CRYPTO_BCR 41 138#define GCC_SDCC1_BCR 42 139#define GCC_SEC_CTRL_BCR 43 140#define GCC_AUDIO_BCR 44 141#define GCC_QPIC_BCR 45 142#define GCC_PCIE_BCR 46 143#define GCC_USB2_BCR 47 144#define GCC_USB2_PHY_BCR 48 145#define GCC_USB3_BCR 49 146#define GCC_USB3_PHY_BCR 50 147#define GCC_SYSTEM_NOC_BCR 51 148#define GCC_PCNOC_BCR 52 149#define GCC_DCD_BCR 53 150#define GCC_SNOC_BUS_TIMEOUT0_BCR 54 151#define GCC_SNOC_BUS_TIMEOUT1_BCR 55 152#define GCC_SNOC_BUS_TIMEOUT2_BCR 56 153#define GCC_SNOC_BUS_TIMEOUT3_BCR 57 154#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58 155#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59 156#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60 157#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61 158#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62 159#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63 160#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64 161#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65 162#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66 163#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67 164#define GCC_TCSR_BCR 68 165#define GCC_QDSS_BCR 69 166#define GCC_MPM_BCR 70 167#define GCC_SPDM_BCR 71 168#define ESS_MAC1_ARES 72 169#define ESS_MAC2_ARES 73 170#define ESS_MAC3_ARES 74 171#define ESS_MAC4_ARES 75 172#define ESS_MAC5_ARES 76 173#define ESS_PSGMII_ARES 77 174 175#endif 176