1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Porting to u-boot:
4 *
5 * (C) Copyright 2010
6 * Stefano Babic, DENX Software Engineering, sbabic@denx.de
7 *
8 * Linux IPU driver for MX51:
9 *
10 * (C) Copyright 2005-2009 Freescale Semiconductor, Inc.
11 */
12
13#ifndef __IPU_REGS_INCLUDED__
14#define __IPU_REGS_INCLUDED__
15
16#define IPU_DISP0_BASE		0x00000000
17#define IPU_MCU_T_DEFAULT	8
18#define IPU_DISP1_BASE		(IPU_MCU_T_DEFAULT << 25)
19#define IPU_CM_REG_BASE		0x00000000
20#define IPU_STAT_REG_BASE	0x00000200
21#define IPU_IDMAC_REG_BASE	0x00008000
22#define IPU_ISP_REG_BASE	0x00010000
23#define IPU_DP_REG_BASE		0x00018000
24#define IPU_IC_REG_BASE		0x00020000
25#define IPU_IRT_REG_BASE	0x00028000
26#define IPU_CSI0_REG_BASE	0x00030000
27#define IPU_CSI1_REG_BASE	0x00038000
28#define IPU_DI0_REG_BASE	0x00040000
29#define IPU_DI1_REG_BASE	0x00048000
30#define IPU_SMFC_REG_BASE	0x00050000
31#define IPU_DC_REG_BASE		0x00058000
32#define IPU_DMFC_REG_BASE	0x00060000
33#define IPU_VDI_REG_BASE	0x00680000
34#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
35#define IPU_CPMEM_REG_BASE	0x01000000
36#define IPU_LUT_REG_BASE	0x01020000
37#define IPU_SRM_REG_BASE	0x01040000
38#define IPU_TPM_REG_BASE	0x01060000
39#define IPU_DC_TMPL_REG_BASE	0x01080000
40#define IPU_ISP_TBPR_REG_BASE	0x010C0000
41#elif defined(CONFIG_MX6)
42#define IPU_CPMEM_REG_BASE	0x00100000
43#define IPU_LUT_REG_BASE	0x00120000
44#define IPU_SRM_REG_BASE	0x00140000
45#define IPU_TPM_REG_BASE	0x00160000
46#define IPU_DC_TMPL_REG_BASE	0x00180000
47#define IPU_ISP_TBPR_REG_BASE	0x001C0000
48#endif
49
50#define IPU_CTRL_BASE_ADDR	(IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET)
51
52extern u32 *ipu_dc_tmpl_reg;
53
54#define DC_EVT_NF		0
55#define DC_EVT_NL		1
56#define DC_EVT_EOF		2
57#define DC_EVT_NFIELD		3
58#define DC_EVT_EOL		4
59#define DC_EVT_EOFIELD		5
60#define DC_EVT_NEW_ADDR		6
61#define DC_EVT_NEW_CHAN		7
62#define DC_EVT_NEW_DATA		8
63
64#define DC_EVT_NEW_ADDR_W_0	0
65#define DC_EVT_NEW_ADDR_W_1	1
66#define DC_EVT_NEW_CHAN_W_0	2
67#define DC_EVT_NEW_CHAN_W_1	3
68#define DC_EVT_NEW_DATA_W_0	4
69#define DC_EVT_NEW_DATA_W_1	5
70#define DC_EVT_NEW_ADDR_R_0	6
71#define DC_EVT_NEW_ADDR_R_1	7
72#define DC_EVT_NEW_CHAN_R_0	8
73#define DC_EVT_NEW_CHAN_R_1	9
74#define DC_EVT_NEW_DATA_R_0	10
75#define DC_EVT_NEW_DATA_R_1	11
76
77/* Software reset for ipu */
78#define SW_IPU_RST	8
79
80enum {
81	IPU_CONF_DP_EN = 0x00000020,
82	IPU_CONF_DI0_EN = 0x00000040,
83	IPU_CONF_DI1_EN = 0x00000080,
84	IPU_CONF_DMFC_EN = 0x00000400,
85	IPU_CONF_DC_EN = 0x00000200,
86
87	DI0_COUNTER_RELEASE = 0x01000000,
88	DI1_COUNTER_RELEASE = 0x02000000,
89
90	DI_DW_GEN_ACCESS_SIZE_OFFSET = 24,
91	DI_DW_GEN_COMPONENT_SIZE_OFFSET = 16,
92
93	DI_GEN_DI_CLK_EXT = 0x100000,
94	DI_GEN_POLARITY_1 = 0x00000001,
95	DI_GEN_POLARITY_2 = 0x00000002,
96	DI_GEN_POLARITY_3 = 0x00000004,
97	DI_GEN_POLARITY_4 = 0x00000008,
98	DI_GEN_POLARITY_5 = 0x00000010,
99	DI_GEN_POLARITY_6 = 0x00000020,
100	DI_GEN_POLARITY_7 = 0x00000040,
101	DI_GEN_POLARITY_8 = 0x00000080,
102	DI_GEN_POL_CLK = 0x20000,
103
104	DI_POL_DRDY_DATA_POLARITY = 0x00000080,
105	DI_POL_DRDY_POLARITY_15 = 0x00000010,
106	DI_VSYNC_SEL_OFFSET = 13,
107
108	DC_WR_CH_CONF_FIELD_MODE = 0x00000200,
109	DC_WR_CH_CONF_PROG_TYPE_OFFSET = 5,
110	DC_WR_CH_CONF_PROG_TYPE_MASK = 0x000000E0,
111	DC_WR_CH_CONF_PROG_DI_ID = 0x00000004,
112	DC_WR_CH_CONF_PROG_DISP_ID_OFFSET = 3,
113	DC_WR_CH_CONF_PROG_DISP_ID_MASK = 0x00000018,
114
115	DP_COM_CONF_FG_EN = 0x00000001,
116	DP_COM_CONF_GWSEL = 0x00000002,
117	DP_COM_CONF_GWAM = 0x00000004,
118	DP_COM_CONF_GWCKE = 0x00000008,
119	DP_COM_CONF_CSC_DEF_MASK = 0x00000300,
120	DP_COM_CONF_CSC_DEF_OFFSET = 8,
121	DP_COM_CONF_CSC_DEF_FG = 0x00000300,
122	DP_COM_CONF_CSC_DEF_BG = 0x00000200,
123	DP_COM_CONF_CSC_DEF_BOTH = 0x00000100,
124	DP_COM_CONF_GAMMA_EN = 0x00001000,
125	DP_COM_CONF_GAMMA_YUV_EN = 0x00002000,
126};
127
128enum di_pins {
129	DI_PIN11 = 0,
130	DI_PIN12 = 1,
131	DI_PIN13 = 2,
132	DI_PIN14 = 3,
133	DI_PIN15 = 4,
134	DI_PIN16 = 5,
135	DI_PIN17 = 6,
136	DI_PIN_CS = 7,
137
138	DI_PIN_SER_CLK = 0,
139	DI_PIN_SER_RS = 1,
140};
141
142enum di_sync_wave {
143	DI_SYNC_NONE = -1,
144	DI_SYNC_CLK = 0,
145	DI_SYNC_INT_HSYNC = 1,
146	DI_SYNC_HSYNC = 2,
147	DI_SYNC_VSYNC = 3,
148	DI_SYNC_DE = 5,
149};
150
151struct ipu_cm {
152	u32 conf;
153	u32 sisg_ctrl0;
154	u32 sisg_ctrl1;
155	u32 sisg_set[6];
156	u32 sisg_clear[6];
157	u32 int_ctrl[15];
158	u32 sdma_event[10];
159	u32 srm_pri1;
160	u32 srm_pri2;
161	u32 fs_proc_flow[3];
162	u32 fs_disp_flow[2];
163	u32 skip;
164	u32 disp_alt_conf;
165	u32 disp_gen;
166	u32 disp_alt[4];
167	u32 snoop;
168	u32 mem_rst;
169	u32 pm;
170	u32 gpr;
171	u32 reserved0[26];
172	u32 ch_db_mode_sel[2];
173	u32 reserved1[4];
174	u32 alt_ch_db_mode_sel[2];
175	u32 reserved2[2];
176	u32 ch_trb_mode_sel[2];
177};
178
179struct ipu_idmac {
180	u32 conf;
181	u32 ch_en[2];
182	u32 sep_alpha;
183	u32 alt_sep_alpha;
184	u32 ch_pri[2];
185	u32 wm_en[2];
186	u32 lock_en[2];
187	u32 sub_addr[5];
188	u32 bndm_en[2];
189	u32 sc_cord[2];
190	u32 reserved[44];
191	u32 ch_busy[2];
192};
193
194struct ipu_com_async {
195	u32 com_conf_async;
196	u32 graph_wind_ctrl_async;
197	u32 fg_pos_async;
198	u32 cur_pos_async;
199	u32 cur_map_async;
200	u32 gamma_c_async[8];
201	u32 gamma_s_async[4];
202	u32 dp_csca_async[4];
203	u32 dp_csc_async[2];
204};
205
206struct ipu_dp {
207	u32 com_conf_sync;
208	u32 graph_wind_ctrl_sync;
209	u32 fg_pos_sync;
210	u32 cur_pos_sync;
211	u32 cur_map_sync;
212	u32 gamma_c_sync[8];
213	u32 gamma_s_sync[4];
214	u32 csca_sync[4];
215	u32 csc_sync[2];
216	u32 cur_pos_alt;
217	struct ipu_com_async async[2];
218};
219
220struct ipu_di {
221	u32 general;
222	u32 bs_clkgen0;
223	u32 bs_clkgen1;
224	u32 sw_gen0[9];
225	u32 sw_gen1[9];
226	u32 sync_as;
227	u32 dw_gen[12];
228	u32 dw_set[48];
229	u32 stp_rep[4];
230	u32 stp_rep9;
231	u32 ser_conf;
232	u32 ssc;
233	u32 pol;
234	u32 aw0;
235	u32 aw1;
236	u32 scr_conf;
237	u32 stat;
238};
239
240struct ipu_stat {
241	u32 int_stat[15];
242	u32 cur_buf[2];
243	u32 alt_cur_buf_0;
244	u32 alt_cur_buf_1;
245	u32 srm_stat;
246	u32 proc_task_stat;
247	u32 disp_task_stat;
248	u32 triple_cur_buf[4];
249	u32 ch_buf0_rdy[2];
250	u32 ch_buf1_rdy[2];
251	u32 alt_ch_buf0_rdy[2];
252	u32 alt_ch_buf1_rdy[2];
253	u32 ch_buf2_rdy[2];
254};
255
256struct ipu_dc_ch {
257	u32 wr_ch_conf;
258	u32 wr_ch_addr;
259	u32 rl[5];
260};
261
262struct ipu_dc {
263	struct ipu_dc_ch dc_ch0_1_2[3];
264	u32 cmd_ch_conf_3;
265	u32 cmd_ch_conf_4;
266	struct ipu_dc_ch dc_ch5_6[2];
267	struct ipu_dc_ch dc_ch8;
268	u32 rl6_ch_8;
269	struct ipu_dc_ch dc_ch9;
270	u32 rl6_ch_9;
271	u32 gen;
272	u32 disp_conf1[4];
273	u32 disp_conf2[4];
274	u32 di0_conf[2];
275	u32 di1_conf[2];
276	u32 dc_map_ptr[15];
277	u32 dc_map_val[12];
278	u32 udge[16];
279	u32 lla[2];
280	u32 r_lla[2];
281	u32 wr_ch_addr_5_alt;
282	u32 stat;
283};
284
285struct ipu_dmfc {
286	u32 rd_chan;
287	u32 wr_chan;
288	u32 wr_chan_def;
289	u32 dp_chan;
290	u32 dp_chan_def;
291	u32 general[2];
292	u32 ic_ctrl;
293	u32 wr_chan_alt;
294	u32 wr_chan_def_alt;
295	u32 general1_alt;
296	u32 stat;
297};
298
299#define IPU_CM_REG		((struct ipu_cm *)(IPU_CTRL_BASE_ADDR + \
300				IPU_CM_REG_BASE))
301#define IPU_CONF		(&IPU_CM_REG->conf)
302#define IPU_SRM_PRI1		(&IPU_CM_REG->srm_pri1)
303#define IPU_SRM_PRI2		(&IPU_CM_REG->srm_pri2)
304#define IPU_FS_PROC_FLOW1	(&IPU_CM_REG->fs_proc_flow[0])
305#define IPU_FS_PROC_FLOW2	(&IPU_CM_REG->fs_proc_flow[1])
306#define IPU_FS_PROC_FLOW3	(&IPU_CM_REG->fs_proc_flow[2])
307#define IPU_FS_DISP_FLOW1	(&IPU_CM_REG->fs_disp_flow[0])
308#define IPU_DISP_GEN		(&IPU_CM_REG->disp_gen)
309#define IPU_MEM_RST		(&IPU_CM_REG->mem_rst)
310#define IPU_GPR			(&IPU_CM_REG->gpr)
311#define IPU_CHA_DB_MODE_SEL(ch)	(&IPU_CM_REG->ch_db_mode_sel[ch / 32])
312
313#define IPU_STAT		((struct ipu_stat *)(IPU_CTRL_BASE_ADDR + \
314				IPU_STAT_REG_BASE))
315#define IPU_INT_STAT(n)		(&IPU_STAT->int_stat[(n) - 1])
316#define IPU_CHA_CUR_BUF(ch)	(&IPU_STAT->cur_buf[ch / 32])
317#define IPU_CHA_BUF0_RDY(ch)	(&IPU_STAT->ch_buf0_rdy[ch / 32])
318#define IPU_CHA_BUF1_RDY(ch)	(&IPU_STAT->ch_buf1_rdy[ch / 32])
319#define IPUIRQ_2_STATREG(irq)	(IPU_INT_STAT(1) + ((irq) / 32))
320#define IPUIRQ_2_MASK(irq)	(1UL << ((irq) & 0x1F))
321
322#define IPU_INT_CTRL(n)		(&IPU_CM_REG->int_ctrl[(n) - 1])
323
324#define IDMAC_REG		((struct ipu_idmac *)(IPU_CTRL_BASE_ADDR + \
325				IPU_IDMAC_REG_BASE))
326#define IDMAC_CONF		(&IDMAC_REG->conf)
327#define IDMAC_CHA_EN(ch)	(&IDMAC_REG->ch_en[ch / 32])
328#define IDMAC_CHA_PRI(ch)	(&IDMAC_REG->ch_pri[ch / 32])
329
330#define DI_REG(di)		((struct ipu_di *)(IPU_CTRL_BASE_ADDR + \
331				((di == 1) ? IPU_DI1_REG_BASE : \
332				IPU_DI0_REG_BASE)))
333#define DI_GENERAL(di)		(&DI_REG(di)->general)
334#define DI_BS_CLKGEN0(di)	(&DI_REG(di)->bs_clkgen0)
335#define DI_BS_CLKGEN1(di)	(&DI_REG(di)->bs_clkgen1)
336
337#define DI_SW_GEN0(di, gen)	(&DI_REG(di)->sw_gen0[gen - 1])
338#define DI_SW_GEN1(di, gen)	(&DI_REG(di)->sw_gen1[gen - 1])
339#define DI_STP_REP(di, gen)	(&DI_REG(di)->stp_rep[(gen - 1) / 2])
340#define DI_STP_REP9(di)		(&DI_REG(di)->stp_rep9)
341#define DI_SYNC_AS_GEN(di)	(&DI_REG(di)->sync_as)
342#define DI_DW_GEN(di, gen)	(&DI_REG(di)->dw_gen[gen])
343#define DI_DW_SET(di, gen, set)	(&DI_REG(di)->dw_set[gen + 12 * set])
344#define DI_POL(di)		(&DI_REG(di)->pol)
345#define DI_SCR_CONF(di)		(&DI_REG(di)->scr_conf)
346
347#define DMFC_REG		((struct ipu_dmfc *)(IPU_CTRL_BASE_ADDR + \
348				IPU_DMFC_REG_BASE))
349#define DMFC_WR_CHAN		(&DMFC_REG->wr_chan)
350#define DMFC_WR_CHAN_DEF	(&DMFC_REG->wr_chan_def)
351#define DMFC_DP_CHAN		(&DMFC_REG->dp_chan)
352#define DMFC_DP_CHAN_DEF	(&DMFC_REG->dp_chan_def)
353#define DMFC_GENERAL1		(&DMFC_REG->general[0])
354#define DMFC_IC_CTRL		(&DMFC_REG->ic_ctrl)
355
356
357#define DC_REG			((struct ipu_dc *)(IPU_CTRL_BASE_ADDR + \
358				IPU_DC_REG_BASE))
359#define DC_MAP_CONF_PTR(n)	(&DC_REG->dc_map_ptr[n / 2])
360#define DC_MAP_CONF_VAL(n)	(&DC_REG->dc_map_val[n / 2])
361
362
363static inline struct ipu_dc_ch *dc_ch_offset(int ch)
364{
365	switch (ch) {
366	case 0:
367	case 1:
368	case 2:
369		return &DC_REG->dc_ch0_1_2[ch];
370	case 5:
371	case 6:
372		return &DC_REG->dc_ch5_6[ch - 5];
373	case 8:
374		return &DC_REG->dc_ch8;
375	case 9:
376		return &DC_REG->dc_ch9;
377	default:
378		printf("%s: invalid channel %d\n", __func__, ch);
379		return NULL;
380	}
381
382}
383
384#define DC_RL_CH(ch, evt)	(&dc_ch_offset(ch)->rl[evt / 2])
385
386#define DC_WR_CH_CONF(ch)	(&dc_ch_offset(ch)->wr_ch_conf)
387#define DC_WR_CH_ADDR(ch)	(&dc_ch_offset(ch)->wr_ch_addr)
388
389#define DC_WR_CH_CONF_1		DC_WR_CH_CONF(1)
390#define DC_WR_CH_CONF_5		DC_WR_CH_CONF(5)
391
392#define DC_GEN			(&DC_REG->gen)
393#define DC_DISP_CONF2(disp)	(&DC_REG->disp_conf2[disp])
394#define DC_STAT			(&DC_REG->stat)
395
396#define DP_SYNC 0
397#define DP_ASYNC0 0x60
398#define DP_ASYNC1 0xBC
399
400#define DP_REG			((struct ipu_dp *)(IPU_CTRL_BASE_ADDR + \
401				IPU_DP_REG_BASE))
402#define DP_COM_CONF()		(&DP_REG->com_conf_sync)
403#define DP_GRAPH_WIND_CTRL()	(&DP_REG->graph_wind_ctrl_sync)
404#define DP_CSC_A_0()		(&DP_REG->csca_sync[0])
405#define DP_CSC_A_1()		(&DP_REG->csca_sync[1])
406#define DP_CSC_A_2()		(&DP_REG->csca_sync[2])
407#define DP_CSC_A_3()		(&DP_REG->csca_sync[3])
408
409#define DP_CSC_0()		(&DP_REG->csc_sync[0])
410#define DP_CSC_1()		(&DP_REG->csc_sync[1])
411
412/* DC template opcodes */
413#define WROD(lf)		(0x18 | (lf << 1))
414
415#endif
416