1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copied from simple-panel 4 * Copyright (c) 2016 Google, Inc 5 * Written by Simon Glass <sjg@chromium.org> 6 * Copyright (c) 2018 Sjoerd Simons <sjoerd.simons@collabora.co.uk> 7 * Modified by Moses Christopher <BollavarapuMoses.Christopher@in.bosch.com> 8 * 9 * Panel Initialization for HX8238D panel from Himax 10 * Resolution: 320x240 11 * Color-Mode: RGB 12 * 13 */ 14 15#include <dm.h> 16#include <panel.h> 17#include <spi.h> 18 19DECLARE_GLOBAL_DATA_PTR; 20 21/* Register Address */ 22#define HX8238D_OUTPUT_CTRL_ADDR 0x01 23#define HX8238D_LCD_AC_CTRL_ADDR 0x02 24#define HX8238D_POWER_CTRL_1_ADDR 0x03 25#define HX8238D_DATA_CLR_CTRL_ADDR 0X04 26#define HX8238D_FUNCTION_CTRL_ADDR 0x05 27#define HX8238D_LED_CTRL_ADDR 0x08 28#define HX8238D_CONT_BRIGHT_CTRL_ADDR 0x0A 29#define HX8238D_FRAME_CYCLE_CTRL_ADDR 0x0B 30#define HX8238D_POWER_CTRL_2_ADDR 0x0D 31#define HX8238D_POWER_CTRL_3_ADDR 0x0E 32#define HX8238D_GATE_SCAN_POS_ADDR 0x0F 33#define HX8238D_HORIZONTAL_PORCH_ADDR 0x16 34#define HX8238D_VERTICAL_PORCH_ADDR 0x17 35#define HX8238D_POWER_CTRL_4_ADDR 0x1E 36#define HX8238D_GAMMA_CTRL_1_ADDR 0x30 37#define HX8238D_GAMMA_CTRL_2_ADDR 0x31 38#define HX8238D_GAMMA_CTRL_3_ADDR 0x32 39#define HX8238D_GAMMA_CTRL_4_ADDR 0x33 40#define HX8238D_GAMMA_CTRL_5_ADDR 0x34 41#define HX8238D_GAMMA_CTRL_6_ADDR 0x35 42#define HX8238D_GAMMA_CTRL_7_ADDR 0x36 43#define HX8238D_GAMMA_CTRL_8_ADDR 0x37 44#define HX8238D_GAMMA_CTRL_9_ADDR 0x3A 45#define HX8238D_GAMMA_CTRL_10_ADDR 0x3B 46 47/* Register Data */ 48#define HX8238D_OUTPUT_CTRL 0x6300 49#define HX8238D_LCD_AC_CTRL 0x0200 50#define HX8238D_POWER_CTRL_1 0x6564 51#define HX8238D_DATA_CLR_CTRL 0x04C7 52#define HX8238D_FUNCTION_CTRL 0xA884 53#define HX8238D_LED_CTRL 0x00CE 54#define HX8238D_CONT_BRIGHT_CTRL 0x4008 55#define HX8238D_FRAME_CYCLE_CTRL 0xD400 56#define HX8238D_POWER_CTRL_2 0x3229 57#define HX8238D_POWER_CTRL_3 0x1200 58#define HX8238D_GATE_SCAN_POS 0x0000 59#define HX8238D_HORIZONTAL_PORCH 0x9F80 60#define HX8238D_VERTICAL_PORCH 0x3F02 61#define HX8238D_POWER_CTRL_4 0x005C 62 63/* Gamma Control */ 64#define HX8238D_GAMMA_CTRL_1 0x0103 65#define HX8238D_GAMMA_CTRL_2 0x0407 66#define HX8238D_GAMMA_CTRL_3 0x0705 67#define HX8238D_GAMMA_CTRL_4 0x0002 68#define HX8238D_GAMMA_CTRL_5 0x0505 69#define HX8238D_GAMMA_CTRL_6 0x0303 70#define HX8238D_GAMMA_CTRL_7 0x0707 71#define HX8238D_GAMMA_CTRL_8 0x0100 72#define HX8238D_GAMMA_CTRL_9 0x1F00 73#define HX8238D_GAMMA_CTRL_10 0x000F 74 75/* Primary SPI register identification, 011100 */ 76/* Select register, RS=0, RS=0 */ 77/* Write register, RS=1, RW=0 */ 78#define HX8238D_PRIMARY_SELECT_REG 0x70 79#define HX8238D_PRIMARY_WRITE_REG (HX8238D_PRIMARY_SELECT_REG | (0x1 << 1)) 80 81#define HX8238D_REG_BIT_LEN 24 82 83struct hx8238d_priv { 84 struct spi_slave *spi; 85}; 86 87static int hx8238d_ofdata_to_platdata(struct udevice *dev) 88{ 89 struct hx8238d_priv *priv = dev_get_priv(dev); 90 91 priv->spi = dev_get_parent_priv(dev); 92 93 return 0; 94} 95 96/* data[0] => REGISTER ADDRESS */ 97/* data[1] => REGISTER VALUE */ 98struct hx8238d_command { 99 u16 data[2]; 100}; 101 102static struct hx8238d_command hx8238d_init_commands[] = { 103 { .data = { HX8238D_OUTPUT_CTRL_ADDR, HX8238D_OUTPUT_CTRL } }, 104 { .data = { HX8238D_LCD_AC_CTRL_ADDR, HX8238D_LCD_AC_CTRL } }, 105 { .data = { HX8238D_POWER_CTRL_1_ADDR, HX8238D_POWER_CTRL_1 } }, 106 { .data = { HX8238D_DATA_CLR_CTRL_ADDR, HX8238D_DATA_CLR_CTRL } }, 107 { .data = { HX8238D_FUNCTION_CTRL_ADDR, HX8238D_FUNCTION_CTRL } }, 108 { .data = { HX8238D_LED_CTRL_ADDR, HX8238D_LED_CTRL } }, 109 { .data = { HX8238D_CONT_BRIGHT_CTRL_ADDR, HX8238D_CONT_BRIGHT_CTRL } }, 110 { .data = { HX8238D_FRAME_CYCLE_CTRL_ADDR, HX8238D_FRAME_CYCLE_CTRL } }, 111 { .data = { HX8238D_POWER_CTRL_2_ADDR, HX8238D_POWER_CTRL_2 } }, 112 { .data = { HX8238D_POWER_CTRL_3_ADDR, HX8238D_POWER_CTRL_3 } }, 113 { .data = { HX8238D_GATE_SCAN_POS_ADDR, HX8238D_GATE_SCAN_POS } }, 114 { .data = { HX8238D_HORIZONTAL_PORCH_ADDR, HX8238D_HORIZONTAL_PORCH } }, 115 { .data = { HX8238D_VERTICAL_PORCH_ADDR, HX8238D_VERTICAL_PORCH } }, 116 { .data = { HX8238D_POWER_CTRL_4_ADDR, HX8238D_POWER_CTRL_4 } }, 117 { .data = { HX8238D_GAMMA_CTRL_1_ADDR, HX8238D_GAMMA_CTRL_1 } }, 118 { .data = { HX8238D_GAMMA_CTRL_2_ADDR, HX8238D_GAMMA_CTRL_2 } }, 119 { .data = { HX8238D_GAMMA_CTRL_3_ADDR, HX8238D_GAMMA_CTRL_3 } }, 120 { .data = { HX8238D_GAMMA_CTRL_4_ADDR, HX8238D_GAMMA_CTRL_4 } }, 121 { .data = { HX8238D_GAMMA_CTRL_5_ADDR, HX8238D_GAMMA_CTRL_5 } }, 122 { .data = { HX8238D_GAMMA_CTRL_6_ADDR, HX8238D_GAMMA_CTRL_6 } }, 123 { .data = { HX8238D_GAMMA_CTRL_7_ADDR, HX8238D_GAMMA_CTRL_7 } }, 124 { .data = { HX8238D_GAMMA_CTRL_8_ADDR, HX8238D_GAMMA_CTRL_8 } }, 125 { .data = { HX8238D_GAMMA_CTRL_9_ADDR, HX8238D_GAMMA_CTRL_9 } }, 126 { .data = { HX8238D_GAMMA_CTRL_10_ADDR, HX8238D_GAMMA_CTRL_10 } }, 127}; 128 129/* 130 * Generate Primary Register Buffer for Register Select and Register Write 131 * First 6 MSB bits of Primary Register is represented with 011100 132 * 133 */ 134static void hx8238d_generate_reg_buffers(struct hx8238d_command command, 135 u8 *sr_buf, uint8_t *wr_buf) 136{ 137 struct hx8238d_command cmd = command; 138 139 sr_buf[0] = HX8238D_PRIMARY_SELECT_REG; 140 sr_buf[1] = (cmd.data[0] >> 8) & 0xff; 141 sr_buf[2] = (cmd.data[0]) & 0xff; 142 143 wr_buf[0] = HX8238D_PRIMARY_WRITE_REG; 144 wr_buf[1] = (cmd.data[1] >> 8) & 0xff; 145 wr_buf[2] = (cmd.data[1]) & 0xff; 146} 147 148static int hx8238d_probe(struct udevice *dev) 149{ 150 struct hx8238d_priv *priv = dev_get_priv(dev); 151 int ret; 152 153 ret = spi_claim_bus(priv->spi); 154 if (ret) { 155 debug("Failed to claim bus: %d\n", ret); 156 return ret; 157 } 158 159 for (int i = 0; i < ARRAY_SIZE(hx8238d_init_commands); i++) { 160 u8 sr_buf[3], wr_buf[3]; 161 const struct hx8238d_command cmd = hx8238d_init_commands[i]; 162 163 hx8238d_generate_reg_buffers(cmd, sr_buf, wr_buf); 164 ret = spi_xfer(priv->spi, HX8238D_REG_BIT_LEN, sr_buf, NULL, 165 SPI_XFER_BEGIN | SPI_XFER_END); 166 if (ret) { 167 debug("Failed to select register %d\n", ret); 168 goto free; 169 } 170 171 ret = spi_xfer(priv->spi, HX8238D_REG_BIT_LEN, wr_buf, NULL, 172 SPI_XFER_BEGIN | SPI_XFER_END); 173 if (ret) { 174 debug("Failed to write value %d\n", ret); 175 goto free; 176 } 177 } 178 179free: 180 spi_release_bus(priv->spi); 181 return ret; 182} 183 184static const struct udevice_id hx8238d_ids[] = { 185 { .compatible = "himax,hx8238d" }, 186 { } 187}; 188 189U_BOOT_DRIVER(hx8238d) = { 190 .name = "hx8238d", 191 .id = UCLASS_PANEL, 192 .of_match = hx8238d_ids, 193 .of_to_plat = hx8238d_ofdata_to_platdata, 194 .probe = hx8238d_probe, 195 .priv_auto = sizeof(struct hx8238d_priv), 196}; 197