1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Driver for AT91/AT32 LCD Controller 4 * 5 * Copyright (C) 2007 Atmel Corporation 6 */ 7 8#include <atmel_lcd.h> 9#include <dm.h> 10#include <fdtdec.h> 11#include <log.h> 12#include <part.h> 13#include <video.h> 14#include <asm/global_data.h> 15#include <asm/io.h> 16#include <asm/arch/gpio.h> 17#include <asm/arch/clk.h> 18#include <bmp_layout.h> 19#include <atmel_lcdc.h> 20#include <linux/delay.h> 21 22DECLARE_GLOBAL_DATA_PTR; 23 24enum { 25 /* Maximum LCD size we support */ 26 LCD_MAX_WIDTH = 1366, 27 LCD_MAX_HEIGHT = 768, 28 LCD_MAX_LOG2_BPP = VIDEO_BPP16, 29}; 30 31struct atmel_fb_priv { 32 struct display_timing timing; 33}; 34 35/* configurable parameters */ 36#define ATMEL_LCDC_CVAL_DEFAULT 0xc8 37#define ATMEL_LCDC_DMA_BURST_LEN 8 38#ifndef ATMEL_LCDC_GUARD_TIME 39#define ATMEL_LCDC_GUARD_TIME 1 40#endif 41 42#if defined(CONFIG_AT91SAM9263) 43#define ATMEL_LCDC_FIFO_SIZE 2048 44#else 45#define ATMEL_LCDC_FIFO_SIZE 512 46#endif 47 48#define lcdc_readl(mmio, reg) __raw_readl((mmio)+(reg)) 49#define lcdc_writel(mmio, reg, val) __raw_writel((val), (mmio)+(reg)) 50 51static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix, 52 bool tft, bool cont_pol_low, ulong lcdbase) 53{ 54 unsigned long value; 55 void *reg = (void *)addr; 56 57 /* Turn off the LCD controller and the DMA controller */ 58 lcdc_writel(reg, ATMEL_LCDC_PWRCON, 59 ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET); 60 61 /* Wait for the LCDC core to become idle */ 62 while (lcdc_readl(reg, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY) 63 udelay(10); 64 65 lcdc_writel(reg, ATMEL_LCDC_DMACON, 0); 66 67 /* Reset LCDC DMA */ 68 lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST); 69 70 /* ...set frame size and burst length = 8 words (?) */ 71 value = (timing->hactive.typ * timing->vactive.typ * 72 (1 << bpix)) / 32; 73 value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET); 74 lcdc_writel(reg, ATMEL_LCDC_DMAFRMCFG, value); 75 76 /* Set pixel clock */ 77 value = get_lcdc_clk_rate(0) / timing->pixelclock.typ; 78 if (get_lcdc_clk_rate(0) % timing->pixelclock.typ) 79 value++; 80 value = (value / 2) - 1; 81 82 if (!value) { 83 lcdc_writel(reg, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS); 84 } else 85 lcdc_writel(reg, ATMEL_LCDC_LCDCON1, 86 value << ATMEL_LCDC_CLKVAL_OFFSET); 87 88 /* Initialize control register 2 */ 89 value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE; 90 if (tft) 91 value |= ATMEL_LCDC_DISTYPE_TFT; 92 93 if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH)) 94 value |= ATMEL_LCDC_INVLINE_INVERTED; 95 if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH)) 96 value |= ATMEL_LCDC_INVFRAME_INVERTED; 97 value |= bpix << 5; 98 lcdc_writel(reg, ATMEL_LCDC_LCDCON2, value); 99 100 /* Vertical timing */ 101 value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET; 102 value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET; 103 value |= timing->vfront_porch.typ; 104 /* Magic! (Datasheet says "Bit 31 must be written to 1") */ 105 value |= 1U << 31; 106 lcdc_writel(reg, ATMEL_LCDC_TIM1, value); 107 108 /* Horizontal timing */ 109 value = (timing->hfront_porch.typ - 1) << ATMEL_LCDC_HFP_OFFSET; 110 value |= (timing->hsync_len.typ - 1) << ATMEL_LCDC_HPW_OFFSET; 111 value |= (timing->hback_porch.typ - 1); 112 lcdc_writel(reg, ATMEL_LCDC_TIM2, value); 113 114 /* Display size */ 115 value = (timing->hactive.typ - 1) << ATMEL_LCDC_HOZVAL_OFFSET; 116 value |= timing->vactive.typ - 1; 117 lcdc_writel(reg, ATMEL_LCDC_LCDFRMCFG, value); 118 119 /* FIFO Threshold: Use formula from data sheet */ 120 value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3); 121 lcdc_writel(reg, ATMEL_LCDC_FIFO, value); 122 123 /* Toggle LCD_MODE every frame */ 124 lcdc_writel(reg, ATMEL_LCDC_MVAL, 0); 125 126 /* Disable all interrupts */ 127 lcdc_writel(reg, ATMEL_LCDC_IDR, ~0UL); 128 129 /* Set contrast */ 130 value = ATMEL_LCDC_PS_DIV8 | 131 ATMEL_LCDC_ENA_PWMENABLE; 132 if (!cont_pol_low) 133 value |= ATMEL_LCDC_POL_POSITIVE; 134 lcdc_writel(reg, ATMEL_LCDC_CONTRAST_CTR, value); 135 lcdc_writel(reg, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT); 136 137 /* Set framebuffer DMA base address and pixel offset */ 138 lcdc_writel(reg, ATMEL_LCDC_DMABADDR1, lcdbase); 139 140 lcdc_writel(reg, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN); 141 lcdc_writel(reg, ATMEL_LCDC_PWRCON, 142 (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR); 143} 144 145static int atmel_fb_lcd_probe(struct udevice *dev) 146{ 147 struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); 148 struct video_priv *uc_priv = dev_get_uclass_priv(dev); 149 struct atmel_fb_priv *priv = dev_get_priv(dev); 150 struct display_timing *timing = &priv->timing; 151 152 /* 153 * For now some values are hard-coded. We could use the device tree 154 * bindings in simple-framebuffer.txt to specify the format/bpp and 155 * some Atmel-specific binding for tft and cont_pol_low. 156 */ 157 atmel_fb_init(ATMEL_BASE_LCDC, timing, VIDEO_BPP16, true, false, 158 uc_plat->base); 159 uc_priv->xsize = timing->hactive.typ; 160 uc_priv->ysize = timing->vactive.typ; 161 uc_priv->bpix = VIDEO_BPP16; 162 video_set_flush_dcache(dev, true); 163 debug("LCD frame buffer at %lx, size %x, %dx%d pixels\n", uc_plat->base, 164 uc_plat->size, uc_priv->xsize, uc_priv->ysize); 165 166 return 0; 167} 168 169static int atmel_fb_of_to_plat(struct udevice *dev) 170{ 171 struct atmel_lcd_plat *plat = dev_get_plat(dev); 172 struct atmel_fb_priv *priv = dev_get_priv(dev); 173 struct display_timing *timing = &priv->timing; 174 const void *blob = gd->fdt_blob; 175 176 if (fdtdec_decode_display_timing(blob, dev_of_offset(dev), 177 plat->timing_index, timing)) { 178 debug("%s: Failed to decode display timing\n", __func__); 179 return -EINVAL; 180 } 181 182 return 0; 183} 184 185static int atmel_fb_lcd_bind(struct udevice *dev) 186{ 187 struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); 188 189 uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT * 190 (1 << VIDEO_BPP16) / 8; 191 debug("%s: Frame buffer size %x\n", __func__, uc_plat->size); 192 193 return 0; 194} 195 196static const struct udevice_id atmel_fb_lcd_ids[] = { 197 { .compatible = "atmel,at91sam9g45-lcdc" }, 198 { } 199}; 200 201U_BOOT_DRIVER(atmel_fb) = { 202 .name = "atmel_fb", 203 .id = UCLASS_VIDEO, 204 .of_match = atmel_fb_lcd_ids, 205 .bind = atmel_fb_lcd_bind, 206 .of_to_plat = atmel_fb_of_to_plat, 207 .probe = atmel_fb_lcd_probe, 208 .plat_auto = sizeof(struct atmel_lcd_plat), 209 .priv_auto = sizeof(struct atmel_fb_priv), 210}; 211