1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2008 by NXP Semiconductors 4 * @Author: Based on code by Kevin Wells 5 * @Descr: USB driver - Embedded Artists LPC3250 OEM Board support functions 6 * 7 * Copyright (c) 2015 Tyco Fire Protection Products. 8 */ 9 10#include <common.h> 11#include <dm.h> 12#include <errno.h> 13#include <init.h> 14#include <log.h> 15#include <wait_bit.h> 16#include <asm/io.h> 17#include <asm/arch/cpu.h> 18#include <asm/arch/clk.h> 19#include <asm/arch/i2c.h> 20#include <usb.h> 21#include <i2c.h> 22 23/* OTG I2C controller module register structures */ 24struct otgi2c_regs { 25 u32 otg_i2c_txrx; /* OTG I2C Tx/Rx Data FIFO */ 26 u32 otg_i2c_stat; /* OTG I2C Status Register */ 27 u32 otg_i2c_ctrl; /* OTG I2C Control Register */ 28 u32 otg_i2c_clk_hi; /* OTG I2C Clock Divider high */ 29 u32 otg_i2c_clk_lo; /* OTG I2C Clock Divider low */ 30}; 31 32/* OTG controller module register structures */ 33struct otg_regs { 34 u32 reserved1[64]; 35 u32 otg_int_sts; /* OTG int status register */ 36 u32 otg_int_enab; /* OTG int enable register */ 37 u32 otg_int_set; /* OTG int set register */ 38 u32 otg_int_clr; /* OTG int clear register */ 39 u32 otg_sts_ctrl; /* OTG status/control register */ 40 u32 otg_timer; /* OTG timer register */ 41 u32 reserved2[122]; 42 struct otgi2c_regs otg_i2c; 43 u32 reserved3[824]; 44 u32 otg_clk_ctrl; /* OTG clock control reg */ 45 u32 otg_clk_sts; /* OTG clock status reg */ 46}; 47 48/* otg_sts_ctrl register definitions */ 49#define OTG_HOST_EN (1 << 0) /* Enable host mode */ 50 51/* otg_clk_ctrl and otg_clk_sts register definitions */ 52#define OTG_CLK_AHB_EN (1 << 4) /* Enable AHB clock */ 53#define OTG_CLK_OTG_EN (1 << 3) /* Enable OTG clock */ 54#define OTG_CLK_I2C_EN (1 << 2) /* Enable I2C clock */ 55#define OTG_CLK_HOST_EN (1 << 0) /* Enable host clock */ 56 57/* ISP1301 USB transceiver I2C registers */ 58#define MC1_SPEED_REG (1 << 0) 59#define MC1_DAT_SE0 (1 << 2) 60#define MC1_UART_EN (1 << 6) 61 62#define MC2_SPD_SUSP_CTRL (1 << 1) 63#define MC2_BI_DI (1 << 2) 64#define MC2_PSW_EN (1 << 6) 65 66#define OTG1_DP_PULLUP (1 << 0) 67#define OTG1_DM_PULLUP (1 << 1) 68#define OTG1_DP_PULLDOWN (1 << 2) 69#define OTG1_DM_PULLDOWN (1 << 3) 70#define OTG1_VBUS_DRV (1 << 5) 71 72#define ISP1301_I2C_ADDR CFG_USB_ISP1301_I2C_ADDR 73 74#define ISP1301_I2C_MODE_CONTROL_1_SET 0x04 75#define ISP1301_I2C_MODE_CONTROL_1_CLR 0x05 76#define ISP1301_I2C_MODE_CONTROL_2_SET 0x12 77#define ISP1301_I2C_MODE_CONTROL_2_CLR 0x13 78#define ISP1301_I2C_OTG_CONTROL_1_SET 0x06 79#define ISP1301_I2C_OTG_CONTROL_1_CLR 0x07 80#define ISP1301_I2C_INTERRUPT_LATCH_CLR 0x0B 81#define ISP1301_I2C_INTERRUPT_FALLING_CLR 0x0D 82#define ISP1301_I2C_INTERRUPT_RISING_CLR 0x0F 83 84static struct otg_regs *otg = (struct otg_regs *)USB_BASE; 85static struct clk_pm_regs *clk_pwr = (struct clk_pm_regs *)CLK_PM_BASE; 86 87static int isp1301_set_value(struct udevice *dev, int reg, u8 value) 88{ 89#if !CONFIG_IS_ENABLED(DM_I2C) 90 return i2c_write(ISP1301_I2C_ADDR, reg, 1, &value, 1); 91#else 92 return dm_i2c_write(dev, reg, &value, 1); 93#endif 94} 95 96static void isp1301_configure(struct udevice *dev) 97{ 98#if !CONFIG_IS_ENABLED(DM_I2C) 99 i2c_set_bus_num(I2C_2); 100#endif 101 102 /* 103 * LPC32XX only supports DAT_SE0 USB mode 104 * This sequence is important 105 */ 106 107 /* Disable transparent UART mode first */ 108 isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_CLR, MC1_UART_EN); 109 110 isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_CLR, ~MC1_SPEED_REG); 111 isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_SET, MC1_SPEED_REG); 112 isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_2_CLR, ~0); 113 isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_2_SET, 114 MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL); 115 116 isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_CLR, ~0); 117 isp1301_set_value(dev, ISP1301_I2C_MODE_CONTROL_1_SET, MC1_DAT_SE0); 118 isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_SET, 119 OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN); 120 isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_CLR, 121 OTG1_DM_PULLUP | OTG1_DP_PULLUP); 122 isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_LATCH_CLR, ~0); 123 isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_FALLING_CLR, ~0); 124 isp1301_set_value(dev, ISP1301_I2C_INTERRUPT_RISING_CLR, ~0); 125 126 /* Enable usb_need_clk clock after transceiver is initialized */ 127 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBDVND_EN); 128} 129 130static int usbpll_setup(void) 131{ 132 u32 ret; 133 134 /* make sure clocks are disabled */ 135 clrbits_le32(&clk_pwr->usb_ctrl, 136 CLK_USBCTRL_CLK_EN1 | CLK_USBCTRL_CLK_EN2); 137 138 /* start PLL clock input */ 139 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_CLK_EN1); 140 141 /* Setup PLL. */ 142 setbits_le32(&clk_pwr->usb_ctrl, 143 CLK_USBCTRL_FDBK_PLUS1(192 - 1)); 144 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_POSTDIV_2POW(0x01)); 145 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_PWRUP); 146 147 ret = wait_for_bit_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_STS, 148 true, CONFIG_SYS_HZ, false); 149 if (ret) 150 return ret; 151 152 /* enable PLL output */ 153 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_CLK_EN2); 154 155 return 0; 156} 157 158int usb_cpu_init(void) 159{ 160 u32 ret; 161 struct udevice *dev = NULL; 162 163#if CONFIG_IS_ENABLED(DM_I2C) 164 ret = i2c_get_chip_for_busnum(I2C_2, ISP1301_I2C_ADDR, 1, &dev); 165 if (ret) { 166 debug("%s: No bus %d\n", __func__, I2C_2); 167 return ret; 168 } 169#endif 170 171 /* 172 * USB pins routing setup is done by "lpc32xx_usb_init()" and should 173 * be call by board "board_init()" or "misc_init_r()" functions. 174 */ 175 176 /* enable AHB slave USB clock */ 177 setbits_le32(&clk_pwr->usb_ctrl, 178 CLK_USBCTRL_HCLK_EN | CLK_USBCTRL_BUS_KEEPER); 179 180 /* enable I2C clock */ 181 writel(OTG_CLK_I2C_EN, &otg->otg_clk_ctrl); 182 ret = wait_for_bit_le32(&otg->otg_clk_sts, OTG_CLK_I2C_EN, true, 183 CONFIG_SYS_HZ, false); 184 if (ret) 185 return ret; 186 187 /* Configure ISP1301 */ 188 isp1301_configure(dev); 189 190 /* setup USB clocks and PLL */ 191 ret = usbpll_setup(); 192 if (ret) 193 return ret; 194 195 /* enable usb_host_need_clk */ 196 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBHSTND_EN); 197 198 /* enable all needed USB clocks */ 199 const u32 mask = OTG_CLK_AHB_EN | OTG_CLK_OTG_EN | 200 OTG_CLK_I2C_EN | OTG_CLK_HOST_EN; 201 writel(mask, &otg->otg_clk_ctrl); 202 203 ret = wait_for_bit_le32(&otg->otg_clk_sts, mask, true, 204 CONFIG_SYS_HZ, false); 205 if (ret) 206 return ret; 207 208 setbits_le32(&otg->otg_sts_ctrl, OTG_HOST_EN); 209 isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV); 210 211 return 0; 212} 213 214int usb_cpu_stop(void) 215{ 216 struct udevice *dev = NULL; 217 int ret = 0; 218 219#if CONFIG_IS_ENABLED(DM_I2C) 220 ret = i2c_get_chip_for_busnum(I2C_2, ISP1301_I2C_ADDR, 1, &dev); 221 if (ret) { 222 debug("%s: No bus %d\n", __func__, I2C_2); 223 return ret; 224 } 225#endif 226 227 /* vbus off */ 228 isp1301_set_value(dev, ISP1301_I2C_OTG_CONTROL_1_SET, OTG1_VBUS_DRV); 229 230 clrbits_le32(&otg->otg_sts_ctrl, OTG_HOST_EN); 231 232 clrbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_HCLK_EN); 233 234 return ret; 235} 236 237int usb_cpu_init_fail(void) 238{ 239 return usb_cpu_stop(); 240} 241