1/*
2 * Copyright 2011, Marvell Semiconductor Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
6#ifndef __GADGET__CI_UDC_H__
7#define __GADGET__CI_UDC_H__
8
9#define NUM_ENDPOINTS		6
10
11#ifdef CONFIG_CI_UDC_HAS_HOSTPC
12struct ci_udc {
13	u32 usbcmd;		/* 0x130 */
14	u32 usbsts;		/* 0x134 */
15	u32 pad1[3];
16	u32 devaddr;		/* 0x144 */
17	u32 epinitaddr;		/* 0x148 */
18	u32 pad2[10];
19	u32 portsc;		/* 0x174 */
20	u32 pad178[(0x1b4 - (0x174 + 4)) / 4];
21	u32 hostpc1_devlc;	/* 0x1b4 */
22	u32 pad1b8[(0x1f8 - (0x1b4 + 4)) / 4];
23	u32 usbmode;		/* 0x1f8 */
24	u32 pad1fc[(0x208 - (0x1f8 + 4)) / 4];
25	u32 epsetupstat;	/* 0x208 */
26	u32 epprime;		/* 0x20c */
27	u32 epflush;		/* 0x210 */
28	u32 epstat;		/* 0x214 */
29	u32 epcomp;		/* 0x218 */
30	u32 epctrl[16];		/* 0x21c */
31};
32#else
33struct ci_udc {
34	u32 usbcmd;		/* 0x140 */
35	u32 usbsts;		/* 0x144 */
36	u32 pad1[3];
37	u32 devaddr;		/* 0x154 */
38	u32 epinitaddr;		/* 0x158 */
39	u32 pad2[10];
40	u32 portsc;		/* 0x184 */
41	u32 pad3[8];
42	u32 usbmode;		/* 0x1a8 */
43	u32 epstat;		/* 0x1ac */
44	u32 epprime;		/* 0x1b0 */
45	u32 epflush;		/* 0x1b4 */
46	u32 pad4;
47	u32 epcomp;		/* 0x1bc */
48	u32 epctrl[16];		/* 0x1c0 */
49};
50
51#define PTS_ENABLE	2
52#define PTS(x)		(((x) & 0x3) << 30)
53#define PFSC		(1 << 24)
54#endif
55
56#define MICRO_8FRAME	0x8
57#define USBCMD_ITC(x)	((((x) > 0xff) ? 0xff : x) << 16)
58#define USBCMD_FS2	(1 << 15)
59#define USBCMD_RST	(1 << 1)
60#define USBCMD_RUN	(1)
61
62#define STS_SLI		(1 << 8)
63#define STS_URI		(1 << 6)
64#define STS_PCI		(1 << 2)
65#define STS_UEI		(1 << 1)
66#define STS_UI		(1 << 0)
67
68#define USBMODE_DEVICE	2
69
70#define EPT_TX(x)	(1 << (((x) & 0xffff) + 16))
71#define EPT_RX(x)	(1 << ((x) & 0xffff))
72
73#define CTRL_TXE	(1 << 23)
74#define CTRL_TXR	(1 << 22)
75#define CTRL_RXE	(1 << 7)
76#define CTRL_RXR	(1 << 6)
77#define CTRL_TXT_BULK	(2 << 18)
78#define CTRL_RXT_BULK	(2 << 2)
79
80struct ci_req {
81	struct usb_request	req;
82	struct list_head	queue;
83	/* Bounce buffer allocated if needed to align the transfer */
84	uint8_t *b_buf;
85	uint32_t b_len;
86	/* Buffer for the current transfer. Either req.buf/len or b_buf/len */
87	uint8_t *hw_buf;
88	uint32_t hw_len;
89	uint32_t dtd_count;
90};
91
92struct ci_ep {
93	struct usb_ep ep;
94	struct list_head queue;
95	bool req_primed;
96	const struct usb_endpoint_descriptor *desc;
97};
98
99struct ci_drv {
100	struct usb_gadget		gadget;
101	struct ci_req			*ep0_req;
102	bool				ep0_data_phase;
103	struct usb_gadget_driver	*driver;
104	struct ehci_ctrl		*ctrl;
105	struct ept_queue_head		*epts;
106	uint8_t				*items_mem;
107	struct ci_ep			ep[NUM_ENDPOINTS];
108};
109
110struct ept_queue_head {
111	unsigned config;
112	unsigned current;	/* read-only */
113
114	unsigned next;
115	unsigned info;
116	unsigned page0;
117	unsigned page1;
118	unsigned page2;
119	unsigned page3;
120	unsigned page4;
121	unsigned reserved_0;
122
123	unsigned char setup_data[8];
124
125	unsigned reserved_1;
126	unsigned reserved_2;
127	unsigned reserved_3;
128	unsigned reserved_4;
129};
130
131#define CFG_MAX_PKT(n)	((n) << 16)
132#define CFG_ZLT		(1 << 29)	/* stop on zero-len xfer */
133#define CFG_IOS		(1 << 15)	/* IRQ on setup */
134
135struct ept_queue_item {
136	unsigned next;
137	unsigned info;
138	unsigned page0;
139	unsigned page1;
140	unsigned page2;
141	unsigned page3;
142	unsigned page4;
143	unsigned reserved;
144};
145
146#define TERMINATE 1
147#define INFO_BYTES(n)		((n) << 16)
148#define INFO_IOC		(1 << 15)
149#define INFO_ACTIVE		(1 << 7)
150#define INFO_HALTED		(1 << 6)
151#define INFO_BUFFER_ERROR	(1 << 5)
152#define INFO_TX_ERROR		(1 << 3)
153#endif
154