1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (c) 2015 Google, Inc 4 * Copyright (c) 2011 The Chromium OS Authors. 5 * Copyright (C) 2009 NVIDIA, Corporation 6 * Copyright (C) 2007-2008 SMSC (Steve Glendinning) 7 */ 8 9#include <common.h> 10#include <dm.h> 11#include <errno.h> 12#include <log.h> 13#include <malloc.h> 14#include <memalign.h> 15#include <net.h> 16#include <usb.h> 17#include <asm/unaligned.h> 18#include <linux/delay.h> 19#include <linux/mii.h> 20#include "usb_ether.h" 21 22/* SMSC LAN95xx based USB 2.0 Ethernet Devices */ 23 24/* LED defines */ 25#define LED_GPIO_CFG (0x24) 26#define LED_GPIO_CFG_SPD_LED (0x01000000) 27#define LED_GPIO_CFG_LNK_LED (0x00100000) 28#define LED_GPIO_CFG_FDX_LED (0x00010000) 29 30/* Tx command words */ 31#define TX_CMD_A_FIRST_SEG_ 0x00002000 32#define TX_CMD_A_LAST_SEG_ 0x00001000 33 34/* Rx status word */ 35#define RX_STS_FL_ 0x3FFF0000 /* Frame Length */ 36#define RX_STS_ES_ 0x00008000 /* Error Summary */ 37 38/* SCSRs */ 39#define ID_REV 0x00 40 41#define INT_STS 0x08 42 43#define TX_CFG 0x10 44#define TX_CFG_ON_ 0x00000004 45 46#define HW_CFG 0x14 47#define HW_CFG_BIR_ 0x00001000 48#define HW_CFG_RXDOFF_ 0x00000600 49#define HW_CFG_MEF_ 0x00000020 50#define HW_CFG_BCE_ 0x00000002 51#define HW_CFG_LRST_ 0x00000008 52 53#define PM_CTRL 0x20 54#define PM_CTL_PHY_RST_ 0x00000010 55 56#define AFC_CFG 0x2C 57 58/* 59 * Hi watermark = 15.5Kb (~10 mtu pkts) 60 * low watermark = 3k (~2 mtu pkts) 61 * backpressure duration = ~ 350us 62 * Apply FC on any frame. 63 */ 64#define AFC_CFG_DEFAULT 0x00F830A1 65 66#define E2P_CMD 0x30 67#define E2P_CMD_BUSY_ 0x80000000 68#define E2P_CMD_READ_ 0x00000000 69#define E2P_CMD_TIMEOUT_ 0x00000400 70#define E2P_CMD_LOADED_ 0x00000200 71#define E2P_CMD_ADDR_ 0x000001FF 72 73#define E2P_DATA 0x34 74 75#define BURST_CAP 0x38 76 77#define INT_EP_CTL 0x68 78#define INT_EP_CTL_PHY_INT_ 0x00008000 79 80#define BULK_IN_DLY 0x6C 81 82/* MAC CSRs */ 83#define MAC_CR 0x100 84#define MAC_CR_MCPAS_ 0x00080000 85#define MAC_CR_PRMS_ 0x00040000 86#define MAC_CR_HPFILT_ 0x00002000 87#define MAC_CR_TXEN_ 0x00000008 88#define MAC_CR_RXEN_ 0x00000004 89 90#define ADDRH 0x104 91 92#define ADDRL 0x108 93 94#define MII_ADDR 0x114 95#define MII_WRITE_ 0x02 96#define MII_BUSY_ 0x01 97#define MII_READ_ 0x00 /* ~of MII Write bit */ 98 99#define MII_DATA 0x118 100 101#define FLOW 0x11C 102 103#define VLAN1 0x120 104 105#define COE_CR 0x130 106#define Tx_COE_EN_ 0x00010000 107#define Rx_COE_EN_ 0x00000001 108 109/* Vendor-specific PHY Definitions */ 110#define PHY_INT_SRC 29 111 112#define PHY_INT_MASK 30 113#define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040) 114#define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010) 115#define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \ 116 PHY_INT_MASK_LINK_DOWN_) 117 118/* USB Vendor Requests */ 119#define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 120#define USB_VENDOR_REQUEST_READ_REGISTER 0xA1 121 122/* Some extra defines */ 123#define HS_USB_PKT_SIZE 512 124#define FS_USB_PKT_SIZE 64 125/* 5/33 is lower limit for BURST_CAP to work */ 126#define DEFAULT_HS_BURST_CAP_SIZE (5 * HS_USB_PKT_SIZE) 127#define DEFAULT_FS_BURST_CAP_SIZE (33 * FS_USB_PKT_SIZE) 128#define DEFAULT_BULK_IN_DELAY 0x00002000 129#define MAX_SINGLE_PACKET_SIZE 2048 130#define EEPROM_MAC_OFFSET 0x01 131#define SMSC95XX_INTERNAL_PHY_ID 1 132#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */ 133 134/* local defines */ 135#define SMSC95XX_BASE_NAME "sms" 136#define USB_CTRL_SET_TIMEOUT 5000 137#define USB_CTRL_GET_TIMEOUT 5000 138#define USB_BULK_SEND_TIMEOUT 5000 139#define USB_BULK_RECV_TIMEOUT 5000 140 141#define RX_URB_SIZE DEFAULT_HS_BURST_CAP_SIZE 142#define PHY_CONNECT_TIMEOUT 5000 143 144#define TURBO_MODE 145 146/* driver private */ 147struct smsc95xx_private { 148 struct ueth_data ueth; 149 size_t rx_urb_size; /* maximum USB URB size */ 150 u32 mac_cr; /* MAC control register value */ 151 int have_hwaddr; /* 1 if we have a hardware MAC address */ 152}; 153 154/* 155 * Smsc95xx infrastructure commands 156 */ 157static int smsc95xx_write_reg(struct usb_device *udev, u32 index, u32 data) 158{ 159 int len; 160 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); 161 162 cpu_to_le32s(&data); 163 tmpbuf[0] = data; 164 165 len = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 166 USB_VENDOR_REQUEST_WRITE_REGISTER, 167 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 168 0, index, tmpbuf, sizeof(data), 169 USB_CTRL_SET_TIMEOUT); 170 if (len != sizeof(data)) { 171 debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d", 172 index, data, len); 173 return -EIO; 174 } 175 return 0; 176} 177 178static int smsc95xx_read_reg(struct usb_device *udev, u32 index, u32 *data) 179{ 180 int len; 181 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); 182 183 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 184 USB_VENDOR_REQUEST_READ_REGISTER, 185 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 186 0, index, tmpbuf, sizeof(*data), 187 USB_CTRL_GET_TIMEOUT); 188 *data = tmpbuf[0]; 189 if (len != sizeof(*data)) { 190 debug("smsc95xx_read_reg failed: index=%d, len=%d", 191 index, len); 192 return -EIO; 193 } 194 195 le32_to_cpus(data); 196 return 0; 197} 198 199/* Loop until the read is completed with timeout */ 200static int smsc95xx_phy_wait_not_busy(struct usb_device *udev) 201{ 202 unsigned long start_time = get_timer(0); 203 u32 val; 204 205 do { 206 smsc95xx_read_reg(udev, MII_ADDR, &val); 207 if (!(val & MII_BUSY_)) 208 return 0; 209 } while (get_timer(start_time) < 1000); 210 211 return -ETIMEDOUT; 212} 213 214static int smsc95xx_mdio_read(struct usb_device *udev, int phy_id, int idx) 215{ 216 u32 val, addr; 217 218 /* confirm MII not busy */ 219 if (smsc95xx_phy_wait_not_busy(udev)) { 220 debug("MII is busy in smsc95xx_mdio_read\n"); 221 return -ETIMEDOUT; 222 } 223 224 /* set the address, index & direction (read from PHY) */ 225 addr = (phy_id << 11) | (idx << 6) | MII_READ_; 226 smsc95xx_write_reg(udev, MII_ADDR, addr); 227 228 if (smsc95xx_phy_wait_not_busy(udev)) { 229 debug("Timed out reading MII reg %02X\n", idx); 230 return -ETIMEDOUT; 231 } 232 233 smsc95xx_read_reg(udev, MII_DATA, &val); 234 235 return (u16)(val & 0xFFFF); 236} 237 238static void smsc95xx_mdio_write(struct usb_device *udev, int phy_id, int idx, 239 int regval) 240{ 241 u32 val, addr; 242 243 /* confirm MII not busy */ 244 if (smsc95xx_phy_wait_not_busy(udev)) { 245 debug("MII is busy in smsc95xx_mdio_write\n"); 246 return; 247 } 248 249 val = regval; 250 smsc95xx_write_reg(udev, MII_DATA, val); 251 252 /* set the address, index & direction (write to PHY) */ 253 addr = (phy_id << 11) | (idx << 6) | MII_WRITE_; 254 smsc95xx_write_reg(udev, MII_ADDR, addr); 255 256 if (smsc95xx_phy_wait_not_busy(udev)) 257 debug("Timed out writing MII reg %02X\n", idx); 258} 259 260static int smsc95xx_eeprom_confirm_not_busy(struct usb_device *udev) 261{ 262 unsigned long start_time = get_timer(0); 263 u32 val; 264 265 do { 266 smsc95xx_read_reg(udev, E2P_CMD, &val); 267 if (!(val & E2P_CMD_BUSY_)) 268 return 0; 269 udelay(40); 270 } while (get_timer(start_time) < 1 * 1000 * 1000); 271 272 debug("EEPROM is busy\n"); 273 return -ETIMEDOUT; 274} 275 276static int smsc95xx_wait_eeprom(struct usb_device *udev) 277{ 278 unsigned long start_time = get_timer(0); 279 u32 val; 280 281 do { 282 smsc95xx_read_reg(udev, E2P_CMD, &val); 283 if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_)) 284 break; 285 udelay(40); 286 } while (get_timer(start_time) < 1 * 1000 * 1000); 287 288 if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) { 289 debug("EEPROM read operation timeout\n"); 290 return -ETIMEDOUT; 291 } 292 return 0; 293} 294 295static int smsc95xx_read_eeprom(struct usb_device *udev, u32 offset, u32 length, 296 u8 *data) 297{ 298 u32 val; 299 int i, ret; 300 301 ret = smsc95xx_eeprom_confirm_not_busy(udev); 302 if (ret) 303 return ret; 304 305 for (i = 0; i < length; i++) { 306 val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_); 307 smsc95xx_write_reg(udev, E2P_CMD, val); 308 309 ret = smsc95xx_wait_eeprom(udev); 310 if (ret < 0) 311 return ret; 312 313 smsc95xx_read_reg(udev, E2P_DATA, &val); 314 data[i] = val & 0xFF; 315 offset++; 316 } 317 return 0; 318} 319 320/* 321 * mii_nway_restart - restart NWay (autonegotiation) for this interface 322 * 323 * Returns 0 on success, negative on error. 324 */ 325static int mii_nway_restart(struct usb_device *udev, struct ueth_data *dev) 326{ 327 int bmcr; 328 int r = -1; 329 330 /* if autoneg is off, it's an error */ 331 bmcr = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMCR); 332 333 if (bmcr & BMCR_ANENABLE) { 334 bmcr |= BMCR_ANRESTART; 335 smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, bmcr); 336 r = 0; 337 } 338 return r; 339} 340 341static int smsc95xx_phy_initialize(struct usb_device *udev, 342 struct ueth_data *dev) 343{ 344 smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, BMCR_RESET); 345 smsc95xx_mdio_write(udev, dev->phy_id, MII_ADVERTISE, 346 ADVERTISE_ALL | ADVERTISE_CSMA | 347 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); 348 349 /* read to clear */ 350 smsc95xx_mdio_read(udev, dev->phy_id, PHY_INT_SRC); 351 352 smsc95xx_mdio_write(udev, dev->phy_id, PHY_INT_MASK, 353 PHY_INT_MASK_DEFAULT_); 354 mii_nway_restart(udev, dev); 355 356 debug("phy initialised succesfully\n"); 357 return 0; 358} 359 360static int smsc95xx_init_mac_address(unsigned char *enetaddr, 361 struct usb_device *udev) 362{ 363 int ret; 364 365 /* try reading mac address from EEPROM */ 366 ret = smsc95xx_read_eeprom(udev, EEPROM_MAC_OFFSET, ETH_ALEN, enetaddr); 367 if (ret) 368 return ret; 369 370 if (is_valid_ethaddr(enetaddr)) { 371 /* eeprom values are valid so use them */ 372 debug("MAC address read from EEPROM\n"); 373 return 0; 374 } 375 376 /* 377 * No eeprom, or eeprom values are invalid. Generating a random MAC 378 * address is not safe. Just return an error. 379 */ 380 debug("Invalid MAC address read from EEPROM\n"); 381 382 return -ENXIO; 383} 384 385static int smsc95xx_write_hwaddr_common(struct usb_device *udev, 386 struct smsc95xx_private *priv, 387 unsigned char *enetaddr) 388{ 389 u32 addr_lo = get_unaligned_le32(&enetaddr[0]); 390 u32 addr_hi = get_unaligned_le16(&enetaddr[4]); 391 int ret; 392 393 /* set hardware address */ 394 debug("** %s()\n", __func__); 395 ret = smsc95xx_write_reg(udev, ADDRL, addr_lo); 396 if (ret < 0) 397 return ret; 398 399 ret = smsc95xx_write_reg(udev, ADDRH, addr_hi); 400 if (ret < 0) 401 return ret; 402 403 debug("MAC %pM\n", enetaddr); 404 priv->have_hwaddr = 1; 405 406 return 0; 407} 408 409/* Enable or disable Tx & Rx checksum offload engines */ 410static int smsc95xx_set_csums(struct usb_device *udev, int use_tx_csum, 411 int use_rx_csum) 412{ 413 u32 read_buf; 414 int ret = smsc95xx_read_reg(udev, COE_CR, &read_buf); 415 if (ret < 0) 416 return ret; 417 418 if (use_tx_csum) 419 read_buf |= Tx_COE_EN_; 420 else 421 read_buf &= ~Tx_COE_EN_; 422 423 if (use_rx_csum) 424 read_buf |= Rx_COE_EN_; 425 else 426 read_buf &= ~Rx_COE_EN_; 427 428 ret = smsc95xx_write_reg(udev, COE_CR, read_buf); 429 if (ret < 0) 430 return ret; 431 432 debug("COE_CR = 0x%08x\n", read_buf); 433 return 0; 434} 435 436static void smsc95xx_set_multicast(struct smsc95xx_private *priv) 437{ 438 /* No multicast in u-boot */ 439 priv->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_); 440} 441 442/* starts the TX path */ 443static void smsc95xx_start_tx_path(struct usb_device *udev, 444 struct smsc95xx_private *priv) 445{ 446 u32 reg_val; 447 448 /* Enable Tx at MAC */ 449 priv->mac_cr |= MAC_CR_TXEN_; 450 451 smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr); 452 453 /* Enable Tx at SCSRs */ 454 reg_val = TX_CFG_ON_; 455 smsc95xx_write_reg(udev, TX_CFG, reg_val); 456} 457 458/* Starts the Receive path */ 459static void smsc95xx_start_rx_path(struct usb_device *udev, 460 struct smsc95xx_private *priv) 461{ 462 priv->mac_cr |= MAC_CR_RXEN_; 463 smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr); 464} 465 466static int smsc95xx_init_common(struct usb_device *udev, struct ueth_data *dev, 467 struct smsc95xx_private *priv, 468 unsigned char *enetaddr) 469{ 470 int ret; 471 u32 write_buf; 472 u32 read_buf; 473 u32 burst_cap; 474 int timeout; 475#define TIMEOUT_RESOLUTION 50 /* ms */ 476 int link_detected; 477 478 debug("** %s()\n", __func__); 479 dev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */ 480 481 write_buf = HW_CFG_LRST_; 482 ret = smsc95xx_write_reg(udev, HW_CFG, write_buf); 483 if (ret < 0) 484 return ret; 485 486 timeout = 0; 487 do { 488 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf); 489 if (ret < 0) 490 return ret; 491 udelay(10 * 1000); 492 timeout++; 493 } while ((read_buf & HW_CFG_LRST_) && (timeout < 100)); 494 495 if (timeout >= 100) { 496 debug("timeout waiting for completion of Lite Reset\n"); 497 return -ETIMEDOUT; 498 } 499 500 write_buf = PM_CTL_PHY_RST_; 501 ret = smsc95xx_write_reg(udev, PM_CTRL, write_buf); 502 if (ret < 0) 503 return ret; 504 505 timeout = 0; 506 do { 507 ret = smsc95xx_read_reg(udev, PM_CTRL, &read_buf); 508 if (ret < 0) 509 return ret; 510 udelay(10 * 1000); 511 timeout++; 512 } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100)); 513 if (timeout >= 100) { 514 debug("timeout waiting for PHY Reset\n"); 515 return -ETIMEDOUT; 516 } 517 if (!priv->have_hwaddr) { 518 puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n"); 519 return -EADDRNOTAVAIL; 520 } 521 ret = smsc95xx_write_hwaddr_common(udev, priv, enetaddr); 522 if (ret < 0) 523 return ret; 524 525#ifdef TURBO_MODE 526 if (dev->pusb_dev->speed == USB_SPEED_HIGH) { 527 burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE; 528 priv->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE; 529 } else { 530 burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE; 531 priv->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE; 532 } 533#else 534 burst_cap = 0; 535 priv->rx_urb_size = MAX_SINGLE_PACKET_SIZE; 536#endif 537 debug("rx_urb_size=%ld\n", (ulong)priv->rx_urb_size); 538 539 ret = smsc95xx_write_reg(udev, BURST_CAP, burst_cap); 540 if (ret < 0) 541 return ret; 542 543 ret = smsc95xx_read_reg(udev, BURST_CAP, &read_buf); 544 if (ret < 0) 545 return ret; 546 debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf); 547 548 read_buf = DEFAULT_BULK_IN_DELAY; 549 ret = smsc95xx_write_reg(udev, BULK_IN_DLY, read_buf); 550 if (ret < 0) 551 return ret; 552 553 ret = smsc95xx_read_reg(udev, BULK_IN_DLY, &read_buf); 554 if (ret < 0) 555 return ret; 556 debug("Read Value from BULK_IN_DLY after writing: " 557 "0x%08x\n", read_buf); 558 559 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf); 560 if (ret < 0) 561 return ret; 562 debug("Read Value from HW_CFG: 0x%08x\n", read_buf); 563 564#ifdef TURBO_MODE 565 read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_); 566#endif 567 read_buf &= ~HW_CFG_RXDOFF_; 568 569#define NET_IP_ALIGN 0 570 read_buf |= NET_IP_ALIGN << 9; 571 572 ret = smsc95xx_write_reg(udev, HW_CFG, read_buf); 573 if (ret < 0) 574 return ret; 575 576 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf); 577 if (ret < 0) 578 return ret; 579 debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf); 580 581 write_buf = 0xFFFFFFFF; 582 ret = smsc95xx_write_reg(udev, INT_STS, write_buf); 583 if (ret < 0) 584 return ret; 585 586 ret = smsc95xx_read_reg(udev, ID_REV, &read_buf); 587 if (ret < 0) 588 return ret; 589 debug("ID_REV = 0x%08x\n", read_buf); 590 591 /* Configure GPIO pins as LED outputs */ 592 write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED | 593 LED_GPIO_CFG_FDX_LED; 594 ret = smsc95xx_write_reg(udev, LED_GPIO_CFG, write_buf); 595 if (ret < 0) 596 return ret; 597 debug("LED_GPIO_CFG set\n"); 598 599 /* Init Tx */ 600 write_buf = 0; 601 ret = smsc95xx_write_reg(udev, FLOW, write_buf); 602 if (ret < 0) 603 return ret; 604 605 read_buf = AFC_CFG_DEFAULT; 606 ret = smsc95xx_write_reg(udev, AFC_CFG, read_buf); 607 if (ret < 0) 608 return ret; 609 610 ret = smsc95xx_read_reg(udev, MAC_CR, &priv->mac_cr); 611 if (ret < 0) 612 return ret; 613 614 /* Init Rx. Set Vlan */ 615 write_buf = (u32)ETH_P_8021Q; 616 ret = smsc95xx_write_reg(udev, VLAN1, write_buf); 617 if (ret < 0) 618 return ret; 619 620 /* Disable checksum offload engines */ 621 ret = smsc95xx_set_csums(udev, 0, 0); 622 if (ret < 0) { 623 debug("Failed to set csum offload: %d\n", ret); 624 return ret; 625 } 626 smsc95xx_set_multicast(priv); 627 628 ret = smsc95xx_phy_initialize(udev, dev); 629 if (ret < 0) 630 return ret; 631 ret = smsc95xx_read_reg(udev, INT_EP_CTL, &read_buf); 632 if (ret < 0) 633 return ret; 634 635 /* enable PHY interrupts */ 636 read_buf |= INT_EP_CTL_PHY_INT_; 637 638 ret = smsc95xx_write_reg(udev, INT_EP_CTL, read_buf); 639 if (ret < 0) 640 return ret; 641 642 smsc95xx_start_tx_path(udev, priv); 643 smsc95xx_start_rx_path(udev, priv); 644 645 timeout = 0; 646 do { 647 link_detected = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMSR) 648 & BMSR_LSTATUS; 649 if (!link_detected) { 650 if (timeout == 0) 651 printf("Waiting for Ethernet connection... "); 652 udelay(TIMEOUT_RESOLUTION * 1000); 653 timeout += TIMEOUT_RESOLUTION; 654 } 655 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT); 656 if (link_detected) { 657 if (timeout != 0) 658 printf("done.\n"); 659 } else { 660 printf("unable to connect.\n"); 661 return -EIO; 662 } 663 return 0; 664} 665 666static int smsc95xx_send_common(struct ueth_data *dev, void *packet, int length) 667{ 668 int err; 669 int actual_len; 670 u32 tx_cmd_a; 671 u32 tx_cmd_b; 672 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg, 673 PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)); 674 675 debug("** %s(), len %d, buf %#x\n", __func__, length, 676 (unsigned int)(ulong)msg); 677 if (length > PKTSIZE) 678 return -ENOSPC; 679 680 tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_; 681 tx_cmd_b = (u32)length; 682 cpu_to_le32s(&tx_cmd_a); 683 cpu_to_le32s(&tx_cmd_b); 684 685 /* prepend cmd_a and cmd_b */ 686 memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a)); 687 memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b)); 688 memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet, 689 length); 690 err = usb_bulk_msg(dev->pusb_dev, 691 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), 692 (void *)msg, 693 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), 694 &actual_len, 695 USB_BULK_SEND_TIMEOUT); 696 debug("Tx: len = %u, actual = %u, err = %d\n", 697 (unsigned int)(length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b)), 698 (unsigned int)actual_len, err); 699 700 return err; 701} 702 703static int smsc95xx_eth_start(struct udevice *dev) 704{ 705 struct usb_device *udev = dev_get_parent_priv(dev); 706 struct smsc95xx_private *priv = dev_get_priv(dev); 707 struct eth_pdata *pdata = dev_get_plat(dev); 708 709 /* Driver-model Ethernet ensures we have this */ 710 priv->have_hwaddr = 1; 711 712 return smsc95xx_init_common(udev, &priv->ueth, priv, pdata->enetaddr); 713} 714 715void smsc95xx_eth_stop(struct udevice *dev) 716{ 717 debug("** %s()\n", __func__); 718} 719 720int smsc95xx_eth_send(struct udevice *dev, void *packet, int length) 721{ 722 struct smsc95xx_private *priv = dev_get_priv(dev); 723 724 return smsc95xx_send_common(&priv->ueth, packet, length); 725} 726 727int smsc95xx_eth_recv(struct udevice *dev, int flags, uchar **packetp) 728{ 729 struct smsc95xx_private *priv = dev_get_priv(dev); 730 struct ueth_data *ueth = &priv->ueth; 731 uint8_t *ptr; 732 int ret, len; 733 u32 packet_len; 734 735 len = usb_ether_get_rx_bytes(ueth, &ptr); 736 debug("%s: first try, len=%d\n", __func__, len); 737 if (!len) { 738 if (!(flags & ETH_RECV_CHECK_DEVICE)) 739 return -EAGAIN; 740 ret = usb_ether_receive(ueth, RX_URB_SIZE); 741 if (ret == -EAGAIN) 742 return ret; 743 744 len = usb_ether_get_rx_bytes(ueth, &ptr); 745 debug("%s: second try, len=%d\n", __func__, len); 746 } 747 748 /* 749 * 1st 4 bytes contain the length of the actual data plus error info. 750 * Extract data length. 751 */ 752 if (len < sizeof(packet_len)) { 753 debug("Rx: incomplete packet length\n"); 754 goto err; 755 } 756 memcpy(&packet_len, ptr, sizeof(packet_len)); 757 le32_to_cpus(&packet_len); 758 if (packet_len & RX_STS_ES_) { 759 debug("Rx: Error header=%#x", packet_len); 760 goto err; 761 } 762 packet_len = ((packet_len & RX_STS_FL_) >> 16); 763 764 if (packet_len > len - sizeof(packet_len)) { 765 debug("Rx: too large packet: %d\n", packet_len); 766 goto err; 767 } 768 769 *packetp = ptr + sizeof(packet_len); 770 return packet_len - 4; 771 772err: 773 usb_ether_advance_rxbuf(ueth, -1); 774 return -EINVAL; 775} 776 777static int smsc95xx_free_pkt(struct udevice *dev, uchar *packet, int packet_len) 778{ 779 struct smsc95xx_private *priv = dev_get_priv(dev); 780 781 packet_len = ALIGN(packet_len + sizeof(u32), 4); 782 usb_ether_advance_rxbuf(&priv->ueth, sizeof(u32) + packet_len); 783 784 return 0; 785} 786 787int smsc95xx_write_hwaddr(struct udevice *dev) 788{ 789 struct usb_device *udev = dev_get_parent_priv(dev); 790 struct eth_pdata *pdata = dev_get_plat(dev); 791 struct smsc95xx_private *priv = dev_get_priv(dev); 792 793 return smsc95xx_write_hwaddr_common(udev, priv, pdata->enetaddr); 794} 795 796int smsc95xx_read_rom_hwaddr(struct udevice *dev) 797{ 798 struct usb_device *udev = dev_get_parent_priv(dev); 799 struct eth_pdata *pdata = dev_get_plat(dev); 800 int ret; 801 802 ret = smsc95xx_init_mac_address(pdata->enetaddr, udev); 803 if (ret) 804 memset(pdata->enetaddr, 0, 6); 805 806 return 0; 807} 808 809static int smsc95xx_eth_probe(struct udevice *dev) 810{ 811 struct smsc95xx_private *priv = dev_get_priv(dev); 812 struct ueth_data *ueth = &priv->ueth; 813 814 return usb_ether_register(dev, ueth, RX_URB_SIZE); 815} 816 817static const struct eth_ops smsc95xx_eth_ops = { 818 .start = smsc95xx_eth_start, 819 .send = smsc95xx_eth_send, 820 .recv = smsc95xx_eth_recv, 821 .free_pkt = smsc95xx_free_pkt, 822 .stop = smsc95xx_eth_stop, 823 .write_hwaddr = smsc95xx_write_hwaddr, 824 .read_rom_hwaddr = smsc95xx_read_rom_hwaddr, 825}; 826 827U_BOOT_DRIVER(smsc95xx_eth) = { 828 .name = "smsc95xx_eth", 829 .id = UCLASS_ETH, 830 .probe = smsc95xx_eth_probe, 831 .ops = &smsc95xx_eth_ops, 832 .priv_auto = sizeof(struct smsc95xx_private), 833 .plat_auto = sizeof(struct eth_pdata), 834}; 835 836static const struct usb_device_id smsc95xx_eth_id_table[] = { 837 { USB_DEVICE(0x05ac, 0x1402) }, 838 { USB_DEVICE(0x0424, 0xec00) }, /* LAN9512/LAN9514 Ethernet */ 839 { USB_DEVICE(0x0424, 0x9500) }, /* LAN9500 Ethernet */ 840 { USB_DEVICE(0x0424, 0x9730) }, /* LAN9730 Ethernet (HSIC) */ 841 { USB_DEVICE(0x0424, 0x9900) }, /* SMSC9500 USB Ethernet (SAL10) */ 842 { USB_DEVICE(0x0424, 0x9e00) }, /* LAN9500A Ethernet */ 843 { } /* Terminating entry */ 844}; 845 846U_BOOT_USB_DEVICE(smsc95xx_eth, smsc95xx_eth_id_table); 847