1// SPDX-License-Identifier: GPL-2.0+ 2 3/* 4 * Freescale QuadSPI driver. 5 * 6 * Copyright (C) 2013 Freescale Semiconductor, Inc. 7 * Copyright (C) 2018 Bootlin 8 * Copyright (C) 2018 exceet electronics GmbH 9 * Copyright (C) 2018 Kontron Electronics GmbH 10 * Copyright 2019-2020 NXP 11 * 12 * This driver is a ported version of Linux Freescale QSPI driver taken from 13 * v5.5-rc1 tag having following information. 14 * 15 * Transition to SPI MEM interface: 16 * Authors: 17 * Boris Brezillon <bbrezillon@kernel.org> 18 * Frieder Schrempf <frieder.schrempf@kontron.de> 19 * Yogesh Gaur <yogeshnarayan.gaur@nxp.com> 20 * Suresh Gupta <suresh.gupta@nxp.com> 21 * 22 * Based on the original fsl-quadspi.c spi-nor driver. 23 * Transition to spi-mem in spi-fsl-qspi.c 24 */ 25 26#include <dm.h> 27#include <dm/device_compat.h> 28#include <log.h> 29#include <spi.h> 30#include <spi-mem.h> 31#include <asm/global_data.h> 32#include <linux/bitops.h> 33#include <linux/delay.h> 34#include <linux/libfdt.h> 35#include <linux/sizes.h> 36#include <linux/iopoll.h> 37#include <linux/iopoll.h> 38#include <linux/sizes.h> 39#include <linux/err.h> 40#include <asm/io.h> 41 42DECLARE_GLOBAL_DATA_PTR; 43 44/* 45 * The driver only uses one single LUT entry, that is updated on 46 * each call of exec_op(). Index 0 is preset at boot with a basic 47 * read operation, so let's use the last entry (15). 48 */ 49#define SEQID_LUT 15 50#define SEQID_LUT_AHB 14 51 52/* Registers used by the driver */ 53#define QUADSPI_MCR 0x00 54#define QUADSPI_MCR_RESERVED_MASK GENMASK(19, 16) 55#define QUADSPI_MCR_MDIS_MASK BIT(14) 56#define QUADSPI_MCR_CLR_TXF_MASK BIT(11) 57#define QUADSPI_MCR_CLR_RXF_MASK BIT(10) 58#define QUADSPI_MCR_DDR_EN_MASK BIT(7) 59#define QUADSPI_MCR_END_CFG_MASK GENMASK(3, 2) 60#define QUADSPI_MCR_SWRSTHD_MASK BIT(1) 61#define QUADSPI_MCR_SWRSTSD_MASK BIT(0) 62 63#define QUADSPI_IPCR 0x08 64#define QUADSPI_IPCR_SEQID(x) ((x) << 24) 65#define QUADSPI_FLSHCR 0x0c 66#define QUADSPI_FLSHCR_TCSS_MASK GENMASK(3, 0) 67#define QUADSPI_FLSHCR_TCSH_MASK GENMASK(11, 8) 68#define QUADSPI_FLSHCR_TDH_MASK GENMASK(17, 16) 69 70#define QUADSPI_BUF3CR 0x1c 71#define QUADSPI_BUF3CR_ALLMST_MASK BIT(31) 72#define QUADSPI_BUF3CR_ADATSZ(x) ((x) << 8) 73#define QUADSPI_BUF3CR_ADATSZ_MASK GENMASK(15, 8) 74 75#define QUADSPI_BFGENCR 0x20 76#define QUADSPI_BFGENCR_SEQID(x) ((x) << 12) 77 78#define QUADSPI_BUF0IND 0x30 79#define QUADSPI_BUF1IND 0x34 80#define QUADSPI_BUF2IND 0x38 81#define QUADSPI_SFAR 0x100 82 83#define QUADSPI_SMPR 0x108 84#define QUADSPI_SMPR_DDRSMP_MASK GENMASK(18, 16) 85#define QUADSPI_SMPR_FSDLY_MASK BIT(6) 86#define QUADSPI_SMPR_FSPHS_MASK BIT(5) 87#define QUADSPI_SMPR_HSENA_MASK BIT(0) 88 89#define QUADSPI_RBCT 0x110 90#define QUADSPI_RBCT_WMRK_MASK GENMASK(4, 0) 91#define QUADSPI_RBCT_RXBRD_USEIPS BIT(8) 92 93#define QUADSPI_TBDR 0x154 94 95#define QUADSPI_SR 0x15c 96#define QUADSPI_SR_IP_ACC_MASK BIT(1) 97#define QUADSPI_SR_AHB_ACC_MASK BIT(2) 98 99#define QUADSPI_FR 0x160 100#define QUADSPI_FR_TFF_MASK BIT(0) 101 102#define QUADSPI_RSER 0x164 103#define QUADSPI_RSER_TFIE BIT(0) 104 105#define QUADSPI_SPTRCLR 0x16c 106#define QUADSPI_SPTRCLR_IPPTRC BIT(8) 107#define QUADSPI_SPTRCLR_BFPTRC BIT(0) 108 109#define QUADSPI_SFA1AD 0x180 110#define QUADSPI_SFA2AD 0x184 111#define QUADSPI_SFB1AD 0x188 112#define QUADSPI_SFB2AD 0x18c 113#define QUADSPI_RBDR(x) (0x200 + ((x) * 4)) 114 115#define QUADSPI_LUTKEY 0x300 116#define QUADSPI_LUTKEY_VALUE 0x5AF05AF0 117 118#define QUADSPI_LCKCR 0x304 119#define QUADSPI_LCKER_LOCK BIT(0) 120#define QUADSPI_LCKER_UNLOCK BIT(1) 121 122#define QUADSPI_LUT_BASE 0x310 123#define QUADSPI_LUT_OFFSET (SEQID_LUT * 4 * 4) 124#define QUADSPI_LUT_REG(idx) \ 125 (QUADSPI_LUT_BASE + QUADSPI_LUT_OFFSET + (idx) * 4) 126 127#define QUADSPI_AHB_LUT_OFFSET (SEQID_LUT_AHB * 4 * 4) 128#define QUADSPI_AHB_LUT_REG(idx) \ 129 (QUADSPI_LUT_BASE + QUADSPI_AHB_LUT_OFFSET + (idx) * 4) 130 131/* Instruction set for the LUT register */ 132#define LUT_STOP 0 133#define LUT_CMD 1 134#define LUT_ADDR 2 135#define LUT_DUMMY 3 136#define LUT_MODE 4 137#define LUT_MODE2 5 138#define LUT_MODE4 6 139#define LUT_FSL_READ 7 140#define LUT_FSL_WRITE 8 141#define LUT_JMP_ON_CS 9 142#define LUT_ADDR_DDR 10 143#define LUT_MODE_DDR 11 144#define LUT_MODE2_DDR 12 145#define LUT_MODE4_DDR 13 146#define LUT_FSL_READ_DDR 14 147#define LUT_FSL_WRITE_DDR 15 148#define LUT_DATA_LEARN 16 149 150/* 151 * The PAD definitions for LUT register. 152 * 153 * The pad stands for the number of IO lines [0:3]. 154 * For example, the quad read needs four IO lines, 155 * so you should use LUT_PAD(4). 156 */ 157#define LUT_PAD(x) (fls(x) - 1) 158 159/* 160 * Macro for constructing the LUT entries with the following 161 * register layout: 162 * 163 * --------------------------------------------------- 164 * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | 165 * --------------------------------------------------- 166 */ 167#define LUT_DEF(idx, ins, pad, opr) \ 168 ((((ins) << 10) | ((pad) << 8) | (opr)) << (((idx) % 2) * 16)) 169 170/* Controller needs driver to swap endianness */ 171#define QUADSPI_QUIRK_SWAP_ENDIAN BIT(0) 172 173/* Controller needs 4x internal clock */ 174#define QUADSPI_QUIRK_4X_INT_CLK BIT(1) 175 176/* 177 * TKT253890, the controller needs the driver to fill the txfifo with 178 * 16 bytes at least to trigger a data transfer, even though the extra 179 * data won't be transferred. 180 */ 181#define QUADSPI_QUIRK_TKT253890 BIT(2) 182 183/* TKT245618, the controller cannot wake up from wait mode */ 184#define QUADSPI_QUIRK_TKT245618 BIT(3) 185 186/* 187 * Controller adds QSPI_AMBA_BASE (base address of the mapped memory) 188 * internally. No need to add it when setting SFXXAD and SFAR registers 189 */ 190#define QUADSPI_QUIRK_BASE_INTERNAL BIT(4) 191 192/* 193 * Controller uses TDH bits in register QUADSPI_FLSHCR. 194 * They need to be set in accordance with the DDR/SDR mode. 195 */ 196#define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5) 197 198/* 199 * Controller only has Two CS on flash A, no flash B port 200 */ 201#define QUADSPI_QUIRK_SINGLE_BUS BIT(6) 202 203struct fsl_qspi_devtype_data { 204 unsigned int rxfifo; 205 unsigned int txfifo; 206 unsigned int ahb_buf_size; 207 unsigned int quirks; 208 bool little_endian; 209}; 210 211static const struct fsl_qspi_devtype_data vybrid_data = { 212 .rxfifo = SZ_128, 213 .txfifo = SZ_64, 214 .ahb_buf_size = SZ_1K, 215 .quirks = QUADSPI_QUIRK_SWAP_ENDIAN, 216 .little_endian = true, 217}; 218 219static const struct fsl_qspi_devtype_data imx6sx_data = { 220 .rxfifo = SZ_128, 221 .txfifo = SZ_512, 222 .ahb_buf_size = SZ_1K, 223 .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618, 224 .little_endian = true, 225}; 226 227static const struct fsl_qspi_devtype_data imx7d_data = { 228 .rxfifo = SZ_128, 229 .txfifo = SZ_512, 230 .ahb_buf_size = SZ_1K, 231 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK | 232 QUADSPI_QUIRK_USE_TDH_SETTING, 233 .little_endian = true, 234}; 235 236static const struct fsl_qspi_devtype_data imx6ul_data = { 237 .rxfifo = SZ_128, 238 .txfifo = SZ_512, 239 .ahb_buf_size = SZ_1K, 240 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK | 241 QUADSPI_QUIRK_USE_TDH_SETTING, 242 .little_endian = true, 243}; 244 245static const struct fsl_qspi_devtype_data imx7ulp_data = { 246 .rxfifo = SZ_64, 247 .txfifo = SZ_64, 248 .ahb_buf_size = SZ_128, 249 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK | 250 QUADSPI_QUIRK_USE_TDH_SETTING | QUADSPI_QUIRK_SINGLE_BUS, 251 .little_endian = true, 252}; 253 254static const struct fsl_qspi_devtype_data ls1021a_data = { 255 .rxfifo = SZ_128, 256 .txfifo = SZ_64, 257 .ahb_buf_size = SZ_1K, 258 .quirks = 0, 259 .little_endian = false, 260}; 261 262static const struct fsl_qspi_devtype_data ls2080a_data = { 263 .rxfifo = SZ_128, 264 .txfifo = SZ_64, 265 .ahb_buf_size = SZ_1K, 266 .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL, 267 .little_endian = true, 268}; 269 270struct fsl_qspi { 271 struct udevice *dev; 272 void __iomem *iobase; 273 void __iomem *ahb_addr; 274 u32 memmap_phy; 275 u32 memmap_size; 276 const struct fsl_qspi_devtype_data *devtype_data; 277 int selected; 278}; 279 280static inline int needs_swap_endian(struct fsl_qspi *q) 281{ 282 return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN; 283} 284 285static inline int needs_4x_clock(struct fsl_qspi *q) 286{ 287 return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK; 288} 289 290static inline int needs_fill_txfifo(struct fsl_qspi *q) 291{ 292 return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890; 293} 294 295static inline int needs_wakeup_wait_mode(struct fsl_qspi *q) 296{ 297 return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618; 298} 299 300static inline int needs_amba_base_offset(struct fsl_qspi *q) 301{ 302 return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL); 303} 304 305static inline int needs_tdh_setting(struct fsl_qspi *q) 306{ 307 return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING; 308} 309 310static inline int needs_single_bus(struct fsl_qspi *q) 311{ 312 return q->devtype_data->quirks & QUADSPI_QUIRK_SINGLE_BUS; 313} 314 315/* 316 * An IC bug makes it necessary to rearrange the 32-bit data. 317 * Later chips, such as IMX6SLX, have fixed this bug. 318 */ 319static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a) 320{ 321 return needs_swap_endian(q) ? __swab32(a) : a; 322} 323 324/* 325 * R/W functions for big- or little-endian registers: 326 * The QSPI controller's endianness is independent of 327 * the CPU core's endianness. So far, although the CPU 328 * core is little-endian the QSPI controller can use 329 * big-endian or little-endian. 330 */ 331static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr) 332{ 333 if (q->devtype_data->little_endian) 334 out_le32(addr, val); 335 else 336 out_be32(addr, val); 337} 338 339static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr) 340{ 341 if (q->devtype_data->little_endian) 342 return in_le32(addr); 343 344 return in_be32(addr); 345} 346 347static int fsl_qspi_check_buswidth(struct fsl_qspi *q, u8 width) 348{ 349 switch (width) { 350 case 1: 351 case 2: 352 case 4: 353 return 0; 354 } 355 356 return -ENOTSUPP; 357} 358 359static bool fsl_qspi_supports_op(struct spi_slave *slave, 360 const struct spi_mem_op *op) 361{ 362 struct fsl_qspi *q = dev_get_priv(slave->dev->parent); 363 int ret; 364 365 ret = fsl_qspi_check_buswidth(q, op->cmd.buswidth); 366 367 if (op->addr.nbytes) 368 ret |= fsl_qspi_check_buswidth(q, op->addr.buswidth); 369 370 if (op->dummy.nbytes) 371 ret |= fsl_qspi_check_buswidth(q, op->dummy.buswidth); 372 373 if (op->data.nbytes) 374 ret |= fsl_qspi_check_buswidth(q, op->data.buswidth); 375 376 if (ret) 377 return false; 378 379 /* 380 * The number of instructions needed for the op, needs 381 * to fit into a single LUT entry. 382 */ 383 if (op->addr.nbytes + 384 (op->dummy.nbytes ? 1 : 0) + 385 (op->data.nbytes ? 1 : 0) > 6) 386 return false; 387 388 /* Max 64 dummy clock cycles supported */ 389 if (op->dummy.nbytes && 390 (op->dummy.nbytes * 8 / op->dummy.buswidth > 64)) 391 return false; 392 393 /* Max data length, check controller limits and alignment */ 394 if (op->data.dir == SPI_MEM_DATA_IN && 395 (op->data.nbytes > q->devtype_data->ahb_buf_size || 396 (op->data.nbytes > q->devtype_data->rxfifo - 4 && 397 !IS_ALIGNED(op->data.nbytes, 8)))) 398 return false; 399 400 if (op->data.dir == SPI_MEM_DATA_OUT && 401 op->data.nbytes > q->devtype_data->txfifo) 402 return false; 403 404 return spi_mem_default_supports_op(slave, op); 405} 406 407static void fsl_qspi_prepare_lut(struct fsl_qspi *q, 408 const struct spi_mem_op *op) 409{ 410 void __iomem *base = q->iobase; 411 u32 lutval[4] = {}; 412 int lutidx = 1, i; 413 414 lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth), 415 op->cmd.opcode); 416 417 if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) { 418 if (op->addr.nbytes) { 419 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_ADDR, 420 LUT_PAD(op->addr.buswidth), 421 (op->addr.nbytes == 4) ? 0x20 : 0x18); 422 lutidx++; 423 } 424 } else { 425 /* 426 * For some unknown reason, using LUT_ADDR doesn't work in some 427 * cases (at least with only one byte long addresses), so 428 * let's use LUT_MODE to write the address bytes one by one 429 */ 430 for (i = 0; i < op->addr.nbytes; i++) { 431 u8 addrbyte = op->addr.val >> (8 * (op->addr.nbytes - i - 1)); 432 433 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_MODE, 434 LUT_PAD(op->addr.buswidth), 435 addrbyte); 436 lutidx++; 437 } 438 } 439 440 if (op->dummy.nbytes) { 441 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_DUMMY, 442 LUT_PAD(op->dummy.buswidth), 443 op->dummy.nbytes * 8 / 444 op->dummy.buswidth); 445 lutidx++; 446 } 447 448 if (op->data.nbytes) { 449 lutval[lutidx / 2] |= LUT_DEF(lutidx, 450 op->data.dir == SPI_MEM_DATA_IN ? 451 LUT_FSL_READ : LUT_FSL_WRITE, 452 LUT_PAD(op->data.buswidth), 453 0); 454 lutidx++; 455 } 456 457 lutval[lutidx / 2] |= LUT_DEF(lutidx, LUT_STOP, 0, 0); 458 459 /* unlock LUT */ 460 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); 461 qspi_writel(q, QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR); 462 463 dev_dbg(q->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n", 464 op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]); 465 466 /* fill LUT */ 467 for (i = 0; i < ARRAY_SIZE(lutval); i++) 468 qspi_writel(q, lutval[i], base + QUADSPI_LUT_REG(i)); 469 470 if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) { 471 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN && 472 op->addr.nbytes) { 473 for (i = 0; i < ARRAY_SIZE(lutval); i++) 474 qspi_writel(q, lutval[i], base + QUADSPI_AHB_LUT_REG(i)); 475 } 476 } 477 478 /* lock LUT */ 479 qspi_writel(q, QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); 480 qspi_writel(q, QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR); 481} 482 483/* 484 * If we have changed the content of the flash by writing or erasing, or if we 485 * read from flash with a different offset into the page buffer, we need to 486 * invalidate the AHB buffer. If we do not do so, we may read out the wrong 487 * data. The spec tells us reset the AHB domain and Serial Flash domain at 488 * the same time. 489 */ 490static void fsl_qspi_invalidate(struct fsl_qspi *q) 491{ 492 u32 reg; 493 494 reg = qspi_readl(q, q->iobase + QUADSPI_MCR); 495 reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK; 496 qspi_writel(q, reg, q->iobase + QUADSPI_MCR); 497 498 /* 499 * The minimum delay : 1 AHB + 2 SFCK clocks. 500 * Delay 1 us is enough. 501 */ 502 udelay(1); 503 504 reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK); 505 qspi_writel(q, reg, q->iobase + QUADSPI_MCR); 506} 507 508static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_slave *slave) 509{ 510 struct dm_spi_slave_plat *plat = 511 dev_get_parent_plat(slave->dev); 512 513 if (q->selected == plat->cs) 514 return; 515 516 q->selected = plat->cs; 517 fsl_qspi_invalidate(q); 518} 519 520static u32 fsl_qspi_memsize_per_cs(struct fsl_qspi *q) 521{ 522 if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) { 523 if (needs_single_bus(q)) 524 return q->memmap_size / 2; 525 else 526 return q->memmap_size / 4; 527 } else { 528 return ALIGN(q->devtype_data->ahb_buf_size, 0x400); 529 } 530} 531 532static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op) 533{ 534 void __iomem *ahb_read_addr = q->ahb_addr; 535 536 if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) { 537 if (op->addr.nbytes) 538 ahb_read_addr += op->addr.val; 539 } 540 541 memcpy_fromio(op->data.buf.in, 542 ahb_read_addr + q->selected * fsl_qspi_memsize_per_cs(q), 543 op->data.nbytes); 544} 545 546static void fsl_qspi_fill_txfifo(struct fsl_qspi *q, 547 const struct spi_mem_op *op) 548{ 549 void __iomem *base = q->iobase; 550 int i; 551 u32 val; 552 553 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) { 554 memcpy(&val, op->data.buf.out + i, 4); 555 val = fsl_qspi_endian_xchg(q, val); 556 qspi_writel(q, val, base + QUADSPI_TBDR); 557 } 558 559 if (i < op->data.nbytes) { 560 memcpy(&val, op->data.buf.out + i, op->data.nbytes - i); 561 val = fsl_qspi_endian_xchg(q, val); 562 qspi_writel(q, val, base + QUADSPI_TBDR); 563 } 564 565 if (needs_fill_txfifo(q)) { 566 for (i = op->data.nbytes; i < 16; i += 4) 567 qspi_writel(q, 0, base + QUADSPI_TBDR); 568 } 569} 570 571static void fsl_qspi_read_rxfifo(struct fsl_qspi *q, 572 const struct spi_mem_op *op) 573{ 574 void __iomem *base = q->iobase; 575 int i; 576 u8 *buf = op->data.buf.in; 577 u32 val; 578 579 for (i = 0; i < ALIGN_DOWN(op->data.nbytes, 4); i += 4) { 580 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4)); 581 val = fsl_qspi_endian_xchg(q, val); 582 memcpy(buf + i, &val, 4); 583 } 584 585 if (i < op->data.nbytes) { 586 val = qspi_readl(q, base + QUADSPI_RBDR(i / 4)); 587 val = fsl_qspi_endian_xchg(q, val); 588 memcpy(buf + i, &val, op->data.nbytes - i); 589 } 590} 591 592static int fsl_qspi_readl_poll_tout(struct fsl_qspi *q, void __iomem *base, 593 u32 mask, u32 delay_us, u32 timeout_us) 594{ 595 u32 reg; 596 597 if (!q->devtype_data->little_endian) 598 mask = (u32)cpu_to_be32(mask); 599 600 return readl_poll_timeout(base, reg, !(reg & mask), timeout_us); 601} 602 603static int fsl_qspi_do_op(struct fsl_qspi *q, const struct spi_mem_op *op) 604{ 605 void __iomem *base = q->iobase; 606 int err = 0; 607 608 /* 609 * Always start the sequence at the same index since we update 610 * the LUT at each exec_op() call. And also specify the DATA 611 * length, since it's has not been specified in the LUT. 612 */ 613 qspi_writel(q, op->data.nbytes | QUADSPI_IPCR_SEQID(SEQID_LUT), 614 base + QUADSPI_IPCR); 615 616 /* wait for the controller being ready */ 617 err = fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, 618 (QUADSPI_SR_IP_ACC_MASK | 619 QUADSPI_SR_AHB_ACC_MASK), 620 10, 1000); 621 622 if (!err && op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN) 623 fsl_qspi_read_rxfifo(q, op); 624 625 return err; 626} 627 628static int fsl_qspi_exec_op(struct spi_slave *slave, 629 const struct spi_mem_op *op) 630{ 631 struct fsl_qspi *q = dev_get_priv(slave->dev->parent); 632 void __iomem *base = q->iobase; 633 u32 addr_offset = 0; 634 int err = 0; 635 636 /* wait for the controller being ready */ 637 fsl_qspi_readl_poll_tout(q, base + QUADSPI_SR, (QUADSPI_SR_IP_ACC_MASK | 638 QUADSPI_SR_AHB_ACC_MASK), 10, 1000); 639 640 fsl_qspi_select_mem(q, slave); 641 642 if (needs_amba_base_offset(q)) 643 addr_offset = q->memmap_phy; 644 645 if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) { 646 if (op->addr.nbytes) 647 addr_offset += op->addr.val; 648 } 649 650 qspi_writel(q, 651 q->selected * fsl_qspi_memsize_per_cs(q) + addr_offset, 652 base + QUADSPI_SFAR); 653 654 qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) | 655 QUADSPI_MCR_CLR_RXF_MASK | QUADSPI_MCR_CLR_TXF_MASK, 656 base + QUADSPI_MCR); 657 658 qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC, 659 base + QUADSPI_SPTRCLR); 660 661 fsl_qspi_prepare_lut(q, op); 662 663 /* 664 * If we have large chunks of data, we read them through the AHB bus 665 * by accessing the mapped memory. In all other cases we use 666 * IP commands to access the flash. 667 */ 668 if (op->data.nbytes > (q->devtype_data->rxfifo - 4) && 669 op->data.dir == SPI_MEM_DATA_IN) { 670 fsl_qspi_read_ahb(q, op); 671 } else { 672 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | 673 QUADSPI_RBCT_RXBRD_USEIPS, base + QUADSPI_RBCT); 674 675 if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) 676 fsl_qspi_fill_txfifo(q, op); 677 678 err = fsl_qspi_do_op(q, op); 679 } 680 681 /* Invalidate the data in the AHB buffer. */ 682 fsl_qspi_invalidate(q); 683 684 return err; 685} 686 687static int fsl_qspi_adjust_op_size(struct spi_slave *slave, 688 struct spi_mem_op *op) 689{ 690 struct fsl_qspi *q = dev_get_priv(slave->dev->parent); 691 692 if (op->data.dir == SPI_MEM_DATA_OUT) { 693 if (op->data.nbytes > q->devtype_data->txfifo) 694 op->data.nbytes = q->devtype_data->txfifo; 695 } else { 696 if (op->data.nbytes > q->devtype_data->ahb_buf_size) 697 op->data.nbytes = q->devtype_data->ahb_buf_size; 698 else if (op->data.nbytes > (q->devtype_data->rxfifo - 4)) 699 op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8); 700 } 701 702 return 0; 703} 704 705static int fsl_qspi_default_setup(struct fsl_qspi *q) 706{ 707 void __iomem *base = q->iobase; 708 u32 reg, addr_offset = 0, memsize_cs; 709 710 /* Reset the module */ 711 qspi_writel(q, QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK, 712 base + QUADSPI_MCR); 713 udelay(1); 714 715 /* Disable the module */ 716 qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK, 717 base + QUADSPI_MCR); 718 719 /* 720 * Previous boot stages (BootROM, bootloader) might have used DDR 721 * mode and did not clear the TDH bits. As we currently use SDR mode 722 * only, clear the TDH bits if necessary. 723 */ 724 if (needs_tdh_setting(q)) 725 qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) & 726 ~QUADSPI_FLSHCR_TDH_MASK, 727 base + QUADSPI_FLSHCR); 728 729 reg = qspi_readl(q, base + QUADSPI_SMPR); 730 qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK 731 | QUADSPI_SMPR_FSPHS_MASK 732 | QUADSPI_SMPR_HSENA_MASK 733 | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR); 734 735 /* We only use the buffer3 for AHB read */ 736 qspi_writel(q, 0, base + QUADSPI_BUF0IND); 737 qspi_writel(q, 0, base + QUADSPI_BUF1IND); 738 qspi_writel(q, 0, base + QUADSPI_BUF2IND); 739 740 if (IS_ENABLED(CONFIG_FSL_QSPI_AHB_FULL_MAP)) 741 qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT_AHB), 742 q->iobase + QUADSPI_BFGENCR); 743 else 744 qspi_writel(q, QUADSPI_BFGENCR_SEQID(SEQID_LUT), 745 q->iobase + QUADSPI_BFGENCR); 746 747 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK, base + QUADSPI_RBCT); 748 qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK | 749 QUADSPI_BUF3CR_ADATSZ(q->devtype_data->ahb_buf_size / 8), 750 base + QUADSPI_BUF3CR); 751 752 if (needs_amba_base_offset(q)) 753 addr_offset = q->memmap_phy; 754 755 /* 756 * In HW there can be a maximum of four chips on two buses with 757 * two chip selects on each bus. We use four chip selects in SW 758 * to differentiate between the four chips. 759 * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD, 760 * SFB2AD accordingly. 761 */ 762 memsize_cs = fsl_qspi_memsize_per_cs(q); 763 qspi_writel(q, memsize_cs + addr_offset, 764 base + QUADSPI_SFA1AD); 765 qspi_writel(q, memsize_cs * 2 + addr_offset, 766 base + QUADSPI_SFA2AD); 767 if (!needs_single_bus(q)) { 768 qspi_writel(q, memsize_cs * 3 + addr_offset, 769 base + QUADSPI_SFB1AD); 770 qspi_writel(q, memsize_cs * 4 + addr_offset, 771 base + QUADSPI_SFB2AD); 772 } 773 774 q->selected = -1; 775 776 /* Enable the module */ 777 qspi_writel(q, QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK, 778 base + QUADSPI_MCR); 779 return 0; 780} 781 782static const struct spi_controller_mem_ops fsl_qspi_mem_ops = { 783 .adjust_op_size = fsl_qspi_adjust_op_size, 784 .supports_op = fsl_qspi_supports_op, 785 .exec_op = fsl_qspi_exec_op, 786}; 787 788static int fsl_qspi_probe(struct udevice *bus) 789{ 790 struct dm_spi_bus *dm_bus = dev_get_uclass_priv(bus); 791 struct fsl_qspi *q = dev_get_priv(bus); 792 const void *blob = gd->fdt_blob; 793 int node = dev_of_offset(bus); 794 struct fdt_resource res; 795 int ret; 796 797 q->dev = bus; 798 q->devtype_data = (struct fsl_qspi_devtype_data *) 799 dev_get_driver_data(bus); 800 801 /* find the resources */ 802 ret = fdt_get_named_resource(blob, node, "reg", "reg-names", "QuadSPI", 803 &res); 804 if (ret) { 805 dev_err(bus, "Can't get regs base addresses(ret = %d)!\n", ret); 806 return -ENOMEM; 807 } 808 809 q->iobase = map_physmem(res.start, res.end - res.start, MAP_NOCACHE); 810 811 ret = fdt_get_named_resource(blob, node, "reg", "reg-names", 812 "QuadSPI-memory", &res); 813 if (ret) { 814 dev_err(bus, "Can't get AMBA base addresses(ret = %d)!\n", ret); 815 return -ENOMEM; 816 } 817 818 q->ahb_addr = map_physmem(res.start, res.end - res.start, MAP_NOCACHE); 819 q->memmap_phy = res.start; 820 q->memmap_size = res.end - res.start; 821 822 dm_bus->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 823 66000000); 824 825 fsl_qspi_default_setup(q); 826 827 return 0; 828} 829 830static int fsl_qspi_xfer(struct udevice *dev, unsigned int bitlen, 831 const void *dout, void *din, unsigned long flags) 832{ 833 return 0; 834} 835 836static int fsl_qspi_claim_bus(struct udevice *dev) 837{ 838 return 0; 839} 840 841static int fsl_qspi_release_bus(struct udevice *dev) 842{ 843 return 0; 844} 845 846static int fsl_qspi_set_speed(struct udevice *bus, uint speed) 847{ 848 return 0; 849} 850 851static int fsl_qspi_set_mode(struct udevice *bus, uint mode) 852{ 853 return 0; 854} 855 856static const struct dm_spi_ops fsl_qspi_ops = { 857 .claim_bus = fsl_qspi_claim_bus, 858 .release_bus = fsl_qspi_release_bus, 859 .xfer = fsl_qspi_xfer, 860 .set_speed = fsl_qspi_set_speed, 861 .set_mode = fsl_qspi_set_mode, 862 .mem_ops = &fsl_qspi_mem_ops, 863}; 864 865static const struct udevice_id fsl_qspi_ids[] = { 866 { .compatible = "fsl,vf610-qspi", .data = (ulong)&vybrid_data, }, 867 { .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data, }, 868 { .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_data, }, 869 { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx7d_data, }, 870 { .compatible = "fsl,imx7ulp-qspi", .data = (ulong)&imx7ulp_data, }, 871 { .compatible = "fsl,ls1021a-qspi", .data = (ulong)&ls1021a_data, }, 872 { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls2080a_data, }, 873 { .compatible = "fsl,ls2080a-qspi", .data = (ulong)&ls2080a_data, }, 874 { } 875}; 876 877U_BOOT_DRIVER(fsl_qspi) = { 878 .name = "fsl_qspi", 879 .id = UCLASS_SPI, 880 .of_match = fsl_qspi_ids, 881 .ops = &fsl_qspi_ops, 882 .priv_auto = sizeof(struct fsl_qspi), 883 .probe = fsl_qspi_probe, 884}; 885