1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * eSPI controller driver. 4 * 5 * Copyright 2010-2011 Freescale Semiconductor, Inc. 6 * Copyright 2020 NXP 7 * Author: Mingkai Hu (Mingkai.hu@freescale.com) 8 * Chuanhua Han (chuanhua.han@nxp.com) 9 */ 10 11#include <common.h> 12#include <log.h> 13#include <linux/bitops.h> 14#include <linux/delay.h> 15 16#include <malloc.h> 17#include <spi.h> 18#include <asm/global_data.h> 19#include <asm/immap_85xx.h> 20#include <dm.h> 21#include <errno.h> 22#include <fdtdec.h> 23#include <dm/platform_data/fsl_espi.h> 24 25struct fsl_spi_slave { 26 struct spi_slave slave; 27 ccsr_espi_t *espi; 28 u32 speed_hz; 29 unsigned int cs; 30 unsigned int div16; 31 unsigned int pm; 32 int tx_timeout; 33 unsigned int mode; 34 size_t cmd_len; 35 u8 cmd_buf[16]; 36 size_t data_len; 37 unsigned int max_transfer_length; 38}; 39 40#define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave) 41#define US_PER_SECOND 1000000UL 42 43/* default SCK frequency, unit: HZ */ 44#define FSL_ESPI_DEFAULT_SCK_FREQ 10000000 45 46#define ESPI_MAX_CS_NUM 4 47#define ESPI_FIFO_WIDTH_BIT 32 48 49#define ESPI_EV_RNE BIT(9) 50#define ESPI_EV_TNF BIT(8) 51#define ESPI_EV_DON BIT(14) 52#define ESPI_EV_TXE BIT(15) 53#define ESPI_EV_RFCNT_SHIFT 24 54#define ESPI_EV_RFCNT_MASK (0x3f << ESPI_EV_RFCNT_SHIFT) 55 56#define ESPI_MODE_EN BIT(31) /* Enable interface */ 57#define ESPI_MODE_TXTHR(x) ((x) << 8) /* Tx FIFO threshold */ 58#define ESPI_MODE_RXTHR(x) ((x) << 0) /* Rx FIFO threshold */ 59 60#define ESPI_COM_CS(x) ((x) << 30) 61#define ESPI_COM_TRANLEN(x) ((x) << 0) 62 63#define ESPI_CSMODE_CI_INACTIVEHIGH BIT(31) 64#define ESPI_CSMODE_CP_BEGIN_EDGCLK BIT(30) 65#define ESPI_CSMODE_REV_MSB_FIRST BIT(29) 66#define ESPI_CSMODE_DIV16 BIT(28) 67#define ESPI_CSMODE_PM(x) ((x) << 24) 68#define ESPI_CSMODE_POL_ASSERTED_LOW BIT(20) 69#define ESPI_CSMODE_LEN(x) ((x) << 16) 70#define ESPI_CSMODE_CSBEF(x) ((x) << 12) 71#define ESPI_CSMODE_CSAFT(x) ((x) << 8) 72#define ESPI_CSMODE_CSCG(x) ((x) << 3) 73 74#define ESPI_CSMODE_INIT_VAL (ESPI_CSMODE_POL_ASSERTED_LOW | \ 75 ESPI_CSMODE_CSBEF(0) | ESPI_CSMODE_CSAFT(0) | \ 76 ESPI_CSMODE_CSCG(1)) 77 78#define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0 79 80void fsl_spi_cs_activate(struct spi_slave *slave, uint cs) 81{ 82 struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); 83 ccsr_espi_t *espi = fsl->espi; 84 unsigned int com = 0; 85 size_t data_len = fsl->data_len; 86 87 com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF)); 88 com |= ESPI_COM_CS(cs); 89 com |= ESPI_COM_TRANLEN(data_len - 1); 90 out_be32(&espi->com, com); 91} 92 93void fsl_spi_cs_deactivate(struct spi_slave *slave) 94{ 95 struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); 96 ccsr_espi_t *espi = fsl->espi; 97 98 /* clear the RXCNT and TXCNT */ 99 out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN)); 100 out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN); 101} 102 103static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout) 104{ 105 ccsr_espi_t *espi = fsl->espi; 106 unsigned int tmpdout, event; 107 int tmp_tx_timeout; 108 109 if (dout) 110 tmpdout = *(u32 *)dout; 111 else 112 tmpdout = 0; 113 114 out_be32(&espi->tx, tmpdout); 115 out_be32(&espi->event, ESPI_EV_TNF); 116 debug("***spi_xfer:...%08x written\n", tmpdout); 117 118 tmp_tx_timeout = fsl->tx_timeout; 119 /* Wait for eSPI transmit to go out */ 120 while (tmp_tx_timeout--) { 121 event = in_be32(&espi->event); 122 if (event & ESPI_EV_DON || event & ESPI_EV_TXE) { 123 out_be32(&espi->event, ESPI_EV_TXE); 124 break; 125 } 126 udelay(1); 127 } 128 129 if (tmp_tx_timeout < 0) 130 debug("***spi_xfer:...Tx timeout! event = %08x\n", event); 131} 132 133static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, 134 unsigned int bytes) 135{ 136 ccsr_espi_t *espi = fsl->espi; 137 unsigned int tmpdin, rx_times; 138 unsigned char *buf, *p_cursor; 139 140 if (bytes <= 0) 141 return 0; 142 143 rx_times = DIV_ROUND_UP(bytes, 4); 144 buf = (unsigned char *)malloc(4 * rx_times); 145 if (!buf) { 146 debug("SF: Failed to malloc memory.\n"); 147 return -1; 148 } 149 p_cursor = buf; 150 while (rx_times--) { 151 tmpdin = in_be32(&espi->rx); 152 debug("***spi_xfer:...%08x readed\n", tmpdin); 153 *(u32 *)p_cursor = tmpdin; 154 p_cursor += 4; 155 } 156 157 if (din) 158 memcpy(din, buf, bytes); 159 160 free(buf); 161 out_be32(&espi->event, ESPI_EV_RNE); 162 163 return bytes; 164} 165 166void espi_release_bus(struct fsl_spi_slave *fsl) 167{ 168 /* Disable the SPI hardware */ 169 out_be32(&fsl->espi->mode, 170 in_be32(&fsl->espi->mode) & (~ESPI_MODE_EN)); 171} 172 173int espi_xfer(struct fsl_spi_slave *fsl, uint cs, unsigned int bitlen, 174 const void *data_out, void *data_in, unsigned long flags) 175{ 176 struct spi_slave *slave = &fsl->slave; 177 ccsr_espi_t *espi = fsl->espi; 178 unsigned int event, rx_bytes; 179 const void *dout = NULL; 180 void *din = NULL; 181 int len = 0; 182 int num_blks, num_chunks, max_tran_len, tran_len; 183 int num_bytes; 184 unsigned char *buffer = NULL; 185 size_t buf_len; 186 u8 *cmd_buf = fsl->cmd_buf; 187 size_t cmd_len = fsl->cmd_len; 188 size_t data_len = bitlen / 8; 189 size_t rx_offset = 0; 190 int rf_cnt; 191 192 max_tran_len = fsl->max_transfer_length; 193 switch (flags) { 194 case SPI_XFER_BEGIN: 195 cmd_len = data_len; 196 fsl->cmd_len = cmd_len; 197 memcpy(cmd_buf, data_out, cmd_len); 198 return 0; 199 case 0: 200 case SPI_XFER_END: 201 if (bitlen == 0) { 202 fsl_spi_cs_deactivate(slave); 203 return 0; 204 } 205 buf_len = 2 * cmd_len + min(data_len, (size_t)max_tran_len); 206 len = cmd_len + data_len; 207 rx_offset = cmd_len; 208 buffer = (unsigned char *)malloc(buf_len); 209 if (!buffer) { 210 debug("SF: Failed to malloc memory.\n"); 211 return 1; 212 } 213 memcpy(buffer, cmd_buf, cmd_len); 214 if (data_in == NULL) 215 memcpy(buffer + cmd_len, data_out, data_len); 216 break; 217 case SPI_XFER_BEGIN | SPI_XFER_END: 218 len = data_len; 219 buffer = (unsigned char *)malloc(len * 2); 220 if (!buffer) { 221 debug("SF: Failed to malloc memory.\n"); 222 return 1; 223 } 224 memcpy(buffer, data_out, len); 225 rx_offset = len; 226 cmd_len = 0; 227 break; 228 } 229 230 debug("spi_xfer: data_out %08X(%p) data_in %08X(%p) len %u\n", 231 *(uint *)data_out, data_out, *(uint *)data_in, data_in, len); 232 233 num_chunks = DIV_ROUND_UP(data_len, max_tran_len); 234 while (num_chunks--) { 235 if (data_in) 236 din = buffer + rx_offset; 237 dout = buffer; 238 tran_len = min(data_len, (size_t)max_tran_len); 239 num_blks = DIV_ROUND_UP(tran_len + cmd_len, 4); 240 num_bytes = (tran_len + cmd_len) % 4; 241 fsl->data_len = tran_len + cmd_len; 242 fsl_spi_cs_activate(slave, cs); 243 244 /* Clear all eSPI events */ 245 out_be32(&espi->event , 0xffffffff); 246 /* handle data in 32-bit chunks */ 247 while (num_blks) { 248 event = in_be32(&espi->event); 249 if (event & ESPI_EV_TNF) { 250 fsl_espi_tx(fsl, dout); 251 /* Set up the next iteration */ 252 if (len > 4) { 253 len -= 4; 254 dout += 4; 255 } 256 } 257 258 event = in_be32(&espi->event); 259 if (event & ESPI_EV_RNE) { 260 rf_cnt = ((event & ESPI_EV_RFCNT_MASK) 261 >> ESPI_EV_RFCNT_SHIFT); 262 if (rf_cnt >= 4) 263 rx_bytes = 4; 264 else if (num_blks == 1 && rf_cnt == num_bytes) 265 rx_bytes = num_bytes; 266 else 267 continue; 268 if (fsl_espi_rx(fsl, din, rx_bytes) 269 == rx_bytes) { 270 num_blks--; 271 if (din) 272 din = (unsigned char *)din 273 + rx_bytes; 274 } 275 } 276 } 277 if (data_in) { 278 memcpy(data_in, buffer + 2 * cmd_len, tran_len); 279 if (*buffer == 0x0b) { 280 data_in += tran_len; 281 data_len -= tran_len; 282 *(int *)buffer += tran_len; 283 } 284 } 285 fsl_spi_cs_deactivate(slave); 286 } 287 288 free(buffer); 289 return 0; 290} 291 292void espi_claim_bus(struct fsl_spi_slave *fsl, unsigned int cs) 293{ 294 ccsr_espi_t *espi = fsl->espi; 295 unsigned char pm = fsl->pm; 296 unsigned int mode = fsl->mode; 297 unsigned int div16 = fsl->div16; 298 int i; 299 300 /* Enable eSPI interface */ 301 out_be32(&espi->mode, ESPI_MODE_RXTHR(3) 302 | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN); 303 304 out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */ 305 out_be32(&espi->mask, 0x00000000); /* Mask all eSPI interrupts */ 306 307 /* Init CS mode interface */ 308 for (i = 0; i < ESPI_MAX_CS_NUM; i++) 309 out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL); 310 311 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) & 312 ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16 313 | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK 314 | ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF))); 315 316 /* Set eSPI BRG clock source */ 317 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) 318 | ESPI_CSMODE_PM(pm) | div16); 319 320 /* Set eSPI mode */ 321 if (mode & SPI_CPHA) 322 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) 323 | ESPI_CSMODE_CP_BEGIN_EDGCLK); 324 if (mode & SPI_CPOL) 325 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) 326 | ESPI_CSMODE_CI_INACTIVEHIGH); 327 328 /* Character bit order: msb first */ 329 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) 330 | ESPI_CSMODE_REV_MSB_FIRST); 331 332 /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */ 333 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) 334 | ESPI_CSMODE_LEN(7)); 335} 336 337void espi_setup_slave(struct fsl_spi_slave *fsl) 338{ 339 unsigned int max_hz; 340 sys_info_t sysinfo; 341 unsigned long spibrg = 0; 342 unsigned long spi_freq = 0; 343 unsigned char pm = 0; 344 345 max_hz = fsl->speed_hz; 346 347 get_sys_info(&sysinfo); 348 spibrg = sysinfo.freq_systembus / 2; 349 fsl->div16 = 0; 350 if ((spibrg / max_hz) > 32) { 351 fsl->div16 = ESPI_CSMODE_DIV16; 352 pm = spibrg / (max_hz * 16 * 2); 353 if (pm > 16) { 354 pm = 16; 355 debug("max_hz is too low: %d Hz, %ld Hz is used.\n", 356 max_hz, spibrg / (32 * 16)); 357 } 358 } else { 359 pm = spibrg / (max_hz * 2); 360 } 361 if (pm) 362 pm--; 363 fsl->pm = pm; 364 365 if (fsl->div16) 366 spi_freq = spibrg / ((pm + 1) * 2 * 16); 367 else 368 spi_freq = spibrg / ((pm + 1) * 2); 369 370 /* set tx_timeout to 10 times of one espi FIFO entry go out */ 371 fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT 372 * 10), spi_freq);/* Set eSPI BRG clock source */ 373} 374 375#if !CONFIG_IS_ENABLED(DM_SPI) 376int spi_cs_is_valid(unsigned int bus, unsigned int cs) 377{ 378 return bus == 0 && cs < ESPI_MAX_CS_NUM; 379} 380 381struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, 382 unsigned int max_hz, unsigned int mode) 383{ 384 struct fsl_spi_slave *fsl; 385 386 if (!spi_cs_is_valid(bus, cs)) 387 return NULL; 388 389 fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs); 390 if (!fsl) 391 return NULL; 392 393 fsl->espi = (void *)(CFG_SYS_MPC85xx_ESPI_ADDR); 394 fsl->mode = mode; 395 fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; 396 fsl->speed_hz = max_hz; 397 398 espi_setup_slave(fsl); 399 400 return &fsl->slave; 401} 402 403void spi_free_slave(struct spi_slave *slave) 404{ 405 struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); 406 407 free(fsl); 408} 409 410int spi_claim_bus(struct spi_slave *slave) 411{ 412 struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); 413 414 espi_claim_bus(fsl, slave->cs); 415 416 return 0; 417} 418 419void spi_release_bus(struct spi_slave *slave) 420{ 421 struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); 422 423 espi_release_bus(fsl); 424} 425 426int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, 427 void *din, unsigned long flags) 428{ 429 struct fsl_spi_slave *fsl = (struct fsl_spi_slave *)slave; 430 431 return espi_xfer(fsl, slave->cs, bitlen, dout, din, flags); 432} 433#else 434static void __espi_set_speed(struct fsl_spi_slave *fsl) 435{ 436 espi_setup_slave(fsl); 437 438 /* Set eSPI BRG clock source */ 439 out_be32(&fsl->espi->csmode[fsl->cs], 440 in_be32(&fsl->espi->csmode[fsl->cs]) 441 | ESPI_CSMODE_PM(fsl->pm) | fsl->div16); 442} 443 444static void __espi_set_mode(struct fsl_spi_slave *fsl) 445{ 446 /* Set eSPI mode */ 447 if (fsl->mode & SPI_CPHA) 448 out_be32(&fsl->espi->csmode[fsl->cs], 449 in_be32(&fsl->espi->csmode[fsl->cs]) 450 | ESPI_CSMODE_CP_BEGIN_EDGCLK); 451 if (fsl->mode & SPI_CPOL) 452 out_be32(&fsl->espi->csmode[fsl->cs], 453 in_be32(&fsl->espi->csmode[fsl->cs]) 454 | ESPI_CSMODE_CI_INACTIVEHIGH); 455} 456 457static int fsl_espi_claim_bus(struct udevice *dev) 458{ 459 struct udevice *bus = dev->parent; 460 struct fsl_spi_slave *fsl = dev_get_priv(bus); 461 462 espi_claim_bus(fsl, fsl->cs); 463 464 return 0; 465} 466 467static int fsl_espi_release_bus(struct udevice *dev) 468{ 469 struct udevice *bus = dev->parent; 470 struct fsl_spi_slave *fsl = dev_get_priv(bus); 471 472 espi_release_bus(fsl); 473 474 return 0; 475} 476 477static int fsl_espi_xfer(struct udevice *dev, unsigned int bitlen, 478 const void *dout, void *din, unsigned long flags) 479{ 480 struct udevice *bus = dev->parent; 481 struct fsl_spi_slave *fsl = dev_get_priv(bus); 482 483 return espi_xfer(fsl, fsl->cs, bitlen, dout, din, flags); 484} 485 486static int fsl_espi_set_speed(struct udevice *bus, uint speed) 487{ 488 struct fsl_spi_slave *fsl = dev_get_priv(bus); 489 490 debug("%s speed %u\n", __func__, speed); 491 fsl->speed_hz = speed; 492 493 __espi_set_speed(fsl); 494 495 return 0; 496} 497 498static int fsl_espi_set_mode(struct udevice *bus, uint mode) 499{ 500 struct fsl_spi_slave *fsl = dev_get_priv(bus); 501 502 debug("%s mode %u\n", __func__, mode); 503 fsl->mode = mode; 504 505 __espi_set_mode(fsl); 506 507 return 0; 508} 509 510static int fsl_espi_child_pre_probe(struct udevice *dev) 511{ 512 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); 513 struct udevice *bus = dev->parent; 514 struct fsl_spi_slave *fsl = dev_get_priv(bus); 515 516 debug("%s cs %u\n", __func__, slave_plat->cs); 517 fsl->cs = slave_plat->cs; 518 519 return 0; 520} 521 522static int fsl_espi_probe(struct udevice *bus) 523{ 524 struct fsl_espi_plat *plat = dev_get_plat(bus); 525 struct fsl_spi_slave *fsl = dev_get_priv(bus); 526 527 fsl->espi = (ccsr_espi_t *)((u32)plat->regs_addr); 528 fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; 529 fsl->speed_hz = plat->speed_hz; 530 531 debug("%s probe done, bus-num %d.\n", bus->name, dev_seq(bus)); 532 533 return 0; 534} 535 536static const struct dm_spi_ops fsl_espi_ops = { 537 .claim_bus = fsl_espi_claim_bus, 538 .release_bus = fsl_espi_release_bus, 539 .xfer = fsl_espi_xfer, 540 .set_speed = fsl_espi_set_speed, 541 .set_mode = fsl_espi_set_mode, 542}; 543 544#if CONFIG_IS_ENABLED(OF_REAL) 545static int fsl_espi_of_to_plat(struct udevice *bus) 546{ 547 fdt_addr_t addr; 548 struct fsl_espi_plat *plat = dev_get_plat(bus); 549 const void *blob = gd->fdt_blob; 550 int node = dev_of_offset(bus); 551 552 addr = dev_read_addr(bus); 553 if (addr == FDT_ADDR_T_NONE) 554 return -EINVAL; 555 556 plat->regs_addr = lower_32_bits(addr); 557 plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency", 558 FSL_ESPI_DEFAULT_SCK_FREQ); 559 560 debug("ESPI: regs=%p, max-frequency=%d\n", 561 &plat->regs_addr, plat->speed_hz); 562 563 return 0; 564} 565 566static const struct udevice_id fsl_espi_ids[] = { 567 { .compatible = "fsl,mpc8536-espi" }, 568 { } 569}; 570#endif 571 572U_BOOT_DRIVER(fsl_espi) = { 573 .name = "fsl_espi", 574 .id = UCLASS_SPI, 575#if CONFIG_IS_ENABLED(OF_REAL) 576 .of_match = fsl_espi_ids, 577 .of_to_plat = fsl_espi_of_to_plat, 578#endif 579 .ops = &fsl_espi_ops, 580 .plat_auto = sizeof(struct fsl_espi_plat), 581 .priv_auto = sizeof(struct fsl_spi_slave), 582 .probe = fsl_espi_probe, 583 .child_pre_probe = fsl_espi_child_pre_probe, 584}; 585#endif 586