1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2012 4 * Altera Corporation <www.altera.com> 5 */ 6 7#include <clk.h> 8#include <log.h> 9#include <dm.h> 10#include <fdtdec.h> 11#include <malloc.h> 12#include <reset.h> 13#include <spi.h> 14#include <spi-mem.h> 15#include <dm/device_compat.h> 16#include <linux/err.h> 17#include <linux/errno.h> 18#include <linux/io.h> 19#include <linux/sizes.h> 20#include <linux/time.h> 21#include <zynqmp_firmware.h> 22#include "cadence_qspi.h" 23#include <dt-bindings/power/xlnx-versal-power.h> 24 25#define CQSPI_STIG_READ 0 26#define CQSPI_STIG_WRITE 1 27#define CQSPI_READ 2 28#define CQSPI_WRITE 3 29 30__weak int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, 31 const struct spi_mem_op *op) 32{ 33 return 0; 34} 35 36__weak int cadence_qspi_versal_flash_reset(struct udevice *dev) 37{ 38 return 0; 39} 40 41__weak ofnode cadence_qspi_get_subnode(struct udevice *dev) 42{ 43 return dev_read_first_subnode(dev); 44} 45 46static int cadence_spi_write_speed(struct udevice *bus, uint hz) 47{ 48 struct cadence_spi_priv *priv = dev_get_priv(bus); 49 50 cadence_qspi_apb_config_baudrate_div(priv->regbase, 51 priv->ref_clk_hz, hz); 52 53 /* Reconfigure delay timing if speed is changed. */ 54 cadence_qspi_apb_delay(priv->regbase, priv->ref_clk_hz, hz, 55 priv->tshsl_ns, priv->tsd2d_ns, 56 priv->tchsh_ns, priv->tslch_ns); 57 58 return 0; 59} 60 61static int cadence_spi_read_id(struct cadence_spi_priv *priv, u8 len, 62 u8 *idcode) 63{ 64 int err; 65 66 struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1), 67 SPI_MEM_OP_NO_ADDR, 68 SPI_MEM_OP_NO_DUMMY, 69 SPI_MEM_OP_DATA_IN(len, idcode, 1)); 70 71 err = cadence_qspi_apb_command_read_setup(priv, &op); 72 if (!err) 73 err = cadence_qspi_apb_command_read(priv, &op); 74 75 return err; 76} 77 78/* Calibration sequence to determine the read data capture delay register */ 79static int spi_calibration(struct udevice *bus, uint hz) 80{ 81 struct cadence_spi_priv *priv = dev_get_priv(bus); 82 void *base = priv->regbase; 83 unsigned int idcode = 0, temp = 0; 84 int err = 0, i, range_lo = -1, range_hi = -1; 85 86 /* start with slowest clock (1 MHz) */ 87 cadence_spi_write_speed(bus, 1000000); 88 89 /* configure the read data capture delay register to 0 */ 90 cadence_qspi_apb_readdata_capture(base, 1, 0); 91 92 /* Enable QSPI */ 93 cadence_qspi_apb_controller_enable(base); 94 95 /* read the ID which will be our golden value */ 96 err = cadence_spi_read_id(priv, 3, (u8 *)&idcode); 97 if (err) { 98 puts("SF: Calibration failed (read)\n"); 99 return err; 100 } 101 102 /* use back the intended clock and find low range */ 103 cadence_spi_write_speed(bus, hz); 104 for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) { 105 /* Disable QSPI */ 106 cadence_qspi_apb_controller_disable(base); 107 108 /* reconfigure the read data capture delay register */ 109 cadence_qspi_apb_readdata_capture(base, 1, i); 110 111 /* Enable back QSPI */ 112 cadence_qspi_apb_controller_enable(base); 113 114 /* issue a RDID to get the ID value */ 115 err = cadence_spi_read_id(priv, 3, (u8 *)&temp); 116 if (err) { 117 puts("SF: Calibration failed (read)\n"); 118 return err; 119 } 120 121 /* search for range lo */ 122 if (range_lo == -1 && temp == idcode) { 123 range_lo = i; 124 continue; 125 } 126 127 /* search for range hi */ 128 if (range_lo != -1 && temp != idcode) { 129 range_hi = i - 1; 130 break; 131 } 132 range_hi = i; 133 } 134 135 if (range_lo == -1) { 136 puts("SF: Calibration failed (low range)\n"); 137 return err; 138 } 139 140 /* Disable QSPI for subsequent initialization */ 141 cadence_qspi_apb_controller_disable(base); 142 143 /* configure the final value for read data capture delay register */ 144 cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2); 145 debug("SF: Read data capture delay calibrated to %i (%i - %i)\n", 146 (range_hi + range_lo) / 2, range_lo, range_hi); 147 148 /* just to ensure we do once only when speed or chip select change */ 149 priv->qspi_calibrated_hz = hz; 150 priv->qspi_calibrated_cs = spi_chip_select(bus); 151 152 return 0; 153} 154 155static int cadence_spi_set_speed(struct udevice *bus, uint hz) 156{ 157 struct cadence_spi_priv *priv = dev_get_priv(bus); 158 int err; 159 160 if (!hz || hz > priv->max_hz) 161 hz = priv->max_hz; 162 /* Disable QSPI */ 163 cadence_qspi_apb_controller_disable(priv->regbase); 164 165 /* 166 * If the device tree already provides a read delay value, use that 167 * instead of calibrating. 168 */ 169 if (priv->read_delay >= 0) { 170 cadence_spi_write_speed(bus, hz); 171 cadence_qspi_apb_readdata_capture(priv->regbase, 1, 172 priv->read_delay); 173 } else if (priv->previous_hz != hz || 174 priv->qspi_calibrated_hz != hz || 175 priv->qspi_calibrated_cs != spi_chip_select(bus)) { 176 /* 177 * Calibration required for different current SCLK speed, 178 * requested SCLK speed or chip select 179 */ 180 err = spi_calibration(bus, hz); 181 if (err) 182 return err; 183 184 /* prevent calibration run when same as previous request */ 185 priv->previous_hz = hz; 186 } 187 188 /* Enable QSPI */ 189 cadence_qspi_apb_controller_enable(priv->regbase); 190 191 debug("%s: speed=%d\n", __func__, hz); 192 193 return 0; 194} 195 196static int cadence_spi_probe(struct udevice *bus) 197{ 198 struct cadence_spi_plat *plat = dev_get_plat(bus); 199 struct cadence_spi_priv *priv = dev_get_priv(bus); 200 struct clk clk; 201 int ret; 202 203 priv->regbase = plat->regbase; 204 priv->ahbbase = plat->ahbbase; 205 priv->is_dma = plat->is_dma; 206 priv->is_decoded_cs = plat->is_decoded_cs; 207 priv->fifo_depth = plat->fifo_depth; 208 priv->fifo_width = plat->fifo_width; 209 priv->trigger_address = plat->trigger_address; 210 priv->read_delay = plat->read_delay; 211 priv->ahbsize = plat->ahbsize; 212 priv->max_hz = plat->max_hz; 213 214 priv->page_size = plat->page_size; 215 priv->block_size = plat->block_size; 216 priv->tshsl_ns = plat->tshsl_ns; 217 priv->tsd2d_ns = plat->tsd2d_ns; 218 priv->tchsh_ns = plat->tchsh_ns; 219 priv->tslch_ns = plat->tslch_ns; 220 221 if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) 222 xilinx_pm_request(PM_REQUEST_NODE, PM_DEV_OSPI, 223 ZYNQMP_PM_CAPABILITY_ACCESS, ZYNQMP_PM_MAX_QOS, 224 ZYNQMP_PM_REQUEST_ACK_NO, NULL); 225 226 if (priv->ref_clk_hz == 0) { 227 ret = clk_get_by_index(bus, 0, &clk); 228 if (ret) { 229#ifdef CONFIG_HAS_CQSPI_REF_CLK 230 priv->ref_clk_hz = CONFIG_CQSPI_REF_CLK; 231#elif defined(CONFIG_ARCH_SOCFPGA) 232 priv->ref_clk_hz = cm_get_qspi_controller_clk_hz(); 233#else 234 return ret; 235#endif 236 } else { 237 priv->ref_clk_hz = clk_get_rate(&clk); 238 if (IS_ERR_VALUE(priv->ref_clk_hz)) 239 return priv->ref_clk_hz; 240 } 241 } 242 243 priv->resets = devm_reset_bulk_get_optional(bus); 244 if (priv->resets) 245 reset_deassert_bulk(priv->resets); 246 247 if (!priv->qspi_is_init) { 248 cadence_qspi_apb_controller_init(priv); 249 priv->qspi_is_init = 1; 250 } 251 252 priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz); 253 254 /* Versal and Versal-NET use spi calibration to set read delay */ 255 if (CONFIG_IS_ENABLED(ARCH_VERSAL) || 256 CONFIG_IS_ENABLED(ARCH_VERSAL_NET)) 257 if (priv->read_delay >= 0) 258 priv->read_delay = -1; 259 260 /* Reset ospi flash device */ 261 return cadence_qspi_versal_flash_reset(bus); 262} 263 264static int cadence_spi_remove(struct udevice *dev) 265{ 266 struct cadence_spi_priv *priv = dev_get_priv(dev); 267 int ret = 0; 268 269 if (priv->resets) 270 ret = reset_release_bulk(priv->resets); 271 272 return ret; 273} 274 275static int cadence_spi_set_mode(struct udevice *bus, uint mode) 276{ 277 struct cadence_spi_priv *priv = dev_get_priv(bus); 278 279 /* Disable QSPI */ 280 cadence_qspi_apb_controller_disable(priv->regbase); 281 282 /* Set SPI mode */ 283 cadence_qspi_apb_set_clk_mode(priv->regbase, mode); 284 285 /* Enable Direct Access Controller */ 286 if (priv->use_dac_mode) 287 cadence_qspi_apb_dac_mode_enable(priv->regbase); 288 289 /* Enable QSPI */ 290 cadence_qspi_apb_controller_enable(priv->regbase); 291 292 return 0; 293} 294 295static int cadence_spi_mem_exec_op(struct spi_slave *spi, 296 const struct spi_mem_op *op) 297{ 298 struct udevice *bus = spi->dev->parent; 299 struct cadence_spi_priv *priv = dev_get_priv(bus); 300 void *base = priv->regbase; 301 int err = 0; 302 u32 mode; 303 304 /* Set Chip select */ 305 cadence_qspi_apb_chipselect(base, spi_chip_select(spi->dev), 306 priv->is_decoded_cs); 307 308 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { 309 /* 310 * Performing reads in DAC mode forces to read minimum 4 bytes 311 * which is unsupported on some flash devices during register 312 * reads, prefer STIG mode for such small reads. 313 */ 314 if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX) 315 mode = CQSPI_STIG_READ; 316 else 317 mode = CQSPI_READ; 318 } else { 319 if (op->data.nbytes <= CQSPI_STIG_DATA_LEN_MAX) 320 mode = CQSPI_STIG_WRITE; 321 else 322 mode = CQSPI_WRITE; 323 } 324 325 switch (mode) { 326 case CQSPI_STIG_READ: 327 err = cadence_qspi_apb_command_read_setup(priv, op); 328 if (!err) 329 err = cadence_qspi_apb_command_read(priv, op); 330 break; 331 case CQSPI_STIG_WRITE: 332 err = cadence_qspi_apb_command_write_setup(priv, op); 333 if (!err) 334 err = cadence_qspi_apb_command_write(priv, op); 335 break; 336 case CQSPI_READ: 337 err = cadence_qspi_apb_read_setup(priv, op); 338 if (!err) { 339 if (priv->is_dma) 340 err = cadence_qspi_apb_dma_read(priv, op); 341 else 342 err = cadence_qspi_apb_read_execute(priv, op); 343 } 344 break; 345 case CQSPI_WRITE: 346 err = cadence_qspi_apb_write_setup(priv, op); 347 if (!err) 348 err = cadence_qspi_apb_write_execute(priv, op); 349 break; 350 default: 351 err = -1; 352 break; 353 } 354 355 return err; 356} 357 358static bool cadence_spi_mem_supports_op(struct spi_slave *slave, 359 const struct spi_mem_op *op) 360{ 361 bool all_true, all_false; 362 363 /* 364 * op->dummy.dtr is required for converting nbytes into ncycles. 365 * Also, don't check the dtr field of the op phase having zero nbytes. 366 */ 367 all_true = op->cmd.dtr && 368 (!op->addr.nbytes || op->addr.dtr) && 369 (!op->dummy.nbytes || op->dummy.dtr) && 370 (!op->data.nbytes || op->data.dtr); 371 372 all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && 373 !op->data.dtr; 374 375 /* Mixed DTR modes not supported. */ 376 if (!(all_true || all_false)) 377 return false; 378 379 if (all_true) 380 return spi_mem_dtr_supports_op(slave, op); 381 else 382 return spi_mem_default_supports_op(slave, op); 383} 384 385static int cadence_spi_of_to_plat(struct udevice *bus) 386{ 387 struct cadence_spi_plat *plat = dev_get_plat(bus); 388 struct cadence_spi_priv *priv = dev_get_priv(bus); 389 ofnode subnode; 390 391 plat->regbase = devfdt_get_addr_index_ptr(bus, 0); 392 plat->ahbbase = devfdt_get_addr_size_index_ptr(bus, 1, &plat->ahbsize); 393 plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs"); 394 plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128); 395 plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4); 396 plat->trigger_address = dev_read_u32_default(bus, 397 "cdns,trigger-address", 398 0); 399 /* Use DAC mode only when MMIO window is at least 8M wide */ 400 if (plat->ahbsize >= SZ_8M) 401 priv->use_dac_mode = true; 402 403 plat->is_dma = dev_read_bool(bus, "cdns,is-dma"); 404 405 /* All other parameters are embedded in the child node */ 406 subnode = cadence_qspi_get_subnode(bus); 407 if (!ofnode_valid(subnode)) { 408 printf("Error: subnode with SPI flash config missing!\n"); 409 return -ENODEV; 410 } 411 412 /* Use 500 KHz as a suitable default */ 413 plat->max_hz = ofnode_read_u32_default(subnode, "spi-max-frequency", 414 500000); 415 416 /* Read other parameters from DT */ 417 plat->page_size = ofnode_read_u32_default(subnode, "page-size", 256); 418 plat->block_size = ofnode_read_u32_default(subnode, "block-size", 16); 419 plat->tshsl_ns = ofnode_read_u32_default(subnode, "cdns,tshsl-ns", 420 200); 421 plat->tsd2d_ns = ofnode_read_u32_default(subnode, "cdns,tsd2d-ns", 422 255); 423 plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20); 424 plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20); 425 /* 426 * Read delay should be an unsigned value but we use a signed integer 427 * so that negative values can indicate that the device tree did not 428 * specify any signed values and we need to perform the calibration 429 * sequence to find it out. 430 */ 431 plat->read_delay = ofnode_read_s32_default(subnode, "cdns,read-delay", 432 -1); 433 434 debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", 435 __func__, plat->regbase, plat->ahbbase, plat->max_hz, 436 plat->page_size); 437 438 return 0; 439} 440 441static const struct spi_controller_mem_ops cadence_spi_mem_ops = { 442 .exec_op = cadence_spi_mem_exec_op, 443 .supports_op = cadence_spi_mem_supports_op, 444}; 445 446static const struct dm_spi_ops cadence_spi_ops = { 447 .set_speed = cadence_spi_set_speed, 448 .set_mode = cadence_spi_set_mode, 449 .mem_ops = &cadence_spi_mem_ops, 450 /* 451 * cs_info is not needed, since we require all chip selects to be 452 * in the device tree explicitly 453 */ 454}; 455 456static const struct udevice_id cadence_spi_ids[] = { 457 { .compatible = "cdns,qspi-nor" }, 458 { .compatible = "ti,am654-ospi" }, 459 { } 460}; 461 462U_BOOT_DRIVER(cadence_spi) = { 463 .name = "cadence_spi", 464 .id = UCLASS_SPI, 465 .of_match = cadence_spi_ids, 466 .ops = &cadence_spi_ops, 467 .of_to_plat = cadence_spi_of_to_plat, 468 .plat_auto = sizeof(struct cadence_spi_plat), 469 .priv_auto = sizeof(struct cadence_spi_priv), 470 .probe = cadence_spi_probe, 471 .remove = cadence_spi_remove, 472 .flags = DM_FLAG_OS_PREPARE, 473}; 474