1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 4 * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <common.h> 8#include <errno.h> 9#include <log.h> 10#include <malloc.h> 11#include <wait_bit.h> 12#include <dm.h> 13#include <reset-uclass.h> 14#include <regmap.h> 15#include <syscon.h> 16#include <asm/global_data.h> 17#include <dt-bindings/reset/stih407-resets.h> 18#include <linux/bitops.h> 19#include <linux/printk.h> 20 21DECLARE_GLOBAL_DATA_PTR; 22 23struct sti_reset { 24 const struct syscfg_reset_controller_data *data; 25}; 26 27/** 28 * Reset channel description for a system configuration register based 29 * reset controller. 30 * 31 * @compatible: Compatible string of the syscon containing this 32 * channel's control and ack (status) bits. 33 * @reset_offset: Reset register offset in sysconf bank. 34 * @reset_bit: Bit number in reset register. 35 * @ack_offset: Ack reset register offset in syscon bank. 36 * @ack_bit: Bit number in Ack reset register. 37 * @deassert_cnt: incremented when reset is deasserted, reset can only be 38 * asserted when equal to 0 39 */ 40 41struct syscfg_reset_channel_data { 42 const char *compatible; 43 int reset_offset; 44 int reset_bit; 45 int ack_offset; 46 int ack_bit; 47 int deassert_cnt; 48}; 49 50/** 51 * Description of a system configuration register based reset controller. 52 * 53 * @wait_for_ack: The controller will wait for reset assert and de-assert to 54 * be "ack'd" in a channel's ack field. 55 * @active_low: Are the resets in this controller active low, i.e. clearing 56 * the reset bit puts the hardware into reset. 57 * @nr_channels: The number of reset channels in this controller. 58 * @channels: An array of reset channel descriptions. 59 */ 60struct syscfg_reset_controller_data { 61 bool wait_for_ack; 62 bool active_low; 63 int nr_channels; 64 struct syscfg_reset_channel_data *channels; 65}; 66 67/* STiH407 Peripheral powerdown definitions. */ 68static const char stih407_core[] = "st,stih407-core-syscfg"; 69static const char stih407_sbc_reg[] = "st,stih407-sbc-reg-syscfg"; 70static const char stih407_lpm[] = "st,stih407-lpm-syscfg"; 71 72#define _SYSCFG_RST_CH(_c, _rr, _rb, _ar, _ab) \ 73 { .compatible = _c, \ 74 .reset_offset = _rr, \ 75 .reset_bit = _rb, \ 76 .ack_offset = _ar, \ 77 .ack_bit = _ab, } 78 79#define _SYSCFG_RST_CH_NO_ACK(_c, _rr, _rb) \ 80 { .compatible = _c, \ 81 .reset_offset = _rr, \ 82 .reset_bit = _rb, } 83 84#define STIH407_SRST_CORE(_reg, _bit) \ 85 _SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit) 86 87#define STIH407_SRST_SBC(_reg, _bit) \ 88 _SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit) 89 90#define STIH407_SRST_LPM(_reg, _bit) \ 91 _SYSCFG_RST_CH_NO_ACK(stih407_lpm, _reg, _bit) 92 93#define STIH407_PDN_0(_bit) \ 94 _SYSCFG_RST_CH(stih407_core, SYSCFG_5000, _bit, SYSSTAT_5500, _bit) 95#define STIH407_PDN_1(_bit) \ 96 _SYSCFG_RST_CH(stih407_core, SYSCFG_5001, _bit, SYSSTAT_5501, _bit) 97#define STIH407_PDN_ETH(_bit, _stat) \ 98 _SYSCFG_RST_CH(stih407_sbc_reg, SYSCFG_4032, _bit, SYSSTAT_4520, _stat) 99 100/* Powerdown requests control 0 */ 101#define SYSCFG_5000 0x0 102#define SYSSTAT_5500 0x7d0 103/* Powerdown requests control 1 (High Speed Links) */ 104#define SYSCFG_5001 0x4 105#define SYSSTAT_5501 0x7d4 106 107/* Ethernet powerdown/status/reset */ 108#define SYSCFG_4032 0x80 109#define SYSSTAT_4520 0x820 110#define SYSCFG_4002 0x8 111 112static struct syscfg_reset_channel_data stih407_powerdowns[] = { 113 [STIH407_EMISS_POWERDOWN] = STIH407_PDN_0(1), 114 [STIH407_NAND_POWERDOWN] = STIH407_PDN_0(0), 115 [STIH407_USB3_POWERDOWN] = STIH407_PDN_1(6), 116 [STIH407_USB2_PORT1_POWERDOWN] = STIH407_PDN_1(5), 117 [STIH407_USB2_PORT0_POWERDOWN] = STIH407_PDN_1(4), 118 [STIH407_PCIE1_POWERDOWN] = STIH407_PDN_1(3), 119 [STIH407_PCIE0_POWERDOWN] = STIH407_PDN_1(2), 120 [STIH407_SATA1_POWERDOWN] = STIH407_PDN_1(1), 121 [STIH407_SATA0_POWERDOWN] = STIH407_PDN_1(0), 122 [STIH407_ETH1_POWERDOWN] = STIH407_PDN_ETH(0, 2), 123}; 124 125/* Reset Generator control 0/1 */ 126#define SYSCFG_5128 0x200 127#define SYSCFG_5131 0x20c 128#define SYSCFG_5132 0x210 129 130#define LPM_SYSCFG_1 0x4 /* Softreset IRB & SBC UART */ 131 132static struct syscfg_reset_channel_data stih407_softresets[] = { 133 [STIH407_ETH1_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 4), 134 [STIH407_MMC1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 3), 135 [STIH407_USB2_PORT0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 28), 136 [STIH407_USB2_PORT1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 29), 137 [STIH407_PICOPHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 30), 138 [STIH407_IRB_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 6), 139 [STIH407_PCIE0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 6), 140 [STIH407_PCIE1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 15), 141 [STIH407_SATA0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 7), 142 [STIH407_SATA1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 16), 143 [STIH407_MIPHY0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 4), 144 [STIH407_MIPHY1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 13), 145 [STIH407_MIPHY2_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 22), 146 [STIH407_SATA0_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 5), 147 [STIH407_SATA1_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 14), 148 [STIH407_DELTA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 3), 149 [STIH407_BLITTER_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 10), 150 [STIH407_HDTVOUT_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 11), 151 [STIH407_HDQVDP_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 12), 152 [STIH407_VDP_AUX_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 14), 153 [STIH407_COMPO_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 15), 154 [STIH407_HDMI_TX_PHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 21), 155 [STIH407_JPEG_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 23), 156 [STIH407_VP8_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 24), 157 [STIH407_GPU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 30), 158 [STIH407_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 0), 159 [STIH407_ERAM_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 1), 160 [STIH407_LPM_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 2), 161 [STIH407_KEYSCAN_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 8), 162 [STIH407_ST231_AUD_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 26), 163 [STIH407_ST231_DMU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 27), 164 [STIH407_ST231_GP0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 28), 165 [STIH407_ST231_GP1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5128, 2), 166}; 167 168/* PicoPHY reset/control */ 169#define SYSCFG_5061 0x0f4 170 171static struct syscfg_reset_channel_data stih407_picophyresets[] = { 172 [STIH407_PICOPHY0_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 5), 173 [STIH407_PICOPHY1_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 6), 174 [STIH407_PICOPHY2_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 7), 175}; 176 177static const struct 178syscfg_reset_controller_data stih407_powerdown_controller = { 179 .wait_for_ack = true, 180 .nr_channels = ARRAY_SIZE(stih407_powerdowns), 181 .channels = stih407_powerdowns, 182}; 183 184static const struct 185syscfg_reset_controller_data stih407_softreset_controller = { 186 .wait_for_ack = false, 187 .active_low = true, 188 .nr_channels = ARRAY_SIZE(stih407_softresets), 189 .channels = stih407_softresets, 190}; 191 192static const struct 193syscfg_reset_controller_data stih407_picophyreset_controller = { 194 .wait_for_ack = false, 195 .nr_channels = ARRAY_SIZE(stih407_picophyresets), 196 .channels = stih407_picophyresets, 197}; 198 199phys_addr_t sti_reset_get_regmap(const char *compatible) 200{ 201 struct udevice *syscon; 202 struct regmap *regmap; 203 int node, ret; 204 205 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, 206 compatible); 207 if (node < 0) { 208 pr_err("unable to find %s node\n", compatible); 209 return node; 210 } 211 212 ret = uclass_get_device_by_of_offset(UCLASS_SYSCON, node, &syscon); 213 if (ret) { 214 pr_err("%s: uclass_get_device_by_of_offset failed: %d\n", 215 __func__, ret); 216 return ret; 217 } 218 219 regmap = syscon_get_regmap(syscon); 220 if (!regmap) { 221 pr_err("unable to get regmap for %s\n", syscon->name); 222 return -ENODEV; 223 } 224 225 return regmap->ranges[0].start; 226} 227 228static int sti_reset_program_hw(struct reset_ctl *reset_ctl, int assert) 229{ 230 struct udevice *dev = reset_ctl->dev; 231 struct syscfg_reset_controller_data *reset_desc = 232 (struct syscfg_reset_controller_data *)(dev->driver_data); 233 struct syscfg_reset_channel_data *ch; 234 phys_addr_t base; 235 u32 ctrl_val = reset_desc->active_low ? !assert : !!assert; 236 void __iomem *reg; 237 238 /* check if reset id is inside available range */ 239 if (reset_ctl->id >= reset_desc->nr_channels) 240 return -EINVAL; 241 242 /* get reset sysconf register base address */ 243 base = sti_reset_get_regmap(reset_desc->channels[reset_ctl->id].compatible); 244 245 ch = &reset_desc->channels[reset_ctl->id]; 246 247 /* check the deassert counter to assert reset when it reaches 0 */ 248 if (!assert) { 249 ch->deassert_cnt++; 250 if (ch->deassert_cnt > 1) 251 return 0; 252 } else { 253 if (ch->deassert_cnt > 0) { 254 ch->deassert_cnt--; 255 if (ch->deassert_cnt > 0) 256 return 0; 257 } else 258 pr_err("Reset balancing error: reset_ctl=%p dev=%p id=%lu\n", 259 reset_ctl, reset_ctl->dev, reset_ctl->id); 260 } 261 262 reg = (void __iomem *)base + ch->reset_offset; 263 264 if (ctrl_val) 265 generic_set_bit(ch->reset_bit, reg); 266 else 267 generic_clear_bit(ch->reset_bit, reg); 268 269 if (!reset_desc->wait_for_ack) 270 return 0; 271 272 reg = (void __iomem *)base + ch->ack_offset; 273 if (wait_for_bit_le32(reg, BIT(ch->ack_bit), ctrl_val, 274 1000, false)) { 275 pr_err("Stuck on waiting ack reset_ctl=%p dev=%p id=%lu\n", 276 reset_ctl, reset_ctl->dev, reset_ctl->id); 277 278 return -ETIMEDOUT; 279 } 280 281 return 0; 282} 283 284static int sti_reset_assert(struct reset_ctl *reset_ctl) 285{ 286 return sti_reset_program_hw(reset_ctl, true); 287} 288 289static int sti_reset_deassert(struct reset_ctl *reset_ctl) 290{ 291 return sti_reset_program_hw(reset_ctl, false); 292} 293 294struct reset_ops sti_reset_ops = { 295 .rst_assert = sti_reset_assert, 296 .rst_deassert = sti_reset_deassert, 297}; 298 299static int sti_reset_probe(struct udevice *dev) 300{ 301 struct sti_reset *priv = dev_get_priv(dev); 302 303 priv->data = (void *)dev_get_driver_data(dev); 304 305 return 0; 306} 307 308static const struct udevice_id sti_reset_ids[] = { 309 { 310 .compatible = "st,stih407-picophyreset", 311 .data = (ulong)&stih407_picophyreset_controller, 312 }, 313 { 314 .compatible = "st,stih407-powerdown", 315 .data = (ulong)&stih407_powerdown_controller, 316 }, 317 { 318 .compatible = "st,stih407-softreset", 319 .data = (ulong)&stih407_softreset_controller, 320 }, 321 { } 322}; 323 324U_BOOT_DRIVER(sti_reset) = { 325 .name = "sti_reset", 326 .id = UCLASS_RESET, 327 .of_match = sti_reset_ids, 328 .probe = sti_reset_probe, 329 .priv_auto = sizeof(struct sti_reset), 330 .ops = &sti_reset_ops, 331}; 332