1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * D1/R528/T113 DRAM controller register and constant defines 4 * 5 * (C) Copyright 2022 Arm Ltd. 6 * Based on H6 and H616 header, which are: 7 * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io> 8 * (C) Copyright 2020 Jernej Skrabec <jernej.skrabec@siol.net> 9 * 10 */ 11 12#ifndef _SUNXI_DRAM_SUN20I_D1_H 13#define _SUNXI_DRAM_SUN20I_D1_H 14 15enum sunxi_dram_type { 16 SUNXI_DRAM_TYPE_DDR2 = 2, 17 SUNXI_DRAM_TYPE_DDR3 = 3, 18 SUNXI_DRAM_TYPE_LPDDR2 = 6, 19 SUNXI_DRAM_TYPE_LPDDR3 = 7, 20}; 21 22/* 23 * This structure contains a mixture of fixed configuration settings, 24 * variables that are used at runtime to communicate settings between 25 * different stages and functions, and unused values. 26 * This is copied from Allwinner's boot0 data structure, which can be 27 * found at offset 0x38 in any boot0 binary. To allow matching up some 28 * board specific settings, this struct is kept compatible, even though 29 * we don't need all members in our code. 30 */ 31typedef struct dram_para { 32 /* normal configuration */ 33 const u32 dram_clk; 34 const u32 dram_type; 35 const u32 dram_zq; 36 const u32 dram_odt_en; 37 38 /* timing configuration */ 39 const u32 dram_mr0; 40 const u32 dram_mr1; 41 const u32 dram_mr2; 42 const u32 dram_mr3; 43 const u32 dram_tpr0; //DRAMTMG0 44 const u32 dram_tpr1; //DRAMTMG1 45 const u32 dram_tpr2; //DRAMTMG2 46 const u32 dram_tpr3; //DRAMTMG3 47 const u32 dram_tpr4; //DRAMTMG4 48 const u32 dram_tpr5; //DRAMTMG5 49 const u32 dram_tpr6; //DRAMTMG8 50 const u32 dram_tpr7; 51 const u32 dram_tpr8; 52 const u32 dram_tpr9; 53 const u32 dram_tpr10; 54 const u32 dram_tpr11; 55 const u32 dram_tpr12; 56} dram_para_t; 57 58typedef struct dram_config { 59 /* control configuration */ 60 u32 dram_para1; 61 u32 dram_para2; 62 /* contains a bitfield of DRAM setup settings */ 63 u32 dram_tpr13; 64} dram_config_t; 65 66static inline int ns_to_t(int nanoseconds) 67{ 68 const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; 69 70 return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); 71} 72 73#endif /* _SUNXI_DRAM_SUN20I_D1_H */ 74