1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd 4 */ 5 6#include <common.h> 7#include <dm.h> 8#include <log.h> 9#include <dm/pinctrl.h> 10#include <regmap.h> 11#include <linux/bitops.h> 12 13#include "pinctrl-rockchip.h" 14 15static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 16 { 17 /* edphdmi_cecinoutt1 */ 18 .bank_num = 7, 19 .pin = 16, 20 .func = 2, 21 .route_offset = 0x264, 22 .route_val = BIT(16 + 12) | BIT(12), 23 }, { 24 /* edphdmi_cecinout */ 25 .bank_num = 7, 26 .pin = 23, 27 .func = 4, 28 .route_offset = 0x264, 29 .route_val = BIT(16 + 12), 30 }, 31}; 32 33static int rk3288_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) 34{ 35 struct rockchip_pinctrl_priv *priv = bank->priv; 36 int iomux_num = (pin / 8); 37 struct regmap *regmap; 38 int reg, ret, mask, mux_type; 39 u8 bit; 40 u32 data; 41 42 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) 43 ? priv->regmap_pmu : priv->regmap_base; 44 45 /* get basic quadrupel of mux registers and the correct reg inside */ 46 mux_type = bank->iomux[iomux_num].type; 47 reg = bank->iomux[iomux_num].offset; 48 reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask); 49 50 /* bank0 is special, there are no higher 16 bit writing bits. */ 51 if (bank->bank_num == 0) { 52 regmap_read(regmap, reg, &data); 53 data &= ~(mask << bit); 54 } else { 55 /* enable the write to the equivalent lower bits */ 56 data = (mask << (bit + 16)); 57 } 58 59 data |= (mux & mask) << bit; 60 ret = regmap_write(regmap, reg, data); 61 62 return ret; 63} 64 65#define RK3288_PULL_OFFSET 0x140 66#define RK3288_PULL_PMU_OFFSET 0x64 67 68static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, 69 int pin_num, struct regmap **regmap, 70 int *reg, u8 *bit) 71{ 72 struct rockchip_pinctrl_priv *priv = bank->priv; 73 74 /* The first 24 pins of the first bank are located in PMU */ 75 if (bank->bank_num == 0) { 76 *regmap = priv->regmap_pmu; 77 *reg = RK3288_PULL_PMU_OFFSET; 78 } else { 79 *regmap = priv->regmap_base; 80 *reg = RK3288_PULL_OFFSET; 81 82 /* correct the offset, as we're starting with the 2nd bank */ 83 *reg -= 0x10; 84 *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE; 85 } 86 87 *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4); 88 89 *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); 90 *bit *= ROCKCHIP_PULL_BITS_PER_PIN; 91} 92 93static int rk3288_set_pull(struct rockchip_pin_bank *bank, 94 int pin_num, int pull) 95{ 96 struct regmap *regmap; 97 int reg, ret; 98 u8 bit, type; 99 u32 data; 100 101 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) 102 return -ENOTSUPP; 103 104 rk3288_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); 105 type = bank->pull_type[pin_num / 8]; 106 ret = rockchip_translate_pull_value(type, pull); 107 if (ret < 0) { 108 debug("unsupported pull setting %d\n", pull); 109 return ret; 110 } 111 112 /* bank0 is special, there are no higher 16 bit writing bits */ 113 if (bank->bank_num == 0) { 114 regmap_read(regmap, reg, &data); 115 data &= ~(((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << bit); 116 } else { 117 /* enable the write to the equivalent lower bits */ 118 data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); 119 } 120 121 data |= (ret << bit); 122 ret = regmap_write(regmap, reg, data); 123 124 return ret; 125} 126 127#define RK3288_DRV_PMU_OFFSET 0x70 128#define RK3288_DRV_GRF_OFFSET 0x1c0 129 130static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 131 int pin_num, struct regmap **regmap, 132 int *reg, u8 *bit) 133{ 134 struct rockchip_pinctrl_priv *priv = bank->priv; 135 136 /* The first 24 pins of the first bank are located in PMU */ 137 if (bank->bank_num == 0) { 138 *regmap = priv->regmap_pmu; 139 *reg = RK3288_DRV_PMU_OFFSET; 140 } else { 141 *regmap = priv->regmap_base; 142 *reg = RK3288_DRV_GRF_OFFSET; 143 144 /* correct the offset, as we're starting with the 2nd bank */ 145 *reg -= 0x10; 146 *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE; 147 } 148 149 *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4); 150 *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG); 151 *bit *= ROCKCHIP_DRV_BITS_PER_PIN; 152} 153 154static int rk3288_set_drive(struct rockchip_pin_bank *bank, 155 int pin_num, int strength) 156{ 157 struct regmap *regmap; 158 int reg, ret; 159 u32 data; 160 u8 bit; 161 int type = bank->drv[pin_num / 8].drv_type; 162 163 rk3288_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); 164 ret = rockchip_translate_drive_value(type, strength); 165 if (ret < 0) { 166 debug("unsupported driver strength %d\n", strength); 167 return ret; 168 } 169 170 /* bank0 is special, there are no higher 16 bit writing bits. */ 171 if (bank->bank_num == 0) { 172 regmap_read(regmap, reg, &data); 173 data &= ~(((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << bit); 174 } else { 175 /* enable the write to the equivalent lower bits */ 176 data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16); 177 } 178 179 data |= (ret << bit); 180 ret = regmap_write(regmap, reg, data); 181 return ret; 182} 183 184static struct rockchip_pin_bank rk3288_pin_banks[] = { 185 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, 186 IOMUX_SOURCE_PMU, 187 IOMUX_SOURCE_PMU, 188 IOMUX_UNROUTED 189 ), 190 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, 191 IOMUX_UNROUTED, 192 IOMUX_UNROUTED, 193 0 194 ), 195 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), 196 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), 197 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, 198 IOMUX_WIDTH_4BIT, 199 0, 200 0 201 ), 202 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, 203 0, 204 0, 205 IOMUX_UNROUTED 206 ), 207 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), 208 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, 209 0, 210 IOMUX_WIDTH_4BIT, 211 IOMUX_UNROUTED 212 ), 213 PIN_BANK(8, 16, "gpio8"), 214}; 215 216static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 217 .pin_banks = rk3288_pin_banks, 218 .nr_banks = ARRAY_SIZE(rk3288_pin_banks), 219 .grf_mux_offset = 0x0, 220 .pmu_mux_offset = 0x84, 221 .iomux_routes = rk3288_mux_route_data, 222 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), 223 .set_mux = rk3288_set_mux, 224 .set_pull = rk3288_set_pull, 225 .set_drive = rk3288_set_drive, 226}; 227 228static const struct udevice_id rk3288_pinctrl_ids[] = { 229 { 230 .compatible = "rockchip,rk3288-pinctrl", 231 .data = (ulong)&rk3288_pin_ctrl 232 }, 233 { } 234}; 235 236U_BOOT_DRIVER(rockchip_rk3288_pinctrl) = { 237 .name = "rockchip_rk3288_pinctrl", 238 .id = UCLASS_PINCTRL, 239 .of_match = rk3288_pinctrl_ids, 240 .priv_auto = sizeof(struct rockchip_pinctrl_priv), 241 .ops = &rockchip_pinctrl_ops, 242#if CONFIG_IS_ENABLED(OF_REAL) 243 .bind = dm_scan_fdt_dev, 244#endif 245 .probe = rockchip_pinctrl_probe, 246}; 247