1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 */ 5 6#include <common.h> 7#include <errno.h> 8#include <linux/bitops.h> 9#include <asm/io.h> 10#include <firmware/imx/sci/sci.h> 11#include <misc.h> 12 13#include "pinctrl-imx.h" 14 15#define PADRING_IFMUX_EN_SHIFT 31 16#define PADRING_IFMUX_EN_MASK BIT(31) 17#define PADRING_GP_EN_SHIFT 30 18#define PADRING_GP_EN_MASK BIT(30) 19#define PADRING_IFMUX_SHIFT 27 20#define PADRING_IFMUX_MASK GENMASK(29, 27) 21 22static int imx_pinconf_scu_set(struct imx_pinctrl_soc_info *info, u32 pad, 23 u32 mux, u32 val) 24{ 25 int ret; 26 27 /* 28 * Mux should be done in pmx set, but we do not have a good api 29 * to handle that in scfw, so config it in pad conf func 30 */ 31 32 if (!sc_rm_is_pad_owned(-1, pad)) { 33 debug("Pad[%u] is not owned by curr partition\n", pad); 34 return -EPERM; 35 } 36 37 val |= PADRING_IFMUX_EN_MASK; 38 val |= PADRING_GP_EN_MASK; 39 val |= (mux << PADRING_IFMUX_SHIFT) & PADRING_IFMUX_MASK; 40 41 ret = sc_pad_set(-1, pad, val); 42 if (ret) 43 printf("%s %d\n", __func__, ret); 44 45 return 0; 46} 47 48int imx_pinctrl_scu_conf_pins(struct imx_pinctrl_soc_info *info, u32 *pin_data, 49 int npins) 50{ 51 int pin_id, mux, config_val; 52 int i, j = 0; 53 int ret; 54 55 /* 56 * Refer to linux documentation for details: 57 * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt 58 */ 59 for (i = 0; i < npins; i++) { 60 pin_id = pin_data[j++]; 61 mux = pin_data[j++]; 62 config_val = pin_data[j++]; 63 64 ret = imx_pinconf_scu_set(info, pin_id, mux, config_val); 65 if (ret && ret != -EPERM) 66 printf("Set pin %d, mux %d, val %d, error\n", pin_id, 67 mux, config_val); 68 } 69 70 return 0; 71} 72