1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Cadence Sierra PHY Driver 4 * 5 * Based on the linux driver provided by Cadence 6 * 7 * Copyright (c) 2018 Cadence Design Systems 8 * Author: Alan Douglas <adouglas@cadence.com> 9 * 10 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ 11 * Jean-Jacques Hiblot <jjhiblot@ti.com> 12 * 13 */ 14#include <common.h> 15#include <clk.h> 16#include <linux/delay.h> 17#include <linux/clk-provider.h> 18#include <generic-phy.h> 19#include <reset.h> 20#include <dm/device.h> 21#include <dm/device-internal.h> 22#include <dm/device_compat.h> 23#include <dm/lists.h> 24#include <dm/read.h> 25#include <dm/uclass.h> 26#include <dm/devres.h> 27#include <linux/io.h> 28#include <dt-bindings/phy/phy.h> 29#include <dt-bindings/phy/phy-cadence.h> 30#include <regmap.h> 31 32#define usleep_range(a, b) udelay((b)) 33 34#define NUM_SSC_MODE 3 35#define NUM_PHY_TYPE 4 36 37/* PHY register offsets */ 38#define SIERRA_COMMON_CDB_OFFSET 0x0 39#define SIERRA_MACRO_ID_REG 0x0 40#define SIERRA_CMN_PLLLC_GEN_PREG 0x42 41#define SIERRA_CMN_PLLLC_MODE_PREG 0x48 42#define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49 43#define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A 44#define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG 0x4B 45#define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F 46#define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50 47#define SIERRA_CMN_PLLLC_DSMCORR_PREG 0x51 48#define SIERRA_CMN_PLLLC_SS_PREG 0x52 49#define SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG 0x53 50#define SIERRA_CMN_PLLLC_SSTWOPT_PREG 0x54 51#define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62 52#define SIERRA_CMN_REFRCV_PREG 0x98 53#define SIERRA_CMN_REFRCV1_PREG 0xB8 54#define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2 55#define SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG 0x63 56#define SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG 0xCA 57#define SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG 0xD0 58#define SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG 0xE2 59 60#define SIERRA_LANE_CDB_OFFSET(ln, offset) \ 61 (0x4000 + ((ln) * (0x800 >> (2 - (offset))))) 62 63#define SIERRA_DET_STANDEC_A_PREG 0x000 64#define SIERRA_DET_STANDEC_B_PREG 0x001 65#define SIERRA_DET_STANDEC_C_PREG 0x002 66#define SIERRA_DET_STANDEC_D_PREG 0x003 67#define SIERRA_DET_STANDEC_E_PREG 0x004 68#define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG 0x008 69#define SIERRA_PSM_A0IN_TMR_PREG 0x009 70#define SIERRA_PSM_A3IN_TMR_PREG 0x00C 71#define SIERRA_PSM_DIAG_PREG 0x015 72#define SIERRA_PSC_LN_A3_PREG 0x023 73#define SIERRA_PSC_LN_A4_PREG 0x024 74#define SIERRA_PSC_LN_IDLE_PREG 0x026 75#define SIERRA_PSC_TX_A0_PREG 0x028 76#define SIERRA_PSC_TX_A1_PREG 0x029 77#define SIERRA_PSC_TX_A2_PREG 0x02A 78#define SIERRA_PSC_TX_A3_PREG 0x02B 79#define SIERRA_PSC_RX_A0_PREG 0x030 80#define SIERRA_PSC_RX_A1_PREG 0x031 81#define SIERRA_PSC_RX_A2_PREG 0x032 82#define SIERRA_PSC_RX_A3_PREG 0x033 83#define SIERRA_PLLCTRL_SUBRATE_PREG 0x03A 84#define SIERRA_PLLCTRL_GEN_A_PREG 0x03B 85#define SIERRA_PLLCTRL_GEN_D_PREG 0x03E 86#define SIERRA_PLLCTRL_CPGAIN_MODE_PREG 0x03F 87#define SIERRA_PLLCTRL_STATUS_PREG 0x044 88#define SIERRA_CLKPATH_BIASTRIM_PREG 0x04B 89#define SIERRA_DFE_BIASTRIM_PREG 0x04C 90#define SIERRA_DRVCTRL_ATTEN_PREG 0x06A 91#define SIERRA_DRVCTRL_BOOST_PREG 0x06F 92#define SIERRA_CLKPATHCTRL_TMR_PREG 0x081 93#define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG 0x085 94#define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG 0x086 95#define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG 0x087 96#define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG 0x088 97#define SIERRA_CREQ_DCBIASATTEN_OVR_PREG 0x08C 98#define SIERRA_CREQ_CCLKDET_MODE01_PREG 0x08E 99#define SIERRA_RX_CTLE_CAL_PREG 0x08F 100#define SIERRA_RX_CTLE_MAINTENANCE_PREG 0x091 101#define SIERRA_CREQ_FSMCLK_SEL_PREG 0x092 102#define SIERRA_CREQ_EQ_CTRL_PREG 0x093 103#define SIERRA_CREQ_SPARE_PREG 0x096 104#define SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG 0x097 105#define SIERRA_CTLELUT_CTRL_PREG 0x098 106#define SIERRA_DFE_ECMP_RATESEL_PREG 0x0C0 107#define SIERRA_DFE_SMP_RATESEL_PREG 0x0C1 108#define SIERRA_DEQ_PHALIGN_CTRL 0x0C4 109#define SIERRA_DEQ_CONCUR_CTRL1_PREG 0x0C8 110#define SIERRA_DEQ_CONCUR_CTRL2_PREG 0x0C9 111#define SIERRA_DEQ_EPIPWR_CTRL2_PREG 0x0CD 112#define SIERRA_DEQ_FAST_MAINT_CYCLES_PREG 0x0CE 113#define SIERRA_DEQ_ERRCMP_CTRL_PREG 0x0D0 114#define SIERRA_DEQ_OFFSET_CTRL_PREG 0x0D8 115#define SIERRA_DEQ_GAIN_CTRL_PREG 0x0E0 116#define SIERRA_DEQ_VGATUNE_CTRL_PREG 0x0E1 117#define SIERRA_DEQ_GLUT0 0x0E8 118#define SIERRA_DEQ_GLUT1 0x0E9 119#define SIERRA_DEQ_GLUT2 0x0EA 120#define SIERRA_DEQ_GLUT3 0x0EB 121#define SIERRA_DEQ_GLUT4 0x0EC 122#define SIERRA_DEQ_GLUT5 0x0ED 123#define SIERRA_DEQ_GLUT6 0x0EE 124#define SIERRA_DEQ_GLUT7 0x0EF 125#define SIERRA_DEQ_GLUT8 0x0F0 126#define SIERRA_DEQ_GLUT9 0x0F1 127#define SIERRA_DEQ_GLUT10 0x0F2 128#define SIERRA_DEQ_GLUT11 0x0F3 129#define SIERRA_DEQ_GLUT12 0x0F4 130#define SIERRA_DEQ_GLUT13 0x0F5 131#define SIERRA_DEQ_GLUT14 0x0F6 132#define SIERRA_DEQ_GLUT15 0x0F7 133#define SIERRA_DEQ_GLUT16 0x0F8 134#define SIERRA_DEQ_ALUT0 0x108 135#define SIERRA_DEQ_ALUT1 0x109 136#define SIERRA_DEQ_ALUT2 0x10A 137#define SIERRA_DEQ_ALUT3 0x10B 138#define SIERRA_DEQ_ALUT4 0x10C 139#define SIERRA_DEQ_ALUT5 0x10D 140#define SIERRA_DEQ_ALUT6 0x10E 141#define SIERRA_DEQ_ALUT7 0x10F 142#define SIERRA_DEQ_ALUT8 0x110 143#define SIERRA_DEQ_ALUT9 0x111 144#define SIERRA_DEQ_ALUT10 0x112 145#define SIERRA_DEQ_ALUT11 0x113 146#define SIERRA_DEQ_ALUT12 0x114 147#define SIERRA_DEQ_ALUT13 0x115 148#define SIERRA_DEQ_DFETAP_CTRL_PREG 0x128 149#define SIERRA_DEQ_DFETAP0 0x129 150#define SIERRA_DEQ_DFETAP1 0x12B 151#define SIERRA_DEQ_DFETAP2 0x12D 152#define SIERRA_DEQ_DFETAP3 0x12F 153#define SIERRA_DEQ_DFETAP4 0x131 154#define SIERRA_DFE_EN_1010_IGNORE_PREG 0x134 155#define SIERRA_DEQ_PRECUR_PREG 0x138 156#define SIERRA_DEQ_POSTCUR_PREG 0x140 157#define SIERRA_DEQ_POSTCUR_DECR_PREG 0x142 158#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 159#define SIERRA_DEQ_TAU_CTRL2_PREG 0x151 160#define SIERRA_DEQ_TAU_CTRL3_PREG 0x152 161#define SIERRA_DEQ_OPENEYE_CTRL_PREG 0x158 162#define SIERRA_DEQ_PICTRL_PREG 0x161 163#define SIERRA_CPICAL_TMRVAL_MODE1_PREG 0x170 164#define SIERRA_CPICAL_TMRVAL_MODE0_PREG 0x171 165#define SIERRA_CPICAL_PICNT_MODE1_PREG 0x174 166#define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C 167#define SIERRA_CPI_RESBIAS_BIN_PREG 0x17E 168#define SIERRA_CPI_TRIM_PREG 0x17F 169#define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG 0x183 170#define SIERRA_EPI_CTRL_PREG 0x187 171#define SIERRA_LFPSDET_SUPPORT_PREG 0x188 172#define SIERRA_LFPSFILT_NS_PREG 0x18A 173#define SIERRA_LFPSFILT_RD_PREG 0x18B 174#define SIERRA_LFPSFILT_MP_PREG 0x18C 175#define SIERRA_SIGDET_SUPPORT_PREG 0x190 176#define SIERRA_SDFILT_H2L_A_PREG 0x191 177#define SIERRA_SDFILT_L2H_PREG 0x193 178#define SIERRA_RXBUFFER_CTLECTRL_PREG 0x19E 179#define SIERRA_RXBUFFER_RCDFECTRL_PREG 0x19F 180#define SIERRA_RXBUFFER_DFECTRL_PREG 0x1A0 181#define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG 0x14F 182#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150 183 184#define SIERRA_PHY_PCS_COMMON_OFFSET 0xc000 185#define SIERRA_PHY_PIPE_CMN_CTRL1 0x0 186#define SIERRA_PHY_PLL_CFG 0xe 187 188/* PHY PMA common registers */ 189#define SIERRA_PHY_PMA_COMMON_OFFSET 0xe000 190#define SIERRA_PHY_PMA_CMN_CTRL 0x0 191 192/* PHY PCS lane registers */ 193#define SIERRA_PHY_PCS_LANE_CDB_OFFSET(ln, offset) \ 194 (0xD000 + ((ln) * (0x800 >> (3 - (offset))))) 195#define SIERRA_PHY_ISO_LINK_CTRL 0xB 196 197/* PHY PMA lane registers */ 198#define SIERRA_PHY_PMA_LANE_CDB_OFFSET(ln, offset) \ 199 (0xF000 + ((ln) * (0x800 >> (3 - (offset))))) 200#define SIERRA_PHY_PMA_XCVR_CTRL 0x000 201 202#define SIERRA_MACRO_ID 0x00007364 203#define SIERRA_MAX_LANES 16 204#define PLL_LOCK_TIME 100 205 206#define CDNS_SIERRA_INPUT_CLOCKS 5 207enum cdns_sierra_clock_input { 208 PHY_CLK, 209 CMN_REFCLK_DIG_DIV, 210 CMN_REFCLK1_DIG_DIV, 211 PLL0_REFCLK, 212 PLL1_REFCLK, 213}; 214 215#define SIERRA_NUM_CMN_PLLC 2 216#define SIERRA_NUM_CMN_PLLC_PARENTS 2 217 218static const struct reg_field macro_id_type = 219 REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15); 220static const struct reg_field phy_pll_cfg_1 = 221 REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1); 222static const struct reg_field pma_cmn_ready = 223 REG_FIELD(SIERRA_PHY_PMA_CMN_CTRL, 0, 0); 224static const struct reg_field pllctrl_lock = 225 REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0); 226static const struct reg_field phy_iso_link_ctrl_1 = 227 REG_FIELD(SIERRA_PHY_ISO_LINK_CTRL, 1, 1); 228 229static const char * const clk_names[] = { 230 [CDNS_SIERRA_PLL_CMNLC] = "pll_cmnlc", 231 [CDNS_SIERRA_PLL_CMNLC1] = "pll_cmnlc1", 232}; 233 234enum cdns_sierra_cmn_plllc { 235 CMN_PLLLC, 236 CMN_PLLLC1, 237}; 238 239struct cdns_sierra_pll_mux_reg_fields { 240 struct reg_field pfdclk_sel_preg; 241 struct reg_field plllc1en_field; 242 struct reg_field termen_field; 243}; 244 245static const struct cdns_sierra_pll_mux_reg_fields cmn_plllc_pfdclk1_sel_preg[] = { 246 [CMN_PLLLC] = { 247 .pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC_GEN_PREG, 1, 1), 248 .plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 8, 8), 249 .termen_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 0, 0), 250 }, 251 [CMN_PLLLC1] = { 252 .pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC1_GEN_PREG, 1, 1), 253 .plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 8, 8), 254 .termen_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 0, 0), 255 }, 256}; 257 258struct cdns_sierra_pll_mux { 259 struct cdns_sierra_phy *sp; 260 struct clk *clk; 261 struct clk *parent_clks[2]; 262 struct regmap_field *pfdclk_sel_preg; 263 struct regmap_field *plllc1en_field; 264 struct regmap_field *termen_field; 265}; 266 267#define reset_control_assert(rst) cdns_reset_assert(rst) 268#define reset_control_deassert(rst) cdns_reset_deassert(rst) 269#define reset_control reset_ctl 270 271enum cdns_sierra_phy_type { 272 TYPE_NONE, 273 TYPE_PCIE, 274 TYPE_USB, 275 TYPE_QSGMII 276}; 277 278enum cdns_sierra_ssc_mode { 279 NO_SSC, 280 EXTERNAL_SSC, 281 INTERNAL_SSC 282}; 283 284struct cdns_sierra_inst { 285 enum cdns_sierra_phy_type phy_type; 286 u32 num_lanes; 287 u32 mlane; 288 struct reset_ctl_bulk *lnk_rst; 289 enum cdns_sierra_ssc_mode ssc_mode; 290}; 291 292struct cdns_reg_pairs { 293 u16 val; 294 u32 off; 295}; 296 297struct cdns_sierra_vals { 298 const struct cdns_reg_pairs *reg_pairs; 299 u32 num_regs; 300}; 301 302struct cdns_sierra_data { 303 u32 id_value; 304 u8 block_offset_shift; 305 u8 reg_offset_shift; 306 struct cdns_sierra_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] 307 [NUM_SSC_MODE]; 308 struct cdns_sierra_vals *phy_pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] 309 [NUM_SSC_MODE]; 310 struct cdns_sierra_vals *pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] 311 [NUM_SSC_MODE]; 312 struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] 313 [NUM_SSC_MODE]; 314}; 315 316struct cdns_sierra_phy { 317 struct udevice *dev; 318 void *base; 319 size_t size; 320 struct regmap *regmap; 321 struct cdns_sierra_data *init_data; 322 struct cdns_sierra_inst *phys[SIERRA_MAX_LANES]; 323 struct reset_control *phy_rst; 324 struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES]; 325 struct regmap *regmap_phy_pcs_common_cdb; 326 struct regmap *regmap_phy_pcs_lane_cdb[SIERRA_MAX_LANES]; 327 struct regmap *regmap_phy_pma_common_cdb; 328 struct regmap *regmap_phy_pma_lane_cdb[SIERRA_MAX_LANES]; 329 struct regmap *regmap_common_cdb; 330 struct regmap_field *macro_id_type; 331 struct regmap_field *phy_pll_cfg_1; 332 struct regmap_field *pma_cmn_ready; 333 struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES]; 334 struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_CMN_PLLC]; 335 struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_CMN_PLLC]; 336 struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC]; 337 struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS]; 338 struct regmap_field *phy_iso_link_ctrl_1[SIERRA_MAX_LANES]; 339 int nsubnodes; 340 u32 num_lanes; 341 bool autoconf; 342 unsigned int already_configured; 343}; 344 345static inline int cdns_reset_assert(struct reset_control *rst) 346{ 347 if (rst) 348 return reset_assert(rst); 349 else 350 return 0; 351} 352 353static inline int cdns_reset_deassert(struct reset_control *rst) 354{ 355 if (rst) 356 return reset_deassert(rst); 357 else 358 return 0; 359} 360 361static int cdns_sierra_link_init(struct phy *gphy) 362{ 363 struct cdns_sierra_inst *ins = dev_get_priv(gphy->dev); 364 struct cdns_sierra_phy *phy = dev_get_priv(gphy->dev->parent); 365 struct cdns_sierra_data *init_data = phy->init_data; 366 struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals; 367 enum cdns_sierra_phy_type phy_type = ins->phy_type; 368 enum cdns_sierra_ssc_mode ssc = ins->ssc_mode; 369 struct cdns_sierra_vals *phy_pma_ln_vals; 370 const struct cdns_reg_pairs *reg_pairs; 371 struct cdns_sierra_vals *pcs_cmn_vals; 372 struct regmap *regmap = phy->regmap; 373 u32 num_regs; 374 int i, j; 375 376 /* Initialise the PHY registers, unless auto configured */ 377 if (phy->autoconf || phy->already_configured || phy->nsubnodes > 1) 378 return 0; 379 380 clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000); 381 clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000); 382 383 /* PHY PCS common registers configurations */ 384 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc]; 385 if (pcs_cmn_vals) { 386 reg_pairs = pcs_cmn_vals->reg_pairs; 387 num_regs = pcs_cmn_vals->num_regs; 388 regmap = phy->regmap_phy_pcs_common_cdb; 389 for (i = 0; i < num_regs; i++) 390 regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val); 391 } 392 393 /* PHY PMA lane registers configurations */ 394 phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_type][TYPE_NONE][ssc]; 395 if (phy_pma_ln_vals) { 396 reg_pairs = phy_pma_ln_vals->reg_pairs; 397 num_regs = phy_pma_ln_vals->num_regs; 398 for (i = 0; i < ins->num_lanes; i++) { 399 regmap = phy->regmap_phy_pma_lane_cdb[i + ins->mlane]; 400 for (j = 0; j < num_regs; j++) 401 regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val); 402 } 403 } 404 405 /* PMA common registers configurations */ 406 pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc]; 407 if (pma_cmn_vals) { 408 reg_pairs = pma_cmn_vals->reg_pairs; 409 num_regs = pma_cmn_vals->num_regs; 410 regmap = phy->regmap_common_cdb; 411 for (i = 0; i < num_regs; i++) 412 regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val); 413 } 414 415 /* PMA TX lane registers configurations */ 416 pma_ln_vals = init_data->pma_ln_vals[phy_type][TYPE_NONE][ssc]; 417 if (pma_ln_vals) { 418 reg_pairs = pma_ln_vals->reg_pairs; 419 num_regs = pma_ln_vals->num_regs; 420 for (i = 0; i < ins->num_lanes; i++) { 421 regmap = phy->regmap_lane_cdb[i + ins->mlane]; 422 for (j = 0; j < num_regs; j++) 423 regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val); 424 } 425 } 426 427 return 0; 428} 429 430static int cdns_sierra_link_on(struct phy *gphy) 431{ 432 struct cdns_sierra_inst *ins = dev_get_priv(gphy->dev); 433 struct cdns_sierra_phy *sp = dev_get_priv(gphy->dev->parent); 434 435 struct udevice *dev = gphy->dev; 436 u32 val; 437 int ret; 438 439 if (sp->already_configured) { 440 usleep_range(5000, 10000); 441 return 0; 442 } 443 444 if (sp->nsubnodes == 1) { 445 /* Take the PHY out of reset */ 446 ret = reset_control_deassert(sp->phy_rst); 447 if (ret) { 448 dev_err(dev, "Failed to take the PHY out of reset\n"); 449 return ret; 450 } 451 } 452 453 /* Take the PHY lane group out of reset */ 454 ret = reset_deassert_bulk(ins->lnk_rst); 455 if (ret) { 456 dev_err(dev, "Failed to take the PHY lane out of reset\n"); 457 return ret; 458 } 459 460 if (ins->phy_type == TYPE_PCIE || ins->phy_type == TYPE_USB) { 461 ret = regmap_field_read_poll_timeout(sp->phy_iso_link_ctrl_1[ins->mlane], 462 val, !val, 1000, PLL_LOCK_TIME); 463 if (ret) { 464 dev_err(dev, "Timeout waiting for PHY status ready\n"); 465 return ret; 466 } 467 } 468 469 /* 470 * Wait for cmn_ready assertion 471 * PHY_PMA_CMN_CTRL[0] == 1 472 */ 473 ret = regmap_field_read_poll_timeout(sp->pma_cmn_ready, val, val, 474 1000, PLL_LOCK_TIME); 475 if (ret) { 476 dev_err(dev, "Timeout waiting for CMN ready\n"); 477 return ret; 478 } 479 480 ret = regmap_field_read_poll_timeout(sp->pllctrl_lock[ins->mlane], 481 val, val, 1000, PLL_LOCK_TIME); 482 if (ret < 0) 483 dev_err(dev, "PLL lock of lane failed\n"); 484 485 reset_control_assert(sp->phy_rst); 486 reset_control_deassert(sp->phy_rst); 487 488 return ret; 489} 490 491static int cdns_sierra_link_off(struct phy *gphy) 492{ 493 struct cdns_sierra_inst *ins = dev_get_priv(gphy->dev); 494 495 return reset_assert_bulk(ins->lnk_rst); 496} 497 498static int cdns_sierra_link_reset(struct phy *gphy) 499{ 500 struct cdns_sierra_phy *sp = dev_get_priv(gphy->dev->parent); 501 502 reset_control_assert(sp->phy_rst); 503 reset_control_deassert(sp->phy_rst); 504 return 0; 505}; 506 507static const struct phy_ops ops = { 508 .init = cdns_sierra_link_init, 509 .power_on = cdns_sierra_link_on, 510 .power_off = cdns_sierra_link_off, 511 .reset = cdns_sierra_link_reset, 512}; 513 514struct cdns_sierra_pll_mux_sel { 515 enum cdns_sierra_cmn_plllc mux_sel; 516 u32 table[2]; 517 const char *node_name; 518 u32 num_parents; 519 u32 parents[2]; 520}; 521 522static struct cdns_sierra_pll_mux_sel pll_clk_mux_sel[] = { 523 { 524 .num_parents = 2, 525 .parents = { PLL0_REFCLK, PLL1_REFCLK }, 526 .mux_sel = CMN_PLLLC, 527 .table = { 0, 1 }, 528 .node_name = "pll_cmnlc", 529 }, 530 { 531 .num_parents = 2, 532 .parents = { PLL1_REFCLK, PLL0_REFCLK }, 533 .mux_sel = CMN_PLLLC1, 534 .table = { 1, 0 }, 535 .node_name = "pll_cmnlc1", 536 }, 537}; 538 539static int cdns_sierra_pll_mux_set_parent(struct clk *clk, struct clk *parent) 540{ 541 struct udevice *dev = clk->dev; 542 struct cdns_sierra_pll_mux *priv = dev_get_priv(dev); 543 struct cdns_sierra_pll_mux_sel *data = dev_get_plat(dev); 544 struct cdns_sierra_phy *sp = priv->sp; 545 int ret; 546 int i; 547 548 for (i = 0; i < ARRAY_SIZE(priv->parent_clks); i++) { 549 if (parent->dev == priv->parent_clks[i]->dev) 550 break; 551 } 552 553 if (i == ARRAY_SIZE(priv->parent_clks)) 554 return -EINVAL; 555 556 ret = regmap_field_write(sp->cmn_refrcv_refclk_plllc1en_preg[data[clk->id].mux_sel], i); 557 ret |= regmap_field_write(sp->cmn_refrcv_refclk_termen_preg[data[clk->id].mux_sel], i); 558 ret |= regmap_field_write(sp->cmn_plllc_pfdclk1_sel_preg[data[clk->id].mux_sel], 559 data[clk->id].table[i]); 560 561 return ret; 562} 563 564static const struct clk_ops cdns_sierra_pll_mux_ops = { 565 .set_parent = cdns_sierra_pll_mux_set_parent, 566}; 567 568static int cdns_sierra_pll_mux_probe(struct udevice *dev) 569{ 570 struct cdns_sierra_pll_mux *priv = dev_get_priv(dev); 571 struct cdns_sierra_phy *sp = dev_get_priv(dev->parent); 572 struct cdns_sierra_pll_mux_sel *data = dev_get_plat(dev); 573 struct clk *clk; 574 int i, j; 575 576 for (j = 0; j < SIERRA_NUM_CMN_PLLC; j++) { 577 for (i = 0; i < ARRAY_SIZE(priv->parent_clks); i++) { 578 clk = sp->input_clks[data[j].parents[i]]; 579 if (IS_ERR_OR_NULL(clk)) { 580 dev_err(dev, "No parent clock for PLL mux clocks\n"); 581 return IS_ERR(clk) ? PTR_ERR(clk) : -ENOENT; 582 } 583 priv->parent_clks[i] = clk; 584 } 585 } 586 587 priv->sp = dev_get_priv(dev->parent); 588 589 return 0; 590} 591 592U_BOOT_DRIVER(cdns_sierra_pll_mux_clk) = { 593 .name = "cdns_sierra_mux_clk", 594 .id = UCLASS_CLK, 595 .priv_auto = sizeof(struct cdns_sierra_pll_mux), 596 .ops = &cdns_sierra_pll_mux_ops, 597 .probe = cdns_sierra_pll_mux_probe, 598 .plat_auto = sizeof(struct cdns_sierra_pll_mux_sel) * SIERRA_NUM_CMN_PLLC, 599}; 600 601static int cdns_sierra_pll_bind_of_clocks(struct cdns_sierra_phy *sp) 602{ 603 struct udevice *dev = sp->dev; 604 struct driver *cdns_sierra_clk_drv; 605 struct cdns_sierra_pll_mux_sel *data = pll_clk_mux_sel; 606 int i, rc; 607 608 cdns_sierra_clk_drv = lists_driver_lookup_name("cdns_sierra_mux_clk"); 609 if (!cdns_sierra_clk_drv) { 610 dev_err(dev, "Can not find driver 'cdns_sierra_mux_clk'\n"); 611 return -ENOENT; 612 } 613 614 rc = device_bind(dev, cdns_sierra_clk_drv, "pll_mux_clk", 615 data, dev_ofnode(dev), NULL); 616 if (rc) { 617 dev_err(dev, "cannot bind driver for clock %s\n", 618 clk_names[i]); 619 } 620 621 return 0; 622} 623 624static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst, 625 ofnode child) 626{ 627 u32 phy_type; 628 629 if (ofnode_read_u32(child, "reg", &inst->mlane)) 630 return -EINVAL; 631 632 if (ofnode_read_u32(child, "cdns,num-lanes", &inst->num_lanes)) 633 return -EINVAL; 634 635 if (ofnode_read_u32(child, "cdns,phy-type", &phy_type)) 636 return -EINVAL; 637 638 switch (phy_type) { 639 case PHY_TYPE_PCIE: 640 inst->phy_type = TYPE_PCIE; 641 break; 642 case PHY_TYPE_USB3: 643 inst->phy_type = TYPE_USB; 644 break; 645 case PHY_TYPE_QSGMII: 646 inst->phy_type = TYPE_QSGMII; 647 break; 648 default: 649 return -EINVAL; 650 } 651 652 inst->ssc_mode = EXTERNAL_SSC; 653 ofnode_read_u32(child, "cdns,ssc-mode", &inst->ssc_mode); 654 655 return 0; 656} 657 658static struct regmap *cdns_regmap_init(struct udevice *dev, void __iomem *base, 659 u32 block_offset, u8 block_offset_shift, 660 u8 reg_offset_shift) 661{ 662 struct cdns_sierra_phy *sp = dev_get_priv(dev); 663 struct regmap_config config; 664 665 config.r_start = (ulong)(base + (block_offset << block_offset_shift)); 666 config.r_size = sp->size - (block_offset << block_offset_shift); 667 config.reg_offset_shift = reg_offset_shift; 668 config.width = REGMAP_SIZE_16; 669 670 return devm_regmap_init(dev, NULL, NULL, &config); 671} 672 673static int cdns_regfield_init(struct cdns_sierra_phy *sp) 674{ 675 struct udevice *dev = sp->dev; 676 struct regmap_field *field; 677 struct reg_field reg_field; 678 struct regmap *regmap; 679 int i; 680 681 regmap = sp->regmap_common_cdb; 682 field = devm_regmap_field_alloc(dev, regmap, macro_id_type); 683 if (IS_ERR(field)) { 684 dev_err(dev, "MACRO_ID_TYPE reg field init failed\n"); 685 return PTR_ERR(field); 686 } 687 sp->macro_id_type = field; 688 689 for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) { 690 reg_field = cmn_plllc_pfdclk1_sel_preg[i].pfdclk_sel_preg; 691 field = devm_regmap_field_alloc(dev, regmap, reg_field); 692 if (IS_ERR(field)) { 693 dev_err(dev, "PLLLC%d_PFDCLK1_SEL failed\n", i); 694 return PTR_ERR(field); 695 } 696 sp->cmn_plllc_pfdclk1_sel_preg[i] = field; 697 698 reg_field = cmn_plllc_pfdclk1_sel_preg[i].plllc1en_field; 699 field = devm_regmap_field_alloc(dev, regmap, reg_field); 700 if (IS_ERR(field)) { 701 dev_err(dev, "REFRCV%d_REFCLK_PLLLC1EN failed\n", i); 702 return PTR_ERR(field); 703 } 704 sp->cmn_refrcv_refclk_plllc1en_preg[i] = field; 705 706 reg_field = cmn_plllc_pfdclk1_sel_preg[i].termen_field; 707 field = devm_regmap_field_alloc(dev, regmap, reg_field); 708 if (IS_ERR(field)) { 709 dev_err(dev, "REFRCV%d_REFCLK_TERMEN failed\n", i); 710 return PTR_ERR(field); 711 } 712 sp->cmn_refrcv_refclk_termen_preg[i] = field; 713 } 714 715 regmap = sp->regmap_phy_pcs_common_cdb; 716 field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1); 717 if (IS_ERR(field)) { 718 dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n"); 719 return PTR_ERR(field); 720 } 721 sp->phy_pll_cfg_1 = field; 722 723 regmap = sp->regmap_phy_pma_common_cdb; 724 field = devm_regmap_field_alloc(dev, regmap, pma_cmn_ready); 725 if (IS_ERR(field)) { 726 dev_err(dev, "PHY_PMA_CMN_CTRL reg field init failed\n"); 727 return PTR_ERR(field); 728 } 729 sp->pma_cmn_ready = field; 730 731 for (i = 0; i < SIERRA_MAX_LANES; i++) { 732 regmap = sp->regmap_lane_cdb[i]; 733 field = devm_regmap_field_alloc(dev, regmap, pllctrl_lock); 734 if (IS_ERR(field)) { 735 dev_err(dev, "P%d_ENABLE reg field init failed\n", i); 736 return PTR_ERR(field); 737 } 738 sp->pllctrl_lock[i] = field; 739 } 740 741 for (i = 0; i < SIERRA_MAX_LANES; i++) { 742 regmap = sp->regmap_phy_pcs_lane_cdb[i]; 743 field = devm_regmap_field_alloc(dev, regmap, phy_iso_link_ctrl_1); 744 if (IS_ERR(field)) { 745 dev_err(dev, "PHY_ISO_LINK_CTRL reg field init for lane %d failed\n", i); 746 return PTR_ERR(field); 747 } 748 sp->phy_iso_link_ctrl_1[i] = field; 749 } 750 751 return 0; 752} 753 754static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp, 755 void __iomem *base, u8 block_offset_shift, 756 u8 reg_offset_shift) 757{ 758 struct udevice *dev = sp->dev; 759 struct regmap *regmap; 760 u32 block_offset; 761 int i; 762 763 for (i = 0; i < SIERRA_MAX_LANES; i++) { 764 block_offset = SIERRA_LANE_CDB_OFFSET(i, reg_offset_shift); 765 regmap = cdns_regmap_init(dev, base, block_offset, 766 block_offset_shift, reg_offset_shift); 767 if (IS_ERR(regmap)) { 768 dev_err(dev, "Failed to init lane CDB regmap\n"); 769 return PTR_ERR(regmap); 770 } 771 sp->regmap_lane_cdb[i] = regmap; 772 } 773 774 regmap = cdns_regmap_init(dev, base, SIERRA_COMMON_CDB_OFFSET, 775 block_offset_shift, reg_offset_shift); 776 if (IS_ERR(regmap)) { 777 dev_err(dev, "Failed to init common CDB regmap\n"); 778 return PTR_ERR(regmap); 779 } 780 sp->regmap_common_cdb = regmap; 781 782 regmap = cdns_regmap_init(dev, base, SIERRA_PHY_PCS_COMMON_OFFSET, 783 block_offset_shift, reg_offset_shift); 784 if (IS_ERR(regmap)) { 785 dev_err(dev, "Failed to init PHY PCS common CDB regmap\n"); 786 return PTR_ERR(regmap); 787 } 788 sp->regmap_phy_pcs_common_cdb = regmap; 789 790 for (i = 0; i < SIERRA_MAX_LANES; i++) { 791 block_offset = SIERRA_PHY_PCS_LANE_CDB_OFFSET(i, reg_offset_shift); 792 regmap = cdns_regmap_init(dev, base, block_offset, 793 block_offset_shift, reg_offset_shift); 794 if (IS_ERR(regmap)) { 795 dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n"); 796 return PTR_ERR(regmap); 797 } 798 sp->regmap_phy_pcs_lane_cdb[i] = regmap; 799 } 800 801 regmap = cdns_regmap_init(dev, base, SIERRA_PHY_PMA_COMMON_OFFSET, 802 block_offset_shift, reg_offset_shift); 803 if (IS_ERR(regmap)) { 804 dev_err(dev, "Failed to init PHY PMA common CDB regmap\n"); 805 return PTR_ERR(regmap); 806 } 807 sp->regmap_phy_pma_common_cdb = regmap; 808 809 for (i = 0; i < SIERRA_MAX_LANES; i++) { 810 block_offset = SIERRA_PHY_PMA_LANE_CDB_OFFSET(i, reg_offset_shift); 811 regmap = cdns_regmap_init(dev, base, block_offset, 812 block_offset_shift, reg_offset_shift); 813 if (IS_ERR(regmap)) { 814 dev_err(dev, "Failed to init PHY PMA lane CDB regmap\n"); 815 return PTR_ERR(regmap); 816 } 817 sp->regmap_phy_pma_lane_cdb[i] = regmap; 818 } 819 820 return 0; 821} 822 823static int cdns_sierra_phy_configure_multilink(struct cdns_sierra_phy *sp) 824{ 825 const struct cdns_sierra_data *init_data = sp->init_data; 826 enum cdns_sierra_phy_type phy_t1, phy_t2, tmp_phy_type; 827 struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals; 828 struct cdns_sierra_vals *phy_pma_ln_vals; 829 const struct cdns_reg_pairs *reg_pairs; 830 struct cdns_sierra_vals *pcs_cmn_vals; 831 int i, j, node, mlane, num_lanes, ret; 832 enum cdns_sierra_ssc_mode ssc; 833 struct regmap *regmap; 834 u32 num_regs; 835 836 /* Maximum 2 links (subnodes) are supported */ 837 if (sp->nsubnodes != 2) 838 return -EINVAL; 839 840 clk_set_rate(sp->input_clks[CMN_REFCLK_DIG_DIV], 25000000); 841 clk_set_rate(sp->input_clks[CMN_REFCLK1_DIG_DIV], 25000000); 842 843 /* PHY configured to use both PLL LC and LC1 */ 844 regmap_field_write(sp->phy_pll_cfg_1, 0x1); 845 846 phy_t1 = sp->phys[0]->phy_type; 847 phy_t2 = sp->phys[1]->phy_type; 848 849 /* 850 * First configure the PHY for first link with phy_t1. Get the array 851 * values as [phy_t1][phy_t2][ssc]. 852 */ 853 for (node = 0; node < sp->nsubnodes; node++) { 854 if (node == 1) { 855 /* 856 * If first link with phy_t1 is configured, then 857 * configure the PHY for second link with phy_t2. 858 * Get the array values as [phy_t2][phy_t1][ssc]. 859 */ 860 tmp_phy_type = phy_t1; 861 phy_t1 = phy_t2; 862 phy_t2 = tmp_phy_type; 863 } 864 865 mlane = sp->phys[node]->mlane; 866 ssc = sp->phys[node]->ssc_mode; 867 num_lanes = sp->phys[node]->num_lanes; 868 869 /* PHY PCS common registers configurations */ 870 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc]; 871 if (pcs_cmn_vals) { 872 reg_pairs = pcs_cmn_vals->reg_pairs; 873 num_regs = pcs_cmn_vals->num_regs; 874 regmap = sp->regmap_phy_pcs_common_cdb; 875 for (i = 0; i < num_regs; i++) 876 regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val); 877 } 878 879 /* PHY PMA lane registers configurations */ 880 phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_t1][phy_t2][ssc]; 881 if (phy_pma_ln_vals) { 882 reg_pairs = phy_pma_ln_vals->reg_pairs; 883 num_regs = phy_pma_ln_vals->num_regs; 884 for (i = 0; i < num_lanes; i++) { 885 regmap = sp->regmap_phy_pma_lane_cdb[i + mlane]; 886 for (j = 0; j < num_regs; j++) 887 regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val); 888 } 889 } 890 891 /* PMA common registers configurations */ 892 pma_cmn_vals = init_data->pma_cmn_vals[phy_t1][phy_t2][ssc]; 893 if (pma_cmn_vals) { 894 reg_pairs = pma_cmn_vals->reg_pairs; 895 num_regs = pma_cmn_vals->num_regs; 896 regmap = sp->regmap_common_cdb; 897 for (i = 0; i < num_regs; i++) 898 regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val); 899 } 900 901 /* PMA TX lane registers configurations */ 902 pma_ln_vals = init_data->pma_ln_vals[phy_t1][phy_t2][ssc]; 903 if (pma_ln_vals) { 904 reg_pairs = pma_ln_vals->reg_pairs; 905 num_regs = pma_ln_vals->num_regs; 906 for (i = 0; i < num_lanes; i++) { 907 regmap = sp->regmap_lane_cdb[i + mlane]; 908 for (j = 0; j < num_regs; j++) 909 regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val); 910 } 911 } 912 913 if (phy_t1 == TYPE_QSGMII) 914 reset_deassert_bulk(sp->phys[node]->lnk_rst); 915 } 916 917 /* Take the PHY out of reset */ 918 ret = reset_control_deassert(sp->phy_rst); 919 if (ret) 920 return ret; 921 922 return 0; 923} 924 925static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp, 926 struct udevice *dev) 927{ 928 struct clk *clk; 929 int ret; 930 931 clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div"); 932 if (IS_ERR(clk)) { 933 dev_err(dev, "cmn_refclk_dig_div clock not found\n"); 934 ret = PTR_ERR(clk); 935 return ret; 936 } 937 sp->input_clks[CMN_REFCLK_DIG_DIV] = clk; 938 939 clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div"); 940 if (IS_ERR(clk)) { 941 dev_err(dev, "cmn_refclk1_dig_div clock not found\n"); 942 ret = PTR_ERR(clk); 943 return ret; 944 } 945 sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk; 946 947 clk = devm_clk_get_optional(dev, "pll0_refclk"); 948 if (IS_ERR(clk)) { 949 dev_err(dev, "pll0_refclk clock not found\n"); 950 ret = PTR_ERR(clk); 951 return ret; 952 } 953 sp->input_clks[PLL0_REFCLK] = clk; 954 955 clk = devm_clk_get_optional(dev, "pll1_refclk"); 956 if (IS_ERR(clk)) { 957 dev_err(dev, "pll1_refclk clock not found\n"); 958 ret = PTR_ERR(clk); 959 return ret; 960 } 961 sp->input_clks[PLL1_REFCLK] = clk; 962 963 return 0; 964} 965 966static int cdns_sierra_phy_clk(struct cdns_sierra_phy *sp) 967{ 968 struct udevice *dev = sp->dev; 969 struct clk *clk; 970 int ret; 971 972 clk = devm_clk_get_optional(dev, "phy_clk"); 973 if (IS_ERR(clk)) { 974 dev_err(dev, "failed to get clock phy_clk\n"); 975 return PTR_ERR(clk); 976 } 977 sp->input_clks[PHY_CLK] = clk; 978 979 ret = clk_prepare_enable(sp->input_clks[PHY_CLK]); 980 if (ret) 981 return ret; 982 983 return 0; 984} 985static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp, 986 struct udevice *dev) 987{ 988 struct reset_control *rst; 989 990 rst = devm_reset_control_get(dev, "sierra_reset"); 991 if (IS_ERR(rst)) { 992 dev_err(dev, "failed to get reset\n"); 993 return PTR_ERR(rst); 994 } 995 sp->phy_rst = rst; 996 997 return 0; 998} 999 1000static int cdns_sierra_phy_bind(struct udevice *dev) 1001{ 1002 struct driver *link_drv; 1003 ofnode child; 1004 int rc; 1005 1006 link_drv = lists_driver_lookup_name("sierra_phy_link"); 1007 if (!link_drv) { 1008 dev_err(dev, "Cannot find driver 'sierra_phy_link'\n"); 1009 return -ENOENT; 1010 } 1011 1012 ofnode_for_each_subnode(child, dev_ofnode(dev)) { 1013 if (!(ofnode_name_eq(child, "phy") || 1014 ofnode_name_eq(child, "link"))) 1015 continue; 1016 1017 rc = device_bind(dev, link_drv, "link", NULL, child, NULL); 1018 if (rc) { 1019 dev_err(dev, "cannot bind driver for link\n"); 1020 return rc; 1021 } 1022 } 1023 1024 return 0; 1025} 1026 1027static int cdns_sierra_link_probe(struct udevice *dev) 1028{ 1029 struct cdns_sierra_inst *inst = dev_get_priv(dev); 1030 struct cdns_sierra_phy *sp = dev_get_priv(dev->parent); 1031 struct reset_ctl_bulk *rst; 1032 int ret, node; 1033 1034 rst = devm_reset_bulk_get_by_node(dev, dev_ofnode(dev)); 1035 if (IS_ERR(rst)) { 1036 ret = PTR_ERR(rst); 1037 dev_err(dev, "failed to get reset\n"); 1038 return ret; 1039 } 1040 inst->lnk_rst = rst; 1041 1042 ret = cdns_sierra_get_optional(inst, dev_ofnode(dev)); 1043 if (ret) { 1044 dev_err(dev, "missing property in node\n"); 1045 return ret; 1046 } 1047 node = sp->nsubnodes; 1048 sp->phys[node] = inst; 1049 sp->nsubnodes += 1; 1050 sp->num_lanes += inst->num_lanes; 1051 1052 /* If more than one subnode, configure the PHY as multilink */ 1053 if (!sp->autoconf && !sp->already_configured && sp->nsubnodes > 1) { 1054 ret = cdns_sierra_phy_configure_multilink(sp); 1055 if (ret) 1056 return ret; 1057 } 1058 1059 return 0; 1060} 1061 1062U_BOOT_DRIVER(sierra_phy_link) = { 1063 .name = "sierra_phy_link", 1064 .id = UCLASS_PHY, 1065 .probe = cdns_sierra_link_probe, 1066 .ops = &ops, 1067 .priv_auto = sizeof(struct cdns_sierra_inst), 1068}; 1069 1070static int cdns_sierra_phy_probe(struct udevice *dev) 1071{ 1072 struct cdns_sierra_phy *sp = dev_get_priv(dev); 1073 struct cdns_sierra_data *data; 1074 unsigned int id_value; 1075 int ret; 1076 1077 sp->dev = dev; 1078 1079 sp->base = devfdt_remap_addr_index(dev, 0); 1080 if (!sp->base) { 1081 dev_err(dev, "unable to map regs\n"); 1082 return -ENOMEM; 1083 } 1084 devfdt_get_addr_size_index(dev, 0, (fdt_size_t *)&sp->size); 1085 1086 /* Get init data for this PHY */ 1087 data = (struct cdns_sierra_data *)dev_get_driver_data(dev); 1088 sp->init_data = data; 1089 1090 ret = cdns_regmap_init_blocks(sp, sp->base, data->block_offset_shift, 1091 data->reg_offset_shift); 1092 if (ret) 1093 return ret; 1094 1095 ret = cdns_regfield_init(sp); 1096 if (ret) 1097 return ret; 1098 1099 ret = cdns_sierra_phy_get_clocks(sp, dev); 1100 if (ret) 1101 return ret; 1102 1103 ret = cdns_sierra_pll_bind_of_clocks(sp); 1104 if (ret) 1105 return ret; 1106 1107 regmap_field_read(sp->pma_cmn_ready, &sp->already_configured); 1108 1109 if (!sp->already_configured) { 1110 ret = cdns_sierra_phy_clk(sp); 1111 if (ret) 1112 return ret; 1113 1114 ret = cdns_sierra_phy_get_resets(sp, dev); 1115 if (ret) 1116 return ret; 1117 } 1118 1119 /* Check that PHY is present */ 1120 regmap_field_read(sp->macro_id_type, &id_value); 1121 if (sp->init_data->id_value != id_value) { 1122 dev_err(dev, "PHY not found 0x%x vs 0x%x\n", 1123 sp->init_data->id_value, id_value); 1124 ret = -EINVAL; 1125 goto clk_disable; 1126 } 1127 1128 sp->autoconf = dev_read_bool(dev, "cdns,autoconf"); 1129 1130 dev_info(dev, "sierra probed\n"); 1131 return 0; 1132 1133clk_disable: 1134 if (!sp->already_configured) 1135 clk_disable_unprepare(sp->input_clks[PHY_CLK]); 1136 return ret; 1137} 1138 1139static int cdns_sierra_phy_remove(struct udevice *dev) 1140{ 1141 struct cdns_sierra_phy *phy = dev_get_priv(dev); 1142 int i; 1143 1144 reset_control_assert(phy->phy_rst); 1145 1146 /* 1147 * The device level resets will be put automatically. 1148 * Need to put the subnode resets here though. 1149 */ 1150 for (i = 0; i < phy->nsubnodes; i++) 1151 reset_assert_bulk(phy->phys[i]->lnk_rst); 1152 1153 clk_disable_unprepare(phy->input_clks[PHY_CLK]); 1154 1155 return 0; 1156} 1157 1158/* QSGMII PHY PMA lane configuration */ 1159static struct cdns_reg_pairs qsgmii_phy_pma_ln_regs[] = { 1160 {0x9010, SIERRA_PHY_PMA_XCVR_CTRL} 1161}; 1162 1163static struct cdns_sierra_vals qsgmii_phy_pma_ln_vals = { 1164 .reg_pairs = qsgmii_phy_pma_ln_regs, 1165 .num_regs = ARRAY_SIZE(qsgmii_phy_pma_ln_regs), 1166}; 1167 1168/* QSGMII refclk 100MHz, 20b, opt1, No BW cal, no ssc, PLL LC1 */ 1169static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_cmn_regs[] = { 1170 {0x2085, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG}, 1171 {0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG}, 1172 {0x0000, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG} 1173}; 1174 1175static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_ln_regs[] = { 1176 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 1177 {0x0252, SIERRA_DET_STANDEC_E_PREG}, 1178 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 1179 {0x0FFE, SIERRA_PSC_RX_A0_PREG}, 1180 {0x0011, SIERRA_PLLCTRL_SUBRATE_PREG}, 1181 {0x0001, SIERRA_PLLCTRL_GEN_A_PREG}, 1182 {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG}, 1183 {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, 1184 {0x0089, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1185 {0x3C3C, SIERRA_CREQ_CCLKDET_MODE01_PREG}, 1186 {0x3222, SIERRA_CREQ_FSMCLK_SEL_PREG}, 1187 {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, 1188 {0x8422, SIERRA_CTLELUT_CTRL_PREG}, 1189 {0x4111, SIERRA_DFE_ECMP_RATESEL_PREG}, 1190 {0x4111, SIERRA_DFE_SMP_RATESEL_PREG}, 1191 {0x0002, SIERRA_DEQ_PHALIGN_CTRL}, 1192 {0x9595, SIERRA_DEQ_VGATUNE_CTRL_PREG}, 1193 {0x0186, SIERRA_DEQ_GLUT0}, 1194 {0x0186, SIERRA_DEQ_GLUT1}, 1195 {0x0186, SIERRA_DEQ_GLUT2}, 1196 {0x0186, SIERRA_DEQ_GLUT3}, 1197 {0x0186, SIERRA_DEQ_GLUT4}, 1198 {0x0861, SIERRA_DEQ_ALUT0}, 1199 {0x07E0, SIERRA_DEQ_ALUT1}, 1200 {0x079E, SIERRA_DEQ_ALUT2}, 1201 {0x071D, SIERRA_DEQ_ALUT3}, 1202 {0x03F5, SIERRA_DEQ_DFETAP_CTRL_PREG}, 1203 {0x0C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG}, 1204 {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1205 {0x1C04, SIERRA_DEQ_TAU_CTRL2_PREG}, 1206 {0x0033, SIERRA_DEQ_PICTRL_PREG}, 1207 {0x0660, SIERRA_CPICAL_TMRVAL_MODE0_PREG}, 1208 {0x00D5, SIERRA_CPI_OUTBUF_RATESEL_PREG}, 1209 {0x0B6D, SIERRA_CPI_RESBIAS_BIN_PREG}, 1210 {0x0102, SIERRA_RXBUFFER_CTLECTRL_PREG}, 1211 {0x0002, SIERRA_RXBUFFER_RCDFECTRL_PREG} 1212}; 1213 1214static struct cdns_sierra_vals qsgmii_100_no_ssc_plllc1_cmn_vals = { 1215 .reg_pairs = qsgmii_100_no_ssc_plllc1_cmn_regs, 1216 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_plllc1_cmn_regs), 1217}; 1218 1219static struct cdns_sierra_vals qsgmii_100_no_ssc_plllc1_ln_vals = { 1220 .reg_pairs = qsgmii_100_no_ssc_plllc1_ln_regs, 1221 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_plllc1_ln_regs), 1222}; 1223 1224/* PCIE PHY PCS common configuration */ 1225static struct cdns_reg_pairs pcie_phy_pcs_cmn_regs[] = { 1226 {0x0430, SIERRA_PHY_PIPE_CMN_CTRL1} 1227}; 1228 1229static struct cdns_sierra_vals pcie_phy_pcs_cmn_vals = { 1230 .reg_pairs = pcie_phy_pcs_cmn_regs, 1231 .num_regs = ARRAY_SIZE(pcie_phy_pcs_cmn_regs), 1232}; 1233 1234/* refclk100MHz_32b_PCIe_cmn_pll_no_ssc, pcie_links_using_plllc, pipe_bw_3 */ 1235static const struct cdns_reg_pairs pcie_100_no_ssc_plllc_cmn_regs[] = { 1236 {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 1237 {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 1238 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 1239 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG} 1240}; 1241 1242/* 1243 * refclk100MHz_32b_PCIe_ln_no_ssc, multilink, using_plllc, 1244 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz 1245 */ 1246static const struct cdns_reg_pairs ml_pcie_100_no_ssc_ln_regs[] = { 1247 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 1248 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 1249 {0x0004, SIERRA_PSC_LN_A3_PREG}, 1250 {0x0004, SIERRA_PSC_LN_A4_PREG}, 1251 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 1252 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 1253 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 1254 {0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 1255 {0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 1256 {0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 1257 {0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1258 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 1259 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 1260 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 1261 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 1262 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 1263 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 1264 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 1265 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 1266 {0x0041, SIERRA_DEQ_GLUT0}, 1267 {0x0082, SIERRA_DEQ_GLUT1}, 1268 {0x00C3, SIERRA_DEQ_GLUT2}, 1269 {0x0145, SIERRA_DEQ_GLUT3}, 1270 {0x0186, SIERRA_DEQ_GLUT4}, 1271 {0x09E7, SIERRA_DEQ_ALUT0}, 1272 {0x09A6, SIERRA_DEQ_ALUT1}, 1273 {0x0965, SIERRA_DEQ_ALUT2}, 1274 {0x08E3, SIERRA_DEQ_ALUT3}, 1275 {0x00FA, SIERRA_DEQ_DFETAP0}, 1276 {0x00FA, SIERRA_DEQ_DFETAP1}, 1277 {0x00FA, SIERRA_DEQ_DFETAP2}, 1278 {0x00FA, SIERRA_DEQ_DFETAP3}, 1279 {0x00FA, SIERRA_DEQ_DFETAP4}, 1280 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 1281 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 1282 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 1283 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1284 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 1285 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 1286 {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, 1287 {0x002B, SIERRA_CPI_TRIM_PREG}, 1288 {0x0003, SIERRA_EPI_CTRL_PREG}, 1289 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 1290 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 1291 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 1292 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} 1293}; 1294 1295static struct cdns_sierra_vals pcie_100_no_ssc_plllc_cmn_vals = { 1296 .reg_pairs = pcie_100_no_ssc_plllc_cmn_regs, 1297 .num_regs = ARRAY_SIZE(pcie_100_no_ssc_plllc_cmn_regs), 1298}; 1299 1300static struct cdns_sierra_vals ml_pcie_100_no_ssc_ln_vals = { 1301 .reg_pairs = ml_pcie_100_no_ssc_ln_regs, 1302 .num_regs = ARRAY_SIZE(ml_pcie_100_no_ssc_ln_regs), 1303}; 1304 1305/* refclk100MHz_32b_PCIe_cmn_pll_int_ssc, pcie_links_using_plllc, pipe_bw_3 */ 1306static const struct cdns_reg_pairs pcie_100_int_ssc_plllc_cmn_regs[] = { 1307 {0x000E, SIERRA_CMN_PLLLC_MODE_PREG}, 1308 {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 1309 {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 1310 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 1311 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 1312 {0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG}, 1313 {0x7F80, SIERRA_CMN_PLLLC_SS_PREG}, 1314 {0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG}, 1315 {0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG}, 1316 {0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}, 1317 {0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG} 1318}; 1319 1320/* 1321 * refclk100MHz_32b_PCIe_ln_int_ssc, multilink, using_plllc, 1322 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz 1323 */ 1324static const struct cdns_reg_pairs ml_pcie_100_int_ssc_ln_regs[] = { 1325 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 1326 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 1327 {0x0004, SIERRA_PSC_LN_A3_PREG}, 1328 {0x0004, SIERRA_PSC_LN_A4_PREG}, 1329 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 1330 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 1331 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 1332 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, 1333 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 1334 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 1335 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 1336 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1337 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 1338 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 1339 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 1340 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 1341 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 1342 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 1343 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 1344 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 1345 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 1346 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 1347 {0x0041, SIERRA_DEQ_GLUT0}, 1348 {0x0082, SIERRA_DEQ_GLUT1}, 1349 {0x00C3, SIERRA_DEQ_GLUT2}, 1350 {0x0145, SIERRA_DEQ_GLUT3}, 1351 {0x0186, SIERRA_DEQ_GLUT4}, 1352 {0x09E7, SIERRA_DEQ_ALUT0}, 1353 {0x09A6, SIERRA_DEQ_ALUT1}, 1354 {0x0965, SIERRA_DEQ_ALUT2}, 1355 {0x08E3, SIERRA_DEQ_ALUT3}, 1356 {0x00FA, SIERRA_DEQ_DFETAP0}, 1357 {0x00FA, SIERRA_DEQ_DFETAP1}, 1358 {0x00FA, SIERRA_DEQ_DFETAP2}, 1359 {0x00FA, SIERRA_DEQ_DFETAP3}, 1360 {0x00FA, SIERRA_DEQ_DFETAP4}, 1361 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 1362 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 1363 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 1364 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1365 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 1366 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 1367 {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, 1368 {0x002B, SIERRA_CPI_TRIM_PREG}, 1369 {0x0003, SIERRA_EPI_CTRL_PREG}, 1370 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 1371 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 1372 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 1373 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} 1374}; 1375 1376static struct cdns_sierra_vals pcie_100_int_ssc_plllc_cmn_vals = { 1377 .reg_pairs = pcie_100_int_ssc_plllc_cmn_regs, 1378 .num_regs = ARRAY_SIZE(pcie_100_int_ssc_plllc_cmn_regs), 1379}; 1380 1381static struct cdns_sierra_vals ml_pcie_100_int_ssc_ln_vals = { 1382 .reg_pairs = ml_pcie_100_int_ssc_ln_regs, 1383 .num_regs = ARRAY_SIZE(ml_pcie_100_int_ssc_ln_regs), 1384}; 1385 1386/* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc, pcie_links_using_plllc, pipe_bw_3 */ 1387static const struct cdns_reg_pairs pcie_100_ext_ssc_plllc_cmn_regs[] = { 1388 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 1389 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 1390 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 1391 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 1392 {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} 1393}; 1394 1395/* 1396 * refclk100MHz_32b_PCIe_ln_ext_ssc, multilink, using_plllc, 1397 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz 1398 */ 1399static const struct cdns_reg_pairs ml_pcie_100_ext_ssc_ln_regs[] = { 1400 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 1401 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 1402 {0x0004, SIERRA_PSC_LN_A3_PREG}, 1403 {0x0004, SIERRA_PSC_LN_A4_PREG}, 1404 {0x0004, SIERRA_PSC_LN_IDLE_PREG}, 1405 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 1406 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 1407 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, 1408 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 1409 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 1410 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 1411 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1412 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 1413 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 1414 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 1415 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 1416 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 1417 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 1418 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 1419 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 1420 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 1421 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 1422 {0x0041, SIERRA_DEQ_GLUT0}, 1423 {0x0082, SIERRA_DEQ_GLUT1}, 1424 {0x00C3, SIERRA_DEQ_GLUT2}, 1425 {0x0145, SIERRA_DEQ_GLUT3}, 1426 {0x0186, SIERRA_DEQ_GLUT4}, 1427 {0x09E7, SIERRA_DEQ_ALUT0}, 1428 {0x09A6, SIERRA_DEQ_ALUT1}, 1429 {0x0965, SIERRA_DEQ_ALUT2}, 1430 {0x08E3, SIERRA_DEQ_ALUT3}, 1431 {0x00FA, SIERRA_DEQ_DFETAP0}, 1432 {0x00FA, SIERRA_DEQ_DFETAP1}, 1433 {0x00FA, SIERRA_DEQ_DFETAP2}, 1434 {0x00FA, SIERRA_DEQ_DFETAP3}, 1435 {0x00FA, SIERRA_DEQ_DFETAP4}, 1436 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 1437 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 1438 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 1439 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1440 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 1441 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 1442 {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, 1443 {0x002B, SIERRA_CPI_TRIM_PREG}, 1444 {0x0003, SIERRA_EPI_CTRL_PREG}, 1445 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 1446 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 1447 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 1448 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} 1449}; 1450 1451static struct cdns_sierra_vals pcie_100_ext_ssc_plllc_cmn_vals = { 1452 .reg_pairs = pcie_100_ext_ssc_plllc_cmn_regs, 1453 .num_regs = ARRAY_SIZE(pcie_100_ext_ssc_plllc_cmn_regs), 1454}; 1455 1456static struct cdns_sierra_vals ml_pcie_100_ext_ssc_ln_vals = { 1457 .reg_pairs = ml_pcie_100_ext_ssc_ln_regs, 1458 .num_regs = ARRAY_SIZE(ml_pcie_100_ext_ssc_ln_regs), 1459}; 1460 1461/* refclk100MHz_32b_PCIe_cmn_pll_no_ssc */ 1462static const struct cdns_reg_pairs cdns_pcie_cmn_regs_no_ssc[] = { 1463 {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 1464 {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 1465 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 1466 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG} 1467}; 1468 1469/* refclk100MHz_32b_PCIe_ln_no_ssc */ 1470static const struct cdns_reg_pairs cdns_pcie_ln_regs_no_ssc[] = { 1471 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 1472 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 1473 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 1474 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 1475 {0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 1476 {0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 1477 {0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 1478 {0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1479 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 1480 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 1481 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 1482 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 1483 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 1484 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 1485 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 1486 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 1487 {0x0041, SIERRA_DEQ_GLUT0}, 1488 {0x0082, SIERRA_DEQ_GLUT1}, 1489 {0x00C3, SIERRA_DEQ_GLUT2}, 1490 {0x0145, SIERRA_DEQ_GLUT3}, 1491 {0x0186, SIERRA_DEQ_GLUT4}, 1492 {0x09E7, SIERRA_DEQ_ALUT0}, 1493 {0x09A6, SIERRA_DEQ_ALUT1}, 1494 {0x0965, SIERRA_DEQ_ALUT2}, 1495 {0x08E3, SIERRA_DEQ_ALUT3}, 1496 {0x00FA, SIERRA_DEQ_DFETAP0}, 1497 {0x00FA, SIERRA_DEQ_DFETAP1}, 1498 {0x00FA, SIERRA_DEQ_DFETAP2}, 1499 {0x00FA, SIERRA_DEQ_DFETAP3}, 1500 {0x00FA, SIERRA_DEQ_DFETAP4}, 1501 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 1502 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 1503 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 1504 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1505 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 1506 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 1507 {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, 1508 {0x002B, SIERRA_CPI_TRIM_PREG}, 1509 {0x0003, SIERRA_EPI_CTRL_PREG}, 1510 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 1511 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 1512 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 1513 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} 1514}; 1515 1516static struct cdns_sierra_vals pcie_100_no_ssc_cmn_vals = { 1517 .reg_pairs = cdns_pcie_cmn_regs_no_ssc, 1518 .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_no_ssc), 1519}; 1520 1521static struct cdns_sierra_vals pcie_100_no_ssc_ln_vals = { 1522 .reg_pairs = cdns_pcie_ln_regs_no_ssc, 1523 .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_no_ssc), 1524}; 1525 1526/* refclk100MHz_32b_PCIe_cmn_pll_int_ssc */ 1527static const struct cdns_reg_pairs cdns_pcie_cmn_regs_int_ssc[] = { 1528 {0x000E, SIERRA_CMN_PLLLC_MODE_PREG}, 1529 {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 1530 {0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 1531 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 1532 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 1533 {0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG}, 1534 {0x7F80, SIERRA_CMN_PLLLC_SS_PREG}, 1535 {0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG}, 1536 {0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG}, 1537 {0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}, 1538 {0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG} 1539}; 1540 1541/* refclk100MHz_32b_PCIe_ln_int_ssc */ 1542static const struct cdns_reg_pairs cdns_pcie_ln_regs_int_ssc[] = { 1543 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 1544 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 1545 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 1546 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 1547 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, 1548 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 1549 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 1550 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 1551 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1552 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 1553 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 1554 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 1555 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 1556 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 1557 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 1558 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 1559 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 1560 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 1561 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 1562 {0x0041, SIERRA_DEQ_GLUT0}, 1563 {0x0082, SIERRA_DEQ_GLUT1}, 1564 {0x00C3, SIERRA_DEQ_GLUT2}, 1565 {0x0145, SIERRA_DEQ_GLUT3}, 1566 {0x0186, SIERRA_DEQ_GLUT4}, 1567 {0x09E7, SIERRA_DEQ_ALUT0}, 1568 {0x09A6, SIERRA_DEQ_ALUT1}, 1569 {0x0965, SIERRA_DEQ_ALUT2}, 1570 {0x08E3, SIERRA_DEQ_ALUT3}, 1571 {0x00FA, SIERRA_DEQ_DFETAP0}, 1572 {0x00FA, SIERRA_DEQ_DFETAP1}, 1573 {0x00FA, SIERRA_DEQ_DFETAP2}, 1574 {0x00FA, SIERRA_DEQ_DFETAP3}, 1575 {0x00FA, SIERRA_DEQ_DFETAP4}, 1576 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 1577 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 1578 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 1579 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1580 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 1581 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 1582 {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, 1583 {0x002B, SIERRA_CPI_TRIM_PREG}, 1584 {0x0003, SIERRA_EPI_CTRL_PREG}, 1585 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 1586 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 1587 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 1588 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} 1589}; 1590 1591static struct cdns_sierra_vals pcie_100_int_ssc_cmn_vals = { 1592 .reg_pairs = cdns_pcie_cmn_regs_int_ssc, 1593 .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_int_ssc), 1594}; 1595 1596static struct cdns_sierra_vals pcie_100_int_ssc_ln_vals = { 1597 .reg_pairs = cdns_pcie_ln_regs_int_ssc, 1598 .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_int_ssc), 1599}; 1600 1601/* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */ 1602static struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = { 1603 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 1604 {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 1605 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, 1606 {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 1607 {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} 1608}; 1609 1610/* refclk100MHz_32b_PCIe_ln_ext_ssc */ 1611static struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = { 1612 {0xFC08, SIERRA_DET_STANDEC_A_PREG}, 1613 {0x001D, SIERRA_PSM_A3IN_TMR_PREG}, 1614 {0x1555, SIERRA_DFE_BIASTRIM_PREG}, 1615 {0x9703, SIERRA_DRVCTRL_BOOST_PREG}, 1616 {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, 1617 {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, 1618 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, 1619 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 1620 {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1621 {0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG}, 1622 {0x9800, SIERRA_RX_CTLE_CAL_PREG}, 1623 {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 1624 {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 1625 {0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 1626 {0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 1627 {0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 1628 {0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 1629 {0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG}, 1630 {0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG}, 1631 {0x0041, SIERRA_DEQ_GLUT0}, 1632 {0x0082, SIERRA_DEQ_GLUT1}, 1633 {0x00C3, SIERRA_DEQ_GLUT2}, 1634 {0x0145, SIERRA_DEQ_GLUT3}, 1635 {0x0186, SIERRA_DEQ_GLUT4}, 1636 {0x09E7, SIERRA_DEQ_ALUT0}, 1637 {0x09A6, SIERRA_DEQ_ALUT1}, 1638 {0x0965, SIERRA_DEQ_ALUT2}, 1639 {0x08E3, SIERRA_DEQ_ALUT3}, 1640 {0x00FA, SIERRA_DEQ_DFETAP0}, 1641 {0x00FA, SIERRA_DEQ_DFETAP1}, 1642 {0x00FA, SIERRA_DEQ_DFETAP2}, 1643 {0x00FA, SIERRA_DEQ_DFETAP3}, 1644 {0x00FA, SIERRA_DEQ_DFETAP4}, 1645 {0x000F, SIERRA_DEQ_PRECUR_PREG}, 1646 {0x0280, SIERRA_DEQ_POSTCUR_PREG}, 1647 {0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG}, 1648 {0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1649 {0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG}, 1650 {0x0100, SIERRA_DEQ_TAU_CTRL3_PREG}, 1651 {0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG}, 1652 {0x002B, SIERRA_CPI_TRIM_PREG}, 1653 {0x0003, SIERRA_EPI_CTRL_PREG}, 1654 {0x803F, SIERRA_SDFILT_H2L_A_PREG}, 1655 {0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG}, 1656 {0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 1657 {0x4432, SIERRA_RXBUFFER_DFECTRL_PREG} 1658}; 1659 1660static struct cdns_sierra_vals pcie_100_ext_ssc_cmn_vals = { 1661 .reg_pairs = cdns_pcie_cmn_regs_ext_ssc, 1662 .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc), 1663}; 1664 1665static struct cdns_sierra_vals pcie_100_ext_ssc_ln_vals = { 1666 .reg_pairs = cdns_pcie_ln_regs_ext_ssc, 1667 .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc), 1668}; 1669 1670/* refclk100MHz_20b_USB_cmn_pll_ext_ssc */ 1671static struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = { 1672 {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, 1673 {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, 1674 {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, 1675 {0x0000, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG} 1676}; 1677 1678/* refclk100MHz_20b_USB_ln_ext_ssc */ 1679static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = { 1680 {0xFE0A, SIERRA_DET_STANDEC_A_PREG}, 1681 {0x000F, SIERRA_DET_STANDEC_B_PREG}, 1682 {0x55A5, SIERRA_DET_STANDEC_C_PREG}, 1683 {0x69ad, SIERRA_DET_STANDEC_D_PREG}, 1684 {0x0241, SIERRA_DET_STANDEC_E_PREG}, 1685 {0x0110, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG}, 1686 {0x0014, SIERRA_PSM_A0IN_TMR_PREG}, 1687 {0xCF00, SIERRA_PSM_DIAG_PREG}, 1688 {0x001F, SIERRA_PSC_TX_A0_PREG}, 1689 {0x0007, SIERRA_PSC_TX_A1_PREG}, 1690 {0x0003, SIERRA_PSC_TX_A2_PREG}, 1691 {0x0003, SIERRA_PSC_TX_A3_PREG}, 1692 {0x0FFF, SIERRA_PSC_RX_A0_PREG}, 1693 {0x0003, SIERRA_PSC_RX_A1_PREG}, 1694 {0x0003, SIERRA_PSC_RX_A2_PREG}, 1695 {0x0001, SIERRA_PSC_RX_A3_PREG}, 1696 {0x0001, SIERRA_PLLCTRL_SUBRATE_PREG}, 1697 {0x0406, SIERRA_PLLCTRL_GEN_D_PREG}, 1698 {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG}, 1699 {0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG}, 1700 {0x2512, SIERRA_DFE_BIASTRIM_PREG}, 1701 {0x0000, SIERRA_DRVCTRL_ATTEN_PREG}, 1702 {0x823E, SIERRA_CLKPATHCTRL_TMR_PREG}, 1703 {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG}, 1704 {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG}, 1705 {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG}, 1706 {0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG}, 1707 {0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG}, 1708 {0x0000, SIERRA_CREQ_EQ_CTRL_PREG}, 1709 {0x0000, SIERRA_CREQ_SPARE_PREG}, 1710 {0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}, 1711 {0x8452, SIERRA_CTLELUT_CTRL_PREG}, 1712 {0x4121, SIERRA_DFE_ECMP_RATESEL_PREG}, 1713 {0x4121, SIERRA_DFE_SMP_RATESEL_PREG}, 1714 {0x0003, SIERRA_DEQ_PHALIGN_CTRL}, 1715 {0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG}, 1716 {0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG}, 1717 {0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG}, 1718 {0x0048, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG}, 1719 {0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG}, 1720 {0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG}, 1721 {0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG}, 1722 {0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG}, 1723 {0x0014, SIERRA_DEQ_GLUT0}, 1724 {0x0014, SIERRA_DEQ_GLUT1}, 1725 {0x0014, SIERRA_DEQ_GLUT2}, 1726 {0x0014, SIERRA_DEQ_GLUT3}, 1727 {0x0014, SIERRA_DEQ_GLUT4}, 1728 {0x0014, SIERRA_DEQ_GLUT5}, 1729 {0x0014, SIERRA_DEQ_GLUT6}, 1730 {0x0014, SIERRA_DEQ_GLUT7}, 1731 {0x0014, SIERRA_DEQ_GLUT8}, 1732 {0x0014, SIERRA_DEQ_GLUT9}, 1733 {0x0014, SIERRA_DEQ_GLUT10}, 1734 {0x0014, SIERRA_DEQ_GLUT11}, 1735 {0x0014, SIERRA_DEQ_GLUT12}, 1736 {0x0014, SIERRA_DEQ_GLUT13}, 1737 {0x0014, SIERRA_DEQ_GLUT14}, 1738 {0x0014, SIERRA_DEQ_GLUT15}, 1739 {0x0014, SIERRA_DEQ_GLUT16}, 1740 {0x0BAE, SIERRA_DEQ_ALUT0}, 1741 {0x0AEB, SIERRA_DEQ_ALUT1}, 1742 {0x0A28, SIERRA_DEQ_ALUT2}, 1743 {0x0965, SIERRA_DEQ_ALUT3}, 1744 {0x08A2, SIERRA_DEQ_ALUT4}, 1745 {0x07DF, SIERRA_DEQ_ALUT5}, 1746 {0x071C, SIERRA_DEQ_ALUT6}, 1747 {0x0659, SIERRA_DEQ_ALUT7}, 1748 {0x0596, SIERRA_DEQ_ALUT8}, 1749 {0x0514, SIERRA_DEQ_ALUT9}, 1750 {0x0492, SIERRA_DEQ_ALUT10}, 1751 {0x0410, SIERRA_DEQ_ALUT11}, 1752 {0x038E, SIERRA_DEQ_ALUT12}, 1753 {0x030C, SIERRA_DEQ_ALUT13}, 1754 {0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG}, 1755 {0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG}, 1756 {0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG}, 1757 {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG}, 1758 {0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG}, 1759 {0x0033, SIERRA_DEQ_PICTRL_PREG}, 1760 {0x0400, SIERRA_CPICAL_TMRVAL_MODE1_PREG}, 1761 {0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG}, 1762 {0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG}, 1763 {0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG}, 1764 {0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG}, 1765 {0x0005, SIERRA_LFPSDET_SUPPORT_PREG}, 1766 {0x000F, SIERRA_LFPSFILT_NS_PREG}, 1767 {0x0009, SIERRA_LFPSFILT_RD_PREG}, 1768 {0x0001, SIERRA_LFPSFILT_MP_PREG}, 1769 {0x6013, SIERRA_SIGDET_SUPPORT_PREG}, 1770 {0x8013, SIERRA_SDFILT_H2L_A_PREG}, 1771 {0x8009, SIERRA_SDFILT_L2H_PREG}, 1772 {0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG}, 1773 {0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG}, 1774 {0x4243, SIERRA_RXBUFFER_DFECTRL_PREG} 1775}; 1776 1777static struct cdns_sierra_vals usb_100_ext_ssc_cmn_vals = { 1778 .reg_pairs = cdns_usb_cmn_regs_ext_ssc, 1779 .num_regs = ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc), 1780}; 1781 1782static struct cdns_sierra_vals usb_100_ext_ssc_ln_vals = { 1783 .reg_pairs = cdns_usb_ln_regs_ext_ssc, 1784 .num_regs = ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc), 1785}; 1786 1787static const struct cdns_sierra_data cdns_map_sierra = { 1788 .id_value = SIERRA_MACRO_ID, 1789 .block_offset_shift = 0x2, 1790 .reg_offset_shift = 0x2, 1791 .pcs_cmn_vals = { 1792 [TYPE_PCIE] = { 1793 [TYPE_NONE] = { 1794 [NO_SSC] = &pcie_phy_pcs_cmn_vals, 1795 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 1796 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 1797 }, 1798 [TYPE_QSGMII] = { 1799 [NO_SSC] = &pcie_phy_pcs_cmn_vals, 1800 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 1801 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 1802 }, 1803 }, 1804 }, 1805 .pma_cmn_vals = { 1806 [TYPE_PCIE] = { 1807 [TYPE_NONE] = { 1808 [NO_SSC] = &pcie_100_no_ssc_cmn_vals, 1809 [EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals, 1810 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals 1811 }, 1812 [TYPE_QSGMII] = { 1813 [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals, 1814 [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals, 1815 [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals, 1816 }, 1817 }, 1818 [TYPE_USB] = { 1819 [TYPE_NONE] = { 1820 [EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals, 1821 }, 1822 }, 1823 [TYPE_QSGMII] = { 1824 [TYPE_PCIE] = { 1825 [NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, 1826 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, 1827 [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, 1828 }, 1829 }, 1830 }, 1831 .pma_ln_vals = { 1832 [TYPE_PCIE] = { 1833 [TYPE_NONE] = { 1834 [NO_SSC] = &pcie_100_no_ssc_ln_vals, 1835 [EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals, 1836 [INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals, 1837 }, 1838 [TYPE_QSGMII] = { 1839 [NO_SSC] = &ml_pcie_100_no_ssc_ln_vals, 1840 [EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals, 1841 [INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals, 1842 }, 1843 }, 1844 [TYPE_USB] = { 1845 [TYPE_NONE] = { 1846 [EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals, 1847 }, 1848 }, 1849 [TYPE_QSGMII] = { 1850 [TYPE_PCIE] = { 1851 [NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, 1852 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, 1853 [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, 1854 }, 1855 }, 1856 1857 }, 1858}; 1859 1860static const struct cdns_sierra_data cdns_ti_map_sierra = { 1861 .id_value = SIERRA_MACRO_ID, 1862 .block_offset_shift = 0x0, 1863 .reg_offset_shift = 0x1, 1864 .pcs_cmn_vals = { 1865 [TYPE_PCIE] = { 1866 [TYPE_NONE] = { 1867 [NO_SSC] = &pcie_phy_pcs_cmn_vals, 1868 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 1869 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 1870 }, 1871 [TYPE_QSGMII] = { 1872 [NO_SSC] = &pcie_phy_pcs_cmn_vals, 1873 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 1874 [INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals, 1875 }, 1876 }, 1877 }, 1878 .phy_pma_ln_vals = { 1879 [TYPE_QSGMII] = { 1880 [TYPE_PCIE] = { 1881 [NO_SSC] = &qsgmii_phy_pma_ln_vals, 1882 [EXTERNAL_SSC] = &qsgmii_phy_pma_ln_vals, 1883 [INTERNAL_SSC] = &qsgmii_phy_pma_ln_vals, 1884 }, 1885 }, 1886 }, 1887 .pma_cmn_vals = { 1888 [TYPE_PCIE] = { 1889 [TYPE_NONE] = { 1890 [NO_SSC] = &pcie_100_no_ssc_cmn_vals, 1891 [EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals, 1892 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals, 1893 }, 1894 [TYPE_QSGMII] = { 1895 [NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals, 1896 [EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals, 1897 [INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals, 1898 }, 1899 }, 1900 [TYPE_USB] = { 1901 [TYPE_NONE] = { 1902 [EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals, 1903 }, 1904 }, 1905 [TYPE_QSGMII] = { 1906 [TYPE_PCIE] = { 1907 [NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, 1908 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, 1909 [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals, 1910 }, 1911 }, 1912 }, 1913 .pma_ln_vals = { 1914 [TYPE_PCIE] = { 1915 [TYPE_NONE] = { 1916 [NO_SSC] = &pcie_100_no_ssc_ln_vals, 1917 [EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals, 1918 [INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals, 1919 }, 1920 [TYPE_QSGMII] = { 1921 [NO_SSC] = &ml_pcie_100_no_ssc_ln_vals, 1922 [EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals, 1923 [INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals, 1924 }, 1925 }, 1926 [TYPE_USB] = { 1927 [TYPE_NONE] = { 1928 [EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals, 1929 }, 1930 }, 1931 [TYPE_QSGMII] = { 1932 [TYPE_PCIE] = { 1933 [NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, 1934 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, 1935 [INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals, 1936 }, 1937 }, 1938 }, 1939}; 1940 1941static const struct udevice_id cdns_sierra_id_table[] = { 1942 { 1943 .compatible = "cdns,sierra-phy-t0", 1944 .data = (ulong)&cdns_map_sierra, 1945 }, 1946 { 1947 .compatible = "ti,sierra-phy-t0", 1948 .data = (ulong)&cdns_ti_map_sierra, 1949 }, 1950 {} 1951}; 1952 1953U_BOOT_DRIVER(sierra_phy_provider) = { 1954 .name = "cdns,sierra", 1955 .id = UCLASS_MISC, 1956 .of_match = cdns_sierra_id_table, 1957 .probe = cdns_sierra_phy_probe, 1958 .remove = cdns_sierra_phy_remove, 1959 .bind = cdns_sierra_phy_bind, 1960 .priv_auto = sizeof(struct cdns_sierra_phy), 1961}; 1962