1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright (C) 2018 Marvell International Ltd. 4 */ 5 6#ifndef __CGX_INTF_H__ 7#define __CGX_INTF_H__ 8 9#define CGX_FIRMWARE_MAJOR_VER 1 10#define CGX_FIRMWARE_MINOR_VER 0 11 12/* Register offsets */ 13#define CGX_CMR_INT 0x87e0e0000040 14#define CGX_CMR_SCRATCH0 0x87e0e0001050 15#define CGX_CMR_SCRATCH1 0x87e0e0001058 16 17#define CGX_SHIFT(x) (0x1000000 * ((x) & 0x3)) 18#define CMR_SHIFT(x) (0x40000 * ((x) & 0x3)) 19 20/* CGX error types. set for cmd response status as CGX_STAT_FAIL */ 21enum cgx_error_type { 22 CGX_ERR_NONE, 23 CGX_ERR_LMAC_NOT_ENABLED, 24 CGX_ERR_LMAC_MODE_INVALID, 25 CGX_ERR_REQUEST_ID_INVALID, 26 CGX_ERR_PREV_ACK_NOT_CLEAR, 27 CGX_ERR_PHY_LINK_DOWN, 28 CGX_ERR_PCS_RESET_FAIL, 29 CGX_ERR_AN_CPT_FAIL, 30 CGX_ERR_TX_NOT_IDLE, 31 CGX_ERR_RX_NOT_IDLE, 32 CGX_ERR_SPUX_BR_BLKLOCK_FAIL, 33 CGX_ERR_SPUX_RX_ALIGN_FAIL, 34 CGX_ERR_SPUX_TX_FAULT, 35 CGX_ERR_SPUX_RX_FAULT, 36 CGX_ERR_SPUX_RESET_FAIL, 37 CGX_ERR_SPUX_AN_RESET_FAIL, 38 CGX_ERR_SPUX_USX_AN_RESET_FAIL, 39 CGX_ERR_SMUX_RX_LINK_NOT_OK, 40 CGX_ERR_PCS_LINK_FAIL, 41 CGX_ERR_TRAINING_FAIL, 42 CGX_ERR_RX_EQU_FAIL, 43 CGX_ERR_SPUX_BER_FAIL, 44 CGX_ERR_SPUX_RSFEC_ALGN_FAIL, 45 CGX_ERR_SPUX_MARKER_LOCK_FAIL, 46 CGX_ERR_SET_FEC_INVALID, 47 CGX_ERR_SET_FEC_FAIL, 48 CGX_ERR_MODULE_INVALID, 49 CGX_ERR_MODULE_NOT_PRESENT, 50 CGX_ERR_SPEED_CHANGE_INVALID, /* = 28 */ 51 /* FIXME : add more error types when adding support for new modes */ 52}; 53 54/* LINK speed types */ 55enum cgx_link_speed { 56 CGX_LINK_NONE, 57 CGX_LINK_10M, 58 CGX_LINK_100M, 59 CGX_LINK_1G, 60 CGX_LINK_2HG, /* 2.5 Gbps */ 61 CGX_LINK_5G, 62 CGX_LINK_10G, 63 CGX_LINK_20G, 64 CGX_LINK_25G, 65 CGX_LINK_40G, 66 CGX_LINK_50G, 67 CGX_LINK_80G, 68 CGX_LINK_100G, 69 CGX_LINK_MAX, 70}; 71 72/* REQUEST ID types. Input to firmware */ 73enum cgx_cmd_id { 74 CGX_CMD_NONE = 0, 75 CGX_CMD_GET_FW_VER, 76 CGX_CMD_GET_MAC_ADDR, 77 CGX_CMD_SET_MTU, 78 CGX_CMD_GET_LINK_STS, /* optional to user */ 79 CGX_CMD_LINK_BRING_UP, /* = 5 */ 80 CGX_CMD_LINK_BRING_DOWN, 81 CGX_CMD_INTERNAL_LBK, 82 CGX_CMD_EXTERNAL_LBK, 83 CGX_CMD_HIGIG, 84 CGX_CMD_LINK_STAT_CHANGE, /* = 10 */ 85 CGX_CMD_MODE_CHANGE, /* hot plug support */ 86 CGX_CMD_INTF_SHUTDOWN, 87 CGX_CMD_GET_MKEX_SIZE, 88 CGX_CMD_GET_MKEX_PROFILE, 89 CGX_CMD_GET_FWD_BASE, /* get base address of shared FW data */ 90 CGX_CMD_GET_LINK_MODES, /* Supported Link Modes */ 91 CGX_CMD_SET_LINK_MODE, 92 CGX_CMD_GET_SUPPORTED_FEC, 93 CGX_CMD_SET_FEC, 94 CGX_CMD_GET_AN, /* = 20 */ 95 CGX_CMD_SET_AN, 96 CGX_CMD_GET_ADV_LINK_MODES, 97 CGX_CMD_GET_ADV_FEC, 98 CGX_CMD_GET_PHY_MOD_TYPE, /* line-side modulation type: NRZ or PAM4 */ 99 CGX_CMD_SET_PHY_MOD_TYPE, /* = 25 */ 100 CGX_CMD_PRBS, 101 CGX_CMD_DISPLAY_EYE, 102 CGX_CMD_GET_PHY_FEC_STATS, 103 CGX_CMD_DISPLAY_SERDES, 104 CGX_CMD_AN_LOOPBACK, /* = 30 */ 105 CGX_CMD_GET_PERSIST_IGNORE, 106 CGX_CMD_SET_PERSIST_IGNORE, 107 CGX_CMD_SET_MAC_ADDR, 108}; 109 110/* async event ids */ 111enum cgx_evt_id { 112 CGX_EVT_NONE, 113 CGX_EVT_LINK_CHANGE, 114}; 115 116/* event types - cause of interrupt */ 117enum cgx_evt_type { 118 CGX_EVT_ASYNC, 119 CGX_EVT_CMD_RESP 120}; 121 122enum cgx_stat { 123 CGX_STAT_SUCCESS, 124 CGX_STAT_FAIL 125}; 126 127enum cgx_cmd_own { 128 /* default ownership with kernel/uefi/u-boot */ 129 CGX_OWN_NON_SECURE_SW, 130 /* set by kernel/uefi/u-boot after posting a new request to ATF */ 131 CGX_OWN_FIRMWARE, 132}; 133 134/* Supported LINK MODE enums 135 * Each link mode is a bit mask of these 136 * enums which are represented as bits 137 */ 138enum cgx_mode_t { 139 CGX_MODE_SGMII_BIT = 0, 140 CGX_MODE_1000_BASEX_BIT, 141 CGX_MODE_QSGMII_BIT, 142 CGX_MODE_10G_C2C_BIT, 143 CGX_MODE_10G_C2M_BIT, 144 CGX_MODE_10G_KR_BIT, 145 CGX_MODE_20G_C2C_BIT, 146 CGX_MODE_25G_C2C_BIT, 147 CGX_MODE_25G_C2M_BIT, 148 CGX_MODE_25G_2_C2C_BIT, 149 CGX_MODE_25G_CR_BIT, 150 CGX_MODE_25G_KR_BIT, 151 CGX_MODE_40G_C2C_BIT, 152 CGX_MODE_40G_C2M_BIT, 153 CGX_MODE_40G_CR4_BIT, 154 CGX_MODE_40G_KR4_BIT, 155 CGX_MODE_40GAUI_C2C_BIT, 156 CGX_MODE_50G_C2C_BIT, 157 CGX_MODE_50G_C2M_BIT, 158 CGX_MODE_50G_4_C2C_BIT, 159 CGX_MODE_50G_CR_BIT, 160 CGX_MODE_50G_KR_BIT, 161 CGX_MODE_80GAUI_C2C_BIT, 162 CGX_MODE_100G_C2C_BIT, 163 CGX_MODE_100G_C2M_BIT, 164 CGX_MODE_100G_CR4_BIT, 165 CGX_MODE_100G_KR4_BIT, 166 CGX_MODE_MAX_BIT /* = 29 */ 167}; 168 169/* scratchx(0) CSR used for ATF->non-secure SW communication. 170 * This acts as the status register 171 * Provides details on command ack/status, link status, error details 172 */ 173 174/* CAUTION : below structures are placed in order based on the bit positions 175 * For any updates/new bitfields, corresponding structures needs to be updated 176 */ 177struct cgx_evt_sts_s { /* start from bit 0 */ 178 u64 ack:1; 179 u64 evt_type:1; /* cgx_evt_type */ 180 u64 stat:1; /* cgx_stat */ 181 u64 id:6; /* cgx_evt_id/cgx_cmd_id */ 182 u64 reserved:55; 183}; 184 185/* all the below structures are in the same memory location of SCRATCHX(0) 186 * value can be read/written based on command ID 187 */ 188 189/* Resp to command IDs with command status as CGX_STAT_FAIL 190 * Not applicable for commands : 191 * CGX_CMD_LINK_BRING_UP/DOWN/CGX_EVT_LINK_CHANGE 192 * check struct cgx_lnk_sts_s comments 193 */ 194struct cgx_err_sts_s { /* start from bit 9 */ 195 u64 reserved1:9; 196 u64 type:10; /* cgx_error_type */ 197 u64 reserved2:35; 198}; 199 200/* Resp to cmd ID as CGX_CMD_GET_FW_VER with cmd status as CGX_STAT_SUCCESS */ 201struct cgx_ver_s { /* start from bit 9 */ 202 u64 reserved1:9; 203 u64 major_ver:4; 204 u64 minor_ver:4; 205 u64 reserved2:47; 206}; 207 208/* Resp to cmd ID as CGX_CMD_GET_MAC_ADDR with cmd status as CGX_STAT_SUCCESS 209 * Returns each byte of MAC address in a separate bit field 210 */ 211struct cgx_mac_addr_s { /* start from bit 9 */ 212 u64 reserved1:9; 213 u64 addr_0:8; 214 u64 addr_1:8; 215 u64 addr_2:8; 216 u64 addr_3:8; 217 u64 addr_4:8; 218 u64 addr_5:8; 219 u64 reserved2:7; 220}; 221 222/* Resp to cmd ID - CGX_CMD_LINK_BRING_UP/DOWN, event ID CGX_EVT_LINK_CHANGE 223 * status can be either CGX_STAT_FAIL or CGX_STAT_SUCCESS 224 * In case of CGX_STAT_FAIL, it indicates CGX configuration failed when 225 * processing link up/down/change command. Both err_type and current link status 226 * will be updated 227 * In case of CGX_STAT_SUCCESS, err_type will be CGX_ERR_NONE and current 228 * link status will be updated 229 */ 230struct cgx_lnk_sts_s { 231 u64 reserved1:9; 232 u64 link_up:1; 233 u64 full_duplex:1; 234 u64 speed:4; /* cgx_link_speed */ 235 u64 err_type:10; 236 u64 an:1; /* Current AN state : enabled/disabled */ 237 u64 fec:2; /* Current FEC type if enabled, if not 0 */ 238 u64 port:8; /* Share the current port info if required */ 239 u64 mode:8; /* cgx_mode_t enum integer value */ 240 u64 reserved2:20; 241}; 242 243struct sh_fwd_base_s { 244 u64 reserved1:9; 245 u64 addr:55; 246}; 247 248struct cgx_link_modes_s { 249 u64 reserved1:9; 250 u64 modes:55; 251}; 252 253/* Resp to cmd ID - CGX_CMD_GET_ADV_FEC/CGX_CMD_GET_SUPPORTED_FEC 254 * fec : 2 bits 255 * typedef enum cgx_fec_type { 256 * CGX_FEC_NONE, 257 * CGX_FEC_BASE_R, 258 * CGX_FEC_RS 259 * } fec_type_t; 260 */ 261struct cgx_fec_types_s { 262 u64 reserved1:9; 263 u64 fec:2; 264 u64 reserved2:53; 265}; 266 267/* Resp to cmd ID - CGX_CMD_GET_AN */ 268struct cgx_get_an_s { 269 u64 reserved1:9; 270 u64 an:1; 271 u64 reserved2:54; 272}; 273 274/* Resp to cmd ID - CGX_CMD_GET_PHY_MOD_TYPE */ 275struct cgx_get_phy_mod_type_s { 276 u64 reserved1:9; 277 u64 mod:1; /* 0=NRZ, 1=PAM4 */ 278 u64 reserved2:54; 279}; 280 281/* Resp to cmd ID - CGX_CMD_GET_PERSIST_IGNORE */ 282struct cgx_get_flash_ignore_s { 283 uint64_t reserved1:9; 284 uint64_t ignore:1; 285 uint64_t reserved2:54; 286}; 287 288union cgx_rsp_sts { 289 /* Fixed, applicable for all commands/events */ 290 struct cgx_evt_sts_s evt_sts; 291 /* response to CGX_CMD_LINK_BRINGUP/DOWN/LINK_CHANGE */ 292 struct cgx_lnk_sts_s link_sts; 293 /* response to CGX_CMD_GET_FW_VER */ 294 struct cgx_ver_s ver; 295 /* response to CGX_CMD_GET_MAC_ADDR */ 296 struct cgx_mac_addr_s mac_s; 297 /* response to CGX_CMD_GET_FWD_BASE */ 298 struct sh_fwd_base_s fwd_base_s; 299 /* response if evt_status = CMD_FAIL */ 300 struct cgx_err_sts_s err; 301 /* response to CGX_CMD_GET_SUPPORTED_FEC */ 302 struct cgx_fec_types_s supported_fec; 303 /* response to CGX_CMD_GET_LINK_MODES */ 304 struct cgx_link_modes_s supported_modes; 305 /* response to CGX_CMD_GET_ADV_LINK_MODES */ 306 struct cgx_link_modes_s adv_modes; 307 /* response to CGX_CMD_GET_ADV_FEC */ 308 struct cgx_fec_types_s adv_fec; 309 /* response to CGX_CMD_GET_AN */ 310 struct cgx_get_an_s an; 311 /* response to CGX_CMD_GET_PHY_MOD_TYPE */ 312 struct cgx_get_phy_mod_type_s phy_mod_type; 313 /* response to CGX_CMD_GET_PERSIST_IGNORE */ 314 struct cgx_get_flash_ignore_s persist; 315#ifdef NT_FW_CONFIG 316 /* response to CGX_CMD_GET_MKEX_SIZE */ 317 struct cgx_mcam_profile_sz_s prfl_sz; 318 /* response to CGX_CMD_GET_MKEX_PROFILE */ 319 struct cgx_mcam_profile_addr_s prfl_addr; 320#endif 321}; 322 323union cgx_scratchx0 { 324 u64 u; 325 union cgx_rsp_sts s; 326}; 327 328/* scratchx(1) CSR used for non-secure SW->ATF communication 329 * This CSR acts as a command register 330 */ 331struct cgx_cmd { /* start from bit 2 */ 332 u64 reserved1:2; 333 u64 id:6; /* cgx_request_id */ 334 u64 reserved2:56; 335}; 336 337/* all the below structures are in the same memory location of SCRATCHX(1) 338 * corresponding arguments for command Id needs to be updated 339 */ 340 341/* Any command using enable/disable as an argument need 342 * to pass the option via this structure. 343 * Ex: Loopback, HiGig... 344 */ 345struct cgx_ctl_args { /* start from bit 8 */ 346 u64 reserved1:8; 347 u64 enable:1; 348 u64 reserved2:55; 349}; 350 351/* command argument to be passed for cmd ID - CGX_CMD_SET_MTU */ 352struct cgx_mtu_args { 353 u64 reserved1:8; 354 u64 size:16; 355 u64 reserved2:40; 356}; 357 358/* command argument to be passed for cmd ID - CGX_CMD_MODE_CHANGE */ 359struct cgx_mode_change_args { 360 uint64_t reserved1:8; 361 uint64_t speed:4; /* cgx_link_speed enum */ 362 uint64_t duplex:1; /* 0 - full duplex, 1 - half duplex */ 363 uint64_t an:1; /* 0 - disable AN, 1 - enable AN */ 364 uint64_t port:8; /* device port */ 365 uint64_t mode:42; 366}; 367 368/* command argument to be passed for cmd ID - CGX_CMD_LINK_CHANGE */ 369struct cgx_link_change_args { /* start from bit 8 */ 370 u64 reserved1:8; 371 u64 link_up:1; 372 u64 full_duplex:1; 373 u64 speed:4; /* cgx_link_speed */ 374 u64 reserved2:50; 375}; 376 377/* command argument to be passed for cmd ID - CGX_CMD_SET_LINK_MODE */ 378struct cgx_set_mode_args { 379 u64 reserved1:8; 380 u64 mode:56; 381}; 382 383/* command argument to be passed for cmd ID - CGX_CMD_SET_FEC */ 384struct cgx_set_fec_args { 385 u64 reserved1:8; 386 u64 fec:2; 387 u64 reserved2:54; 388}; 389 390/* command argument to be passed for cmd ID - CGX_CMD_SET_PHY_MOD_TYPE */ 391struct cgx_set_phy_mod_args { 392 u64 reserved1:8; 393 u64 mod:1; /* 0=NRZ, 1=PAM4 */ 394 u64 reserved2:55; 395}; 396 397/* command argument to be passed for cmd ID - CGX_CMD_SET_PERSIST_IGNORE */ 398struct cgx_set_flash_ignore_args { 399 uint64_t reserved1:8; 400 uint64_t ignore:1; 401 uint64_t reserved2:55; 402}; 403 404/* command argument to be passed for cmd ID - CGX_CMD_SET_MAC_ADDR */ 405struct cgx_mac_addr_args { 406 uint64_t reserved1:8; 407 uint64_t addr:48; 408 uint64_t pf_id:8; 409}; 410 411struct cgx_prbs_args { 412 u64 reserved1:8; /* start from bit 8 */ 413 u64 lane:8; 414 u64 qlm:8; 415 u64 stop_on_error:1; 416 u64 mode:8; 417 u64 time:31; 418}; 419 420struct cgx_display_eye_args { 421 u64 reserved1:8; /* start from bit 8 */ 422 u64 qlm:8; 423 u64 lane:47; 424}; 425 426union cgx_cmd_s { 427 u64 own_status:2; /* cgx_cmd_own */ 428 struct cgx_cmd cmd; 429 struct cgx_ctl_args cmd_args; 430 struct cgx_mtu_args mtu_size; 431 struct cgx_link_change_args lnk_args; /* Input to CGX_CMD_LINK_CHANGE */ 432 struct cgx_set_mode_args mode_args; 433 struct cgx_mode_change_args mode_change_args; 434 struct cgx_set_fec_args fec_args; 435 struct cgx_set_phy_mod_args phy_mod_args; 436 struct cgx_set_flash_ignore_args persist_args; 437 struct cgx_mac_addr_args mac_args; 438 /* any other arg for command id * like : mtu, dmac filtering control */ 439 struct cgx_prbs_args prbs_args; 440 struct cgx_display_eye_args dsp_eye_args; 441}; 442 443union cgx_scratchx1 { 444 u64 u; 445 union cgx_cmd_s s; 446}; 447 448#endif /* __CGX_INTF_H__ */ 449