1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2012 Freescale Semiconductor, Inc.
4 *	Roy Zang <tie-fei.zang@freescale.com>
5 */
6#include <common.h>
7#include <phy.h>
8#include <fm_eth.h>
9#include <asm/io.h>
10#include <asm/immap_85xx.h>
11#include <asm/fsl_serdes.h>
12
13u32 port_to_devdisr[] = {
14	[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
15	[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
16	[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
17	[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
18	[FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
19	[FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
20	[FM1_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC1_9,
21	[FM1_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC1_10,
22	[FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
23	[FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
24	[FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
25	[FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
26	[FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
27	[FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
28	[FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5,
29	[FM2_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC2_6,
30	[FM2_DTSEC9] = FSL_CORENET_DEVDISR2_DTSEC2_9,
31	[FM2_DTSEC10] = FSL_CORENET_DEVDISR2_DTSEC2_10,
32	[FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2_1,
33	[FM2_10GEC2] = FSL_CORENET_DEVDISR2_10GEC2_2,
34};
35
36static int is_device_disabled(enum fm_port port)
37{
38	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
39	u32 devdisr2 = in_be32(&gur->devdisr2);
40
41	return port_to_devdisr[port] & devdisr2;
42}
43
44void fman_disable_port(enum fm_port port)
45{
46	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
47
48	setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
49}
50
51void fman_enable_port(enum fm_port port)
52{
53	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
54
55	clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
56}
57
58phy_interface_t fman_port_enet_if(enum fm_port port)
59{
60	ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
61	u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
62
63	if (is_device_disabled(port))
64		return PHY_INTERFACE_MODE_NA;
65
66	if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
67	    ((is_serdes_configured(XAUI_FM1_MAC9))	||
68	     (is_serdes_configured(XAUI_FM1_MAC10))	||
69	     (is_serdes_configured(XFI_FM1_MAC9))	||
70	     (is_serdes_configured(XFI_FM1_MAC10))))
71		return PHY_INTERFACE_MODE_XGMII;
72
73	if ((port == FM1_DTSEC9 || port == FM1_DTSEC10) &&
74	    ((is_serdes_configured(XFI_FM1_MAC9)) ||
75	     (is_serdes_configured(XFI_FM1_MAC10))))
76		return PHY_INTERFACE_MODE_NA;
77
78	if ((port == FM2_10GEC1 || port == FM2_10GEC2) &&
79	    ((is_serdes_configured(XAUI_FM2_MAC9))	||
80	     (is_serdes_configured(XAUI_FM2_MAC10))	||
81	     (is_serdes_configured(XFI_FM2_MAC9))	||
82	     (is_serdes_configured(XFI_FM2_MAC10))))
83		return PHY_INTERFACE_MODE_XGMII;
84
85#define FSL_CORENET_RCWSR13_EC1			0x60000000 /* bits 417..418 */
86#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII	0x00000000
87#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO		0x40000000
88#define FSL_CORENET_RCWSR13_EC2			0x18000000 /* bits 419..420 */
89#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII	0x00000000
90#define FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII	0x08000000
91#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO		0x10000000
92	/* handle RGMII first */
93	if ((port == FM2_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
94		FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII))
95		return PHY_INTERFACE_MODE_RGMII;
96
97	if ((port == FM1_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
98		FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII))
99		return PHY_INTERFACE_MODE_RGMII;
100
101	if ((port == FM2_DTSEC6) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
102		FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII))
103		return PHY_INTERFACE_MODE_RGMII;
104	switch (port) {
105	case FM1_DTSEC1:
106	case FM1_DTSEC2:
107	case FM1_DTSEC3:
108	case FM1_DTSEC4:
109	case FM1_DTSEC5:
110	case FM1_DTSEC6:
111	case FM1_DTSEC9:
112	case FM1_DTSEC10:
113		if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
114			return PHY_INTERFACE_MODE_SGMII;
115		break;
116	case FM2_DTSEC1:
117	case FM2_DTSEC2:
118	case FM2_DTSEC3:
119	case FM2_DTSEC4:
120	case FM2_DTSEC5:
121	case FM2_DTSEC6:
122	case FM2_DTSEC9:
123	case FM2_DTSEC10:
124		if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
125			return PHY_INTERFACE_MODE_SGMII;
126		break;
127	default:
128		break;
129	}
130
131	/* handle QSGMII */
132	switch (port) {
133	case FM1_DTSEC1:
134	case FM1_DTSEC2:
135	case FM1_DTSEC3:
136	case FM1_DTSEC4:
137		/* check lane G on SerDes1 */
138		if (is_serdes_configured(QSGMII_FM1_A))
139			return PHY_INTERFACE_MODE_QSGMII;
140		break;
141	case FM1_DTSEC5:
142	case FM1_DTSEC6:
143	case FM1_DTSEC9:
144	case FM1_DTSEC10:
145		/* check lane C on SerDes1 */
146		if (is_serdes_configured(QSGMII_FM1_B))
147			return PHY_INTERFACE_MODE_QSGMII;
148		break;
149	case FM2_DTSEC1:
150	case FM2_DTSEC2:
151	case FM2_DTSEC3:
152	case FM2_DTSEC4:
153		/* check lane G on SerDes2 */
154		if (is_serdes_configured(QSGMII_FM2_A))
155			return PHY_INTERFACE_MODE_QSGMII;
156		break;
157	case FM2_DTSEC5:
158	case FM2_DTSEC6:
159	case FM2_DTSEC9:
160	case FM2_DTSEC10:
161		/* check lane C on SerDes2 */
162		if (is_serdes_configured(QSGMII_FM2_B))
163			return PHY_INTERFACE_MODE_QSGMII;
164		break;
165	default:
166		break;
167	}
168
169	return PHY_INTERFACE_MODE_NA;
170}
171