1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2009-2015 Freescale Semiconductor, Inc. and others 4 * 5 * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver. 6 * Ported to U-Boot by Stefan Agner 7 * Based on RFC driver posted on Kernel Mailing list by Bill Pringlemeir 8 * Jason ported to M54418TWR and MVFA5. 9 * Authors: Stefan Agner <stefan.agner@toradex.com> 10 * Bill Pringlemeir <bpringlemeir@nbsps.com> 11 * Shaohui Xie <b21989@freescale.com> 12 * Jason Jin <Jason.jin@freescale.com> 13 * 14 * Based on original driver mpc5121_nfc.c. 15 * 16 * Limitations: 17 * - Untested on MPC5125 and M54418. 18 * - DMA and pipelining not used. 19 * - 2K pages or less. 20 * - HW ECC: Only 2K page with 64+ OOB. 21 * - HW ECC: Only 24 and 32-bit error correction implemented. 22 */ 23 24#include <common.h> 25#include <malloc.h> 26#include <dm/device_compat.h> 27#include <linux/printk.h> 28 29#include <linux/mtd/mtd.h> 30#include <linux/mtd/rawnand.h> 31#include <linux/mtd/partitions.h> 32 33#include <nand.h> 34#include <errno.h> 35#include <asm/io.h> 36#if CONFIG_NAND_VF610_NFC_DT 37#include <dm.h> 38#include <linux/io.h> 39#include <linux/ioport.h> 40#endif 41 42/* Register Offsets */ 43#define NFC_FLASH_CMD1 0x3F00 44#define NFC_FLASH_CMD2 0x3F04 45#define NFC_COL_ADDR 0x3F08 46#define NFC_ROW_ADDR 0x3F0c 47#define NFC_ROW_ADDR_INC 0x3F14 48#define NFC_FLASH_STATUS1 0x3F18 49#define NFC_FLASH_STATUS2 0x3F1c 50#define NFC_CACHE_SWAP 0x3F28 51#define NFC_SECTOR_SIZE 0x3F2c 52#define NFC_FLASH_CONFIG 0x3F30 53#define NFC_IRQ_STATUS 0x3F38 54 55/* Addresses for NFC MAIN RAM BUFFER areas */ 56#define NFC_MAIN_AREA(n) ((n) * 0x1000) 57 58#define PAGE_2K 0x0800 59#define OOB_64 0x0040 60#define OOB_MAX 0x0100 61 62/* 63 * NFC_CMD2[CODE] values. See section: 64 * - 31.4.7 Flash Command Code Description, Vybrid manual 65 * - 23.8.6 Flash Command Sequencer, MPC5125 manual 66 * 67 * Briefly these are bitmasks of controller cycles. 68 */ 69#define READ_PAGE_CMD_CODE 0x7EE0 70#define READ_ONFI_PARAM_CMD_CODE 0x4860 71#define PROGRAM_PAGE_CMD_CODE 0x7FC0 72#define ERASE_CMD_CODE 0x4EC0 73#define READ_ID_CMD_CODE 0x4804 74#define RESET_CMD_CODE 0x4040 75#define STATUS_READ_CMD_CODE 0x4068 76 77/* NFC ECC mode define */ 78#define ECC_BYPASS 0 79#define ECC_45_BYTE 6 80#define ECC_60_BYTE 7 81 82/*** Register Mask and bit definitions */ 83 84/* NFC_FLASH_CMD1 Field */ 85#define CMD_BYTE2_MASK 0xFF000000 86#define CMD_BYTE2_SHIFT 24 87 88/* NFC_FLASH_CM2 Field */ 89#define CMD_BYTE1_MASK 0xFF000000 90#define CMD_BYTE1_SHIFT 24 91#define CMD_CODE_MASK 0x00FFFF00 92#define CMD_CODE_SHIFT 8 93#define BUFNO_MASK 0x00000006 94#define BUFNO_SHIFT 1 95#define START_BIT (1<<0) 96 97/* NFC_COL_ADDR Field */ 98#define COL_ADDR_MASK 0x0000FFFF 99#define COL_ADDR_SHIFT 0 100 101/* NFC_ROW_ADDR Field */ 102#define ROW_ADDR_MASK 0x00FFFFFF 103#define ROW_ADDR_SHIFT 0 104#define ROW_ADDR_CHIP_SEL_RB_MASK 0xF0000000 105#define ROW_ADDR_CHIP_SEL_RB_SHIFT 28 106#define ROW_ADDR_CHIP_SEL_MASK 0x0F000000 107#define ROW_ADDR_CHIP_SEL_SHIFT 24 108 109/* NFC_FLASH_STATUS2 Field */ 110#define STATUS_BYTE1_MASK 0x000000FF 111 112/* NFC_FLASH_CONFIG Field */ 113#define CFG_ECC_SRAM_ADDR_MASK 0x7FC00000 114#define CFG_ECC_SRAM_ADDR_SHIFT 22 115#define CFG_ECC_SRAM_REQ_BIT (1<<21) 116#define CFG_DMA_REQ_BIT (1<<20) 117#define CFG_ECC_MODE_MASK 0x000E0000 118#define CFG_ECC_MODE_SHIFT 17 119#define CFG_FAST_FLASH_BIT (1<<16) 120#define CFG_16BIT (1<<7) 121#define CFG_BOOT_MODE_BIT (1<<6) 122#define CFG_ADDR_AUTO_INCR_BIT (1<<5) 123#define CFG_BUFNO_AUTO_INCR_BIT (1<<4) 124#define CFG_PAGE_CNT_MASK 0xF 125#define CFG_PAGE_CNT_SHIFT 0 126 127/* NFC_IRQ_STATUS Field */ 128#define IDLE_IRQ_BIT (1<<29) 129#define IDLE_EN_BIT (1<<20) 130#define CMD_DONE_CLEAR_BIT (1<<18) 131#define IDLE_CLEAR_BIT (1<<17) 132 133#define NFC_TIMEOUT (1000) 134 135/* 136 * ECC status - seems to consume 8 bytes (double word). The documented 137 * status byte is located in the lowest byte of the second word (which is 138 * the 4th or 7th byte depending on endianness). 139 * Calculate an offset to store the ECC status at the end of the buffer. 140 */ 141#define ECC_SRAM_ADDR (PAGE_2K + OOB_MAX - 8) 142 143#define ECC_STATUS 0x4 144#define ECC_STATUS_MASK 0x80 145#define ECC_STATUS_ERR_COUNT 0x3F 146 147enum vf610_nfc_alt_buf { 148 ALT_BUF_DATA = 0, 149 ALT_BUF_ID = 1, 150 ALT_BUF_STAT = 2, 151 ALT_BUF_ONFI = 3, 152}; 153 154struct vf610_nfc { 155 struct nand_chip chip; 156 /* NULL without CONFIG_NAND_VF610_NFC_DT */ 157 struct udevice *dev; 158 void __iomem *regs; 159 uint buf_offset; 160 int write_sz; 161 /* Status and ID are in alternate locations. */ 162 enum vf610_nfc_alt_buf alt_buf; 163}; 164 165#define mtd_to_nfc(_mtd) nand_get_controller_data(mtd_to_nand(_mtd)) 166 167#if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES) 168#define ECC_HW_MODE ECC_45_BYTE 169 170static struct nand_ecclayout vf610_nfc_ecc = { 171 .eccbytes = 45, 172 .eccpos = {19, 20, 21, 22, 23, 173 24, 25, 26, 27, 28, 29, 30, 31, 174 32, 33, 34, 35, 36, 37, 38, 39, 175 40, 41, 42, 43, 44, 45, 46, 47, 176 48, 49, 50, 51, 52, 53, 54, 55, 177 56, 57, 58, 59, 60, 61, 62, 63}, 178 .oobfree = { 179 {.offset = 2, 180 .length = 17} } 181}; 182#elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES) 183#define ECC_HW_MODE ECC_60_BYTE 184 185static struct nand_ecclayout vf610_nfc_ecc = { 186 .eccbytes = 60, 187 .eccpos = { 4, 5, 6, 7, 8, 9, 10, 11, 188 12, 13, 14, 15, 16, 17, 18, 19, 189 20, 21, 22, 23, 24, 25, 26, 27, 190 28, 29, 30, 31, 32, 33, 34, 35, 191 36, 37, 38, 39, 40, 41, 42, 43, 192 44, 45, 46, 47, 48, 49, 50, 51, 193 52, 53, 54, 55, 56, 57, 58, 59, 194 60, 61, 62, 63 }, 195 .oobfree = { 196 {.offset = 2, 197 .length = 2} } 198}; 199#endif 200 201static inline u32 vf610_nfc_read(struct mtd_info *mtd, uint reg) 202{ 203 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 204 205 return readl(nfc->regs + reg); 206} 207 208static inline void vf610_nfc_write(struct mtd_info *mtd, uint reg, u32 val) 209{ 210 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 211 212 writel(val, nfc->regs + reg); 213} 214 215static inline void vf610_nfc_set(struct mtd_info *mtd, uint reg, u32 bits) 216{ 217 vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) | bits); 218} 219 220static inline void vf610_nfc_clear(struct mtd_info *mtd, uint reg, u32 bits) 221{ 222 vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) & ~bits); 223} 224 225static inline void vf610_nfc_set_field(struct mtd_info *mtd, u32 reg, 226 u32 mask, u32 shift, u32 val) 227{ 228 vf610_nfc_write(mtd, reg, 229 (vf610_nfc_read(mtd, reg) & (~mask)) | val << shift); 230} 231 232static inline void vf610_nfc_memcpy(void *dst, const void *src, size_t n) 233{ 234 /* 235 * Use this accessor for the internal SRAM buffers. On the ARM 236 * Freescale Vybrid SoC it's known that the driver can treat 237 * the SRAM buffer as if it's memory. Other platform might need 238 * to treat the buffers differently. 239 * 240 * For the time being, use memcpy 241 */ 242 memcpy(dst, src, n); 243} 244 245/* Clear flags for upcoming command */ 246static inline void vf610_nfc_clear_status(void __iomem *regbase) 247{ 248 void __iomem *reg = regbase + NFC_IRQ_STATUS; 249 u32 tmp = __raw_readl(reg); 250 tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT; 251 __raw_writel(tmp, reg); 252} 253 254/* Wait for complete operation */ 255static void vf610_nfc_done(struct mtd_info *mtd) 256{ 257 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 258 uint start; 259 260 /* 261 * Barrier is needed after this write. This write need 262 * to be done before reading the next register the first 263 * time. 264 * vf610_nfc_set implicates such a barrier by using writel 265 * to write to the register. 266 */ 267 vf610_nfc_set(mtd, NFC_FLASH_CMD2, START_BIT); 268 269 start = get_timer(0); 270 271 while (!(vf610_nfc_read(mtd, NFC_IRQ_STATUS) & IDLE_IRQ_BIT)) { 272 if (get_timer(start) > NFC_TIMEOUT) { 273 printf("Timeout while waiting for IDLE.\n"); 274 return; 275 } 276 } 277 vf610_nfc_clear_status(nfc->regs); 278} 279 280static u8 vf610_nfc_get_id(struct mtd_info *mtd, int col) 281{ 282 u32 flash_id; 283 284 if (col < 4) { 285 flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS1); 286 flash_id >>= (3 - col) * 8; 287 } else { 288 flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS2); 289 flash_id >>= 24; 290 } 291 292 return flash_id & 0xff; 293} 294 295static u8 vf610_nfc_get_status(struct mtd_info *mtd) 296{ 297 return vf610_nfc_read(mtd, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK; 298} 299 300/* Single command */ 301static void vf610_nfc_send_command(void __iomem *regbase, u32 cmd_byte1, 302 u32 cmd_code) 303{ 304 void __iomem *reg = regbase + NFC_FLASH_CMD2; 305 u32 tmp; 306 vf610_nfc_clear_status(regbase); 307 308 tmp = __raw_readl(reg); 309 tmp &= ~(CMD_BYTE1_MASK | CMD_CODE_MASK | BUFNO_MASK); 310 tmp |= cmd_byte1 << CMD_BYTE1_SHIFT; 311 tmp |= cmd_code << CMD_CODE_SHIFT; 312 __raw_writel(tmp, reg); 313} 314 315/* Two commands */ 316static void vf610_nfc_send_commands(void __iomem *regbase, u32 cmd_byte1, 317 u32 cmd_byte2, u32 cmd_code) 318{ 319 void __iomem *reg = regbase + NFC_FLASH_CMD1; 320 u32 tmp; 321 vf610_nfc_send_command(regbase, cmd_byte1, cmd_code); 322 323 tmp = __raw_readl(reg); 324 tmp &= ~CMD_BYTE2_MASK; 325 tmp |= cmd_byte2 << CMD_BYTE2_SHIFT; 326 __raw_writel(tmp, reg); 327} 328 329static void vf610_nfc_addr_cycle(struct mtd_info *mtd, int column, int page) 330{ 331 if (column != -1) { 332 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 333 if (nfc->chip.options & NAND_BUSWIDTH_16) 334 column = column / 2; 335 vf610_nfc_set_field(mtd, NFC_COL_ADDR, COL_ADDR_MASK, 336 COL_ADDR_SHIFT, column); 337 } 338 if (page != -1) 339 vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK, 340 ROW_ADDR_SHIFT, page); 341} 342 343static inline void vf610_nfc_ecc_mode(struct mtd_info *mtd, int ecc_mode) 344{ 345 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, 346 CFG_ECC_MODE_MASK, 347 CFG_ECC_MODE_SHIFT, ecc_mode); 348} 349 350static inline void vf610_nfc_transfer_size(void __iomem *regbase, int size) 351{ 352 __raw_writel(size, regbase + NFC_SECTOR_SIZE); 353} 354 355/* Send command to NAND chip */ 356static void vf610_nfc_command(struct mtd_info *mtd, unsigned command, 357 int column, int page) 358{ 359 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 360 int trfr_sz = nfc->chip.options & NAND_BUSWIDTH_16 ? 1 : 0; 361 362 nfc->buf_offset = max(column, 0); 363 nfc->alt_buf = ALT_BUF_DATA; 364 365 switch (command) { 366 case NAND_CMD_SEQIN: 367 /* Use valid column/page from preread... */ 368 vf610_nfc_addr_cycle(mtd, column, page); 369 nfc->buf_offset = 0; 370 371 /* 372 * SEQIN => data => PAGEPROG sequence is done by the controller 373 * hence we do not need to issue the command here... 374 */ 375 return; 376 case NAND_CMD_PAGEPROG: 377 trfr_sz += nfc->write_sz; 378 vf610_nfc_ecc_mode(mtd, ECC_HW_MODE); 379 vf610_nfc_transfer_size(nfc->regs, trfr_sz); 380 vf610_nfc_send_commands(nfc->regs, NAND_CMD_SEQIN, 381 command, PROGRAM_PAGE_CMD_CODE); 382 break; 383 384 case NAND_CMD_RESET: 385 vf610_nfc_transfer_size(nfc->regs, 0); 386 vf610_nfc_send_command(nfc->regs, command, RESET_CMD_CODE); 387 break; 388 389 case NAND_CMD_READOOB: 390 trfr_sz += mtd->oobsize; 391 column = mtd->writesize; 392 vf610_nfc_transfer_size(nfc->regs, trfr_sz); 393 vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0, 394 NAND_CMD_READSTART, READ_PAGE_CMD_CODE); 395 vf610_nfc_addr_cycle(mtd, column, page); 396 vf610_nfc_ecc_mode(mtd, ECC_BYPASS); 397 break; 398 399 case NAND_CMD_READ0: 400 trfr_sz += mtd->writesize + mtd->oobsize; 401 vf610_nfc_transfer_size(nfc->regs, trfr_sz); 402 vf610_nfc_ecc_mode(mtd, ECC_HW_MODE); 403 vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0, 404 NAND_CMD_READSTART, READ_PAGE_CMD_CODE); 405 vf610_nfc_addr_cycle(mtd, column, page); 406 break; 407 408 case NAND_CMD_PARAM: 409 nfc->alt_buf = ALT_BUF_ONFI; 410 trfr_sz = 3 * sizeof(struct nand_onfi_params); 411 vf610_nfc_transfer_size(nfc->regs, trfr_sz); 412 vf610_nfc_send_command(nfc->regs, NAND_CMD_PARAM, 413 READ_ONFI_PARAM_CMD_CODE); 414 vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK, 415 ROW_ADDR_SHIFT, column); 416 vf610_nfc_ecc_mode(mtd, ECC_BYPASS); 417 break; 418 419 case NAND_CMD_ERASE1: 420 vf610_nfc_transfer_size(nfc->regs, 0); 421 vf610_nfc_send_commands(nfc->regs, command, 422 NAND_CMD_ERASE2, ERASE_CMD_CODE); 423 vf610_nfc_addr_cycle(mtd, column, page); 424 break; 425 426 case NAND_CMD_READID: 427 nfc->alt_buf = ALT_BUF_ID; 428 nfc->buf_offset = 0; 429 vf610_nfc_transfer_size(nfc->regs, 0); 430 vf610_nfc_send_command(nfc->regs, command, READ_ID_CMD_CODE); 431 vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK, 432 ROW_ADDR_SHIFT, column); 433 break; 434 435 case NAND_CMD_STATUS: 436 nfc->alt_buf = ALT_BUF_STAT; 437 vf610_nfc_transfer_size(nfc->regs, 0); 438 vf610_nfc_send_command(nfc->regs, command, STATUS_READ_CMD_CODE); 439 break; 440 default: 441 return; 442 } 443 444 vf610_nfc_done(mtd); 445 446 nfc->write_sz = 0; 447} 448 449/* Read data from NFC buffers */ 450static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len) 451{ 452 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 453 uint c = nfc->buf_offset; 454 455 /* Alternate buffers are only supported through read_byte */ 456 if (nfc->alt_buf) 457 return; 458 459 vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c, len); 460 461 nfc->buf_offset += len; 462} 463 464/* Write data to NFC buffers */ 465static void vf610_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, 466 int len) 467{ 468 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 469 uint c = nfc->buf_offset; 470 uint l; 471 472 l = min_t(uint, len, mtd->writesize + mtd->oobsize - c); 473 vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l); 474 475 nfc->write_sz += l; 476 nfc->buf_offset += l; 477} 478 479/* Read byte from NFC buffers */ 480static uint8_t vf610_nfc_read_byte(struct mtd_info *mtd) 481{ 482 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 483 u8 tmp; 484 uint c = nfc->buf_offset; 485 486 switch (nfc->alt_buf) { 487 case ALT_BUF_ID: 488 tmp = vf610_nfc_get_id(mtd, c); 489 break; 490 case ALT_BUF_STAT: 491 tmp = vf610_nfc_get_status(mtd); 492 break; 493#ifdef __LITTLE_ENDIAN 494 case ALT_BUF_ONFI: 495 /* Reverse byte since the controller uses big endianness */ 496 c = nfc->buf_offset ^ 0x3; 497 /* fall-through */ 498#endif 499 default: 500 tmp = *((u8 *)(nfc->regs + NFC_MAIN_AREA(0) + c)); 501 break; 502 } 503 nfc->buf_offset++; 504 return tmp; 505} 506 507/* Read word from NFC buffers */ 508static u16 vf610_nfc_read_word(struct mtd_info *mtd) 509{ 510 u16 tmp; 511 512 vf610_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp)); 513 return tmp; 514} 515 516/* If not provided, upper layers apply a fixed delay. */ 517static int vf610_nfc_dev_ready(struct mtd_info *mtd) 518{ 519 /* NFC handles R/B internally; always ready. */ 520 return 1; 521} 522 523/* 524 * This function supports Vybrid only (MPC5125 would have full RB and four CS) 525 */ 526static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip) 527{ 528#ifdef CONFIG_VF610 529 u32 tmp = vf610_nfc_read(mtd, NFC_ROW_ADDR); 530 tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK); 531 532 if (chip >= 0) { 533 tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT; 534 tmp |= (1 << chip) << ROW_ADDR_CHIP_SEL_SHIFT; 535 } 536 537 vf610_nfc_write(mtd, NFC_ROW_ADDR, tmp); 538#endif 539} 540 541/* Count the number of 0's in buff upto max_bits */ 542static inline int count_written_bits(uint8_t *buff, int size, int max_bits) 543{ 544 uint32_t *buff32 = (uint32_t *)buff; 545 int k, written_bits = 0; 546 547 for (k = 0; k < (size / 4); k++) { 548 written_bits += hweight32(~buff32[k]); 549 if (written_bits > max_bits) 550 break; 551 } 552 553 return written_bits; 554} 555 556static inline int vf610_nfc_correct_data(struct mtd_info *mtd, uint8_t *dat, 557 uint8_t *oob, int page) 558{ 559 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 560 u32 ecc_status_off = NFC_MAIN_AREA(0) + ECC_SRAM_ADDR + ECC_STATUS; 561 u8 ecc_status; 562 u8 ecc_count; 563 int flips; 564 int flips_threshold = nfc->chip.ecc.strength / 2; 565 566 ecc_status = vf610_nfc_read(mtd, ecc_status_off) & 0xff; 567 ecc_count = ecc_status & ECC_STATUS_ERR_COUNT; 568 569 if (!(ecc_status & ECC_STATUS_MASK)) 570 return ecc_count; 571 572 /* Read OOB without ECC unit enabled */ 573 vf610_nfc_command(mtd, NAND_CMD_READOOB, 0, page); 574 vf610_nfc_read_buf(mtd, oob, mtd->oobsize); 575 576 /* 577 * On an erased page, bit count (including OOB) should be zero or 578 * at least less then half of the ECC strength. 579 */ 580 flips = count_written_bits(dat, nfc->chip.ecc.size, flips_threshold); 581 flips += count_written_bits(oob, mtd->oobsize, flips_threshold); 582 583 if (unlikely(flips > flips_threshold)) 584 return -EINVAL; 585 586 /* Erased page. */ 587 memset(dat, 0xff, nfc->chip.ecc.size); 588 memset(oob, 0xff, mtd->oobsize); 589 return flips; 590} 591 592static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip, 593 uint8_t *buf, int oob_required, int page) 594{ 595 int eccsize = chip->ecc.size; 596 int stat; 597 598 vf610_nfc_read_buf(mtd, buf, eccsize); 599 if (oob_required) 600 vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize); 601 602 stat = vf610_nfc_correct_data(mtd, buf, chip->oob_poi, page); 603 604 if (stat < 0) { 605 mtd->ecc_stats.failed++; 606 return 0; 607 } else { 608 mtd->ecc_stats.corrected += stat; 609 return stat; 610 } 611} 612 613/* 614 * ECC will be calculated automatically 615 */ 616static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip, 617 const uint8_t *buf, int oob_required, int page) 618{ 619 struct vf610_nfc *nfc = mtd_to_nfc(mtd); 620 621 vf610_nfc_write_buf(mtd, buf, mtd->writesize); 622 if (oob_required) 623 vf610_nfc_write_buf(mtd, chip->oob_poi, mtd->oobsize); 624 625 /* Always write whole page including OOB due to HW ECC */ 626 nfc->write_sz = mtd->writesize + mtd->oobsize; 627 628 return 0; 629} 630 631struct vf610_nfc_config { 632 int hardware_ecc; 633 int width; 634 int flash_bbt; 635}; 636 637static int vf610_nfc_nand_init(struct vf610_nfc *nfc, int devnum) 638{ 639 struct nand_chip *chip = &nfc->chip; 640 struct mtd_info *mtd = nand_to_mtd(chip); 641 int err = 0; 642 struct vf610_nfc_config cfg = { 643 .hardware_ecc = 1, 644#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT 645 .width = 16, 646#else 647 .width = 8, 648#endif 649 .flash_bbt = 1, 650 }; 651 652 nand_set_controller_data(chip, nfc); 653 654 if (cfg.width == 16) 655 chip->options |= NAND_BUSWIDTH_16; 656 657 chip->dev_ready = vf610_nfc_dev_ready; 658 chip->cmdfunc = vf610_nfc_command; 659 chip->read_byte = vf610_nfc_read_byte; 660 chip->read_word = vf610_nfc_read_word; 661 chip->read_buf = vf610_nfc_read_buf; 662 chip->write_buf = vf610_nfc_write_buf; 663 chip->select_chip = vf610_nfc_select_chip; 664 665 chip->options |= NAND_NO_SUBPAGE_WRITE; 666 667 chip->ecc.size = PAGE_2K; 668 669 /* Set configuration register. */ 670 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_16BIT); 671 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_ADDR_AUTO_INCR_BIT); 672 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_BUFNO_AUTO_INCR_BIT); 673 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_BOOT_MODE_BIT); 674 vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_DMA_REQ_BIT); 675 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CFG_FAST_FLASH_BIT); 676 677 /* Disable virtual pages, only one elementary transfer unit */ 678 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CFG_PAGE_CNT_MASK, 679 CFG_PAGE_CNT_SHIFT, 1); 680 681 /* first scan to find the device and get the page size */ 682 if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) { 683 err = -ENXIO; 684 goto error; 685 } 686 687 if (cfg.width == 16) 688 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CFG_16BIT); 689 690 /* Bad block options. */ 691 if (cfg.flash_bbt) 692 chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB | 693 NAND_BBT_CREATE; 694 695 /* Single buffer only, max 256 OOB minus ECC status */ 696 if (mtd->writesize + mtd->oobsize > PAGE_2K + OOB_MAX - 8) { 697 dev_err(nfc->dev, "Unsupported flash page size\n"); 698 err = -ENXIO; 699 goto error; 700 } 701 702 if (cfg.hardware_ecc) { 703 if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) { 704 dev_err(nfc->dev, "Unsupported flash with hwecc\n"); 705 err = -ENXIO; 706 goto error; 707 } 708 709 if (chip->ecc.size != mtd->writesize) { 710 dev_err(nfc->dev, "ecc size: %d\n", chip->ecc.size); 711 dev_err(nfc->dev, "Step size needs to be page size\n"); 712 err = -ENXIO; 713 goto error; 714 } 715 716 /* Current HW ECC layouts only use 64 bytes of OOB */ 717 if (mtd->oobsize > 64) 718 mtd->oobsize = 64; 719 720 /* propagate ecc.layout to mtd_info */ 721 mtd->ecclayout = chip->ecc.layout; 722 chip->ecc.read_page = vf610_nfc_read_page; 723 chip->ecc.write_page = vf610_nfc_write_page; 724 chip->ecc.mode = NAND_ECC_HW; 725 726 chip->ecc.size = PAGE_2K; 727 chip->ecc.layout = &vf610_nfc_ecc; 728#if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES) 729 chip->ecc.strength = 24; 730 chip->ecc.bytes = 45; 731#elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES) 732 chip->ecc.strength = 32; 733 chip->ecc.bytes = 60; 734#endif 735 736 /* Set ECC_STATUS offset */ 737 vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, 738 CFG_ECC_SRAM_ADDR_MASK, 739 CFG_ECC_SRAM_ADDR_SHIFT, 740 ECC_SRAM_ADDR >> 3); 741 742 /* Enable ECC status in SRAM */ 743 vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CFG_ECC_SRAM_REQ_BIT); 744 } 745 746 /* second phase scan */ 747 err = nand_scan_tail(mtd); 748 if (err) 749 return err; 750 751 err = nand_register(devnum, mtd); 752 if (err) 753 return err; 754 755 return 0; 756 757error: 758 return err; 759} 760 761#if CONFIG_NAND_VF610_NFC_DT 762static const struct udevice_id vf610_nfc_dt_ids[] = { 763 { 764 .compatible = "fsl,vf610-nfc", 765 }, 766 { /* sentinel */ } 767}; 768 769static int vf610_nfc_dt_probe(struct udevice *dev) 770{ 771 struct resource res; 772 struct vf610_nfc *nfc = dev_get_priv(dev); 773 int ret; 774 775 ret = dev_read_resource(dev, 0, &res); 776 if (ret) 777 return ret; 778 779 nfc->regs = devm_ioremap(dev, res.start, resource_size(&res)); 780 nfc->dev = dev; 781 return vf610_nfc_nand_init(nfc, 0); 782} 783 784U_BOOT_DRIVER(vf610_nfc_dt) = { 785 .name = "vf610-nfc-dt", 786 .id = UCLASS_MTD, 787 .of_match = vf610_nfc_dt_ids, 788 .priv_auto = sizeof(struct vf610_nfc), 789 .probe = vf610_nfc_dt_probe, 790}; 791 792void board_nand_init(void) 793{ 794 struct udevice *dev; 795 int ret; 796 797 ret = uclass_get_device_by_driver(UCLASS_MTD, 798 DM_DRIVER_GET(vf610_nfc_dt), 799 &dev); 800 if (ret && ret != -ENODEV) 801 pr_err("Failed to initialize NAND controller. (error %d)\n", 802 ret); 803} 804#else 805void board_nand_init(void) 806{ 807 int err; 808 struct vf610_nfc *nfc; 809 810 nfc = calloc(1, sizeof(*nfc)); 811 if (!nfc) { 812 printf("%s: Out of memory\n", __func__); 813 return; 814 } 815 816 nfc->regs = (void __iomem *)CFG_SYS_NAND_BASE; 817 err = vf610_nfc_nand_init(nfc, 0); 818 if (err) 819 printf("VF610 NAND init failed (err %d)\n", err); 820} 821#endif /* CONFIG_NAND_VF610_NFC_DT */ 822