1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2006-2008 4 * Stefan Roese, DENX Software Engineering, sr@denx.de. 5 */ 6 7#include <common.h> 8#include <nand.h> 9#include <system-constants.h> 10#include <asm/io.h> 11#include <linux/mtd/nand_ecc.h> 12#include <linux/mtd/rawnand.h> 13 14static int nand_ecc_pos[] = CFG_SYS_NAND_ECCPOS; 15static struct mtd_info *mtd; 16static struct nand_chip nand_chip; 17 18#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ 19 CFG_SYS_NAND_ECCSIZE) 20#define ECCTOTAL (ECCSTEPS * CFG_SYS_NAND_ECCBYTES) 21 22 23#if (CONFIG_SYS_NAND_PAGE_SIZE <= 512) 24/* 25 * NAND command for small page NAND devices (512) 26 */ 27static int nand_command(int block, int page, uint32_t offs, 28 u8 cmd) 29{ 30 struct nand_chip *this = mtd_to_nand(mtd); 31 int page_addr = page + block * SYS_NAND_BLOCK_PAGES; 32 33 while (!this->dev_ready(mtd)) 34 ; 35 36 /* Begin command latch cycle */ 37 this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); 38 /* Set ALE and clear CLE to start address cycle */ 39 /* Column address */ 40 this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE); 41 this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */ 42 this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff, 43 NAND_CTRL_ALE); /* A[24:17] */ 44 /* Latch in address */ 45 this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); 46 47 /* 48 * Wait a while for the data to be ready 49 */ 50 while (!this->dev_ready(mtd)) 51 ; 52 53 return 0; 54} 55#else 56/* 57 * NAND command for large page NAND devices (2k) 58 */ 59static int nand_command(int block, int page, uint32_t offs, 60 u8 cmd) 61{ 62 struct nand_chip *this = mtd_to_nand(mtd); 63 int page_addr = page + block * SYS_NAND_BLOCK_PAGES; 64 void (*hwctrl)(struct mtd_info *mtd, int cmd, 65 unsigned int ctrl) = this->cmd_ctrl; 66 67 while (!this->dev_ready(mtd)) 68 ; 69 70 /* Emulate NAND_CMD_READOOB */ 71 if (cmd == NAND_CMD_READOOB) { 72 offs += CONFIG_SYS_NAND_PAGE_SIZE; 73 cmd = NAND_CMD_READ0; 74 } 75 76 /* Shift the offset from byte addressing to word addressing. */ 77 if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd)) 78 offs >>= 1; 79 80 /* Begin command latch cycle */ 81 hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); 82 /* Set ALE and clear CLE to start address cycle */ 83 /* Column address */ 84 hwctrl(mtd, offs & 0xff, 85 NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */ 86 hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */ 87 /* Row address */ 88 hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */ 89 hwctrl(mtd, ((page_addr >> 8) & 0xff), 90 NAND_CTRL_ALE); /* A[27:20] */ 91#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE 92 /* One more address cycle for devices > 128MiB */ 93 hwctrl(mtd, (page_addr >> 16) & 0x0f, 94 NAND_CTRL_ALE); /* A[31:28] */ 95#endif 96 /* Latch in address */ 97 hwctrl(mtd, NAND_CMD_READSTART, 98 NAND_CTRL_CLE | NAND_CTRL_CHANGE); 99 hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); 100 101 /* 102 * Wait a while for the data to be ready 103 */ 104 while (!this->dev_ready(mtd)) 105 ; 106 107 return 0; 108} 109#endif 110 111static int nand_is_bad_block(int block) 112{ 113 struct nand_chip *this = mtd_to_nand(mtd); 114 u_char bb_data[2]; 115 116 nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, 117 NAND_CMD_READOOB); 118 119 /* 120 * Read one byte (or two if it's a 16 bit chip). 121 */ 122 if (this->options & NAND_BUSWIDTH_16) { 123 this->read_buf(mtd, bb_data, 2); 124 if (bb_data[0] != 0xff || bb_data[1] != 0xff) 125 return 1; 126 } else { 127 this->read_buf(mtd, bb_data, 1); 128 if (bb_data[0] != 0xff) 129 return 1; 130 } 131 132 return 0; 133} 134 135#if defined(CONFIG_SYS_NAND_HW_ECC_OOBFIRST) 136static int nand_read_page(int block, int page, uchar *dst) 137{ 138 struct nand_chip *this = mtd_to_nand(mtd); 139 u_char ecc_calc[ECCTOTAL]; 140 u_char ecc_code[ECCTOTAL]; 141 u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; 142 int i; 143 int eccsize = CFG_SYS_NAND_ECCSIZE; 144 int eccbytes = CFG_SYS_NAND_ECCBYTES; 145 int eccsteps = ECCSTEPS; 146 uint8_t *p = dst; 147 148 nand_command(block, page, 0, NAND_CMD_READOOB); 149 this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE); 150 nand_command(block, page, 0, NAND_CMD_READ0); 151 152 /* Pick the ECC bytes out of the oob data */ 153 for (i = 0; i < ECCTOTAL; i++) 154 ecc_code[i] = oob_data[nand_ecc_pos[i]]; 155 156 157 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 158 this->ecc.hwctl(mtd, NAND_ECC_READ); 159 this->read_buf(mtd, p, eccsize); 160 this->ecc.calculate(mtd, p, &ecc_calc[i]); 161 this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); 162 } 163 164 return 0; 165} 166#else 167static int nand_read_page(int block, int page, void *dst) 168{ 169 struct nand_chip *this = mtd_to_nand(mtd); 170 u_char ecc_calc[ECCTOTAL]; 171 u_char ecc_code[ECCTOTAL]; 172 u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; 173 int i; 174 int eccsize = CFG_SYS_NAND_ECCSIZE; 175 int eccbytes = CFG_SYS_NAND_ECCBYTES; 176 int eccsteps = ECCSTEPS; 177 uint8_t *p = dst; 178 179 nand_command(block, page, 0, NAND_CMD_READ0); 180 181 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 182 if (this->ecc.mode != NAND_ECC_SOFT) 183 this->ecc.hwctl(mtd, NAND_ECC_READ); 184 this->read_buf(mtd, p, eccsize); 185 this->ecc.calculate(mtd, p, &ecc_calc[i]); 186 } 187 this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE); 188 189 /* Pick the ECC bytes out of the oob data */ 190 for (i = 0; i < ECCTOTAL; i++) 191 ecc_code[i] = oob_data[nand_ecc_pos[i]]; 192 193 eccsteps = ECCSTEPS; 194 p = dst; 195 196 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 197 /* No chance to do something with the possible error message 198 * from correct_data(). We just hope that all possible errors 199 * are corrected by this routine. 200 */ 201 this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); 202 } 203 204 return 0; 205} 206#endif 207 208/* nand_init() - initialize data to make nand usable by SPL */ 209void nand_init(void) 210{ 211 /* 212 * Init board specific nand support 213 */ 214 mtd = nand_to_mtd(&nand_chip); 215 nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = 216 (void __iomem *)CFG_SYS_NAND_BASE; 217 board_nand_init(&nand_chip); 218 219#ifdef CONFIG_SPL_NAND_SOFTECC 220 if (nand_chip.ecc.mode == NAND_ECC_SOFT) { 221 nand_chip.ecc.calculate = nand_calculate_ecc; 222 nand_chip.ecc.correct = nand_correct_data; 223 } 224#endif 225 226 if (nand_chip.select_chip) 227 nand_chip.select_chip(mtd, 0); 228} 229 230unsigned int nand_page_size(void) 231{ 232 return nand_to_mtd(&nand_chip)->writesize; 233} 234 235/* Unselect after operation */ 236void nand_deselect(void) 237{ 238 if (nand_chip.select_chip) 239 nand_chip.select_chip(mtd, -1); 240} 241 242#include "nand_spl_loaders.c" 243