1/* 2 * Overview: 3 * This is the generic MTD driver for NAND flash devices. It should be 4 * capable of working with almost all NAND chips currently available. 5 * 6 * Additional technical information is available on 7 * http://www.linux-mtd.infradead.org/doc/nand.html 8 * 9 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com) 10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de) 11 * 12 * Credits: 13 * David Woodhouse for adding multichip support 14 * 15 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the 16 * rework for 2K page size chips 17 * 18 * TODO: 19 * Enable cached programming for 2k page size chips 20 * Check, if mtd->ecctype should be set to MTD_ECC_HW 21 * if we have HW ECC support. 22 * BBT table is not serialized, has to be fixed 23 * 24 * This program is free software; you can redistribute it and/or modify 25 * it under the terms of the GNU General Public License version 2 as 26 * published by the Free Software Foundation. 27 * 28 */ 29 30#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 31#include <common.h> 32#include <log.h> 33#include <malloc.h> 34#include <watchdog.h> 35#include <dm/devres.h> 36#include <linux/bitops.h> 37#include <linux/bug.h> 38#include <linux/delay.h> 39#include <linux/err.h> 40#include <linux/compat.h> 41#include <linux/mtd/mtd.h> 42#include <linux/mtd/rawnand.h> 43#include <linux/mtd/nand_ecc.h> 44#include <linux/mtd/nand_bch.h> 45#ifdef CONFIG_MTD_PARTITIONS 46#include <linux/mtd/partitions.h> 47#endif 48#include <asm/io.h> 49#include <linux/errno.h> 50 51/* Define default oob placement schemes for large and small page devices */ 52#ifndef CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT 53static struct nand_ecclayout nand_oob_8 = { 54 .eccbytes = 3, 55 .eccpos = {0, 1, 2}, 56 .oobfree = { 57 {.offset = 3, 58 .length = 2}, 59 {.offset = 6, 60 .length = 2} } 61}; 62 63static struct nand_ecclayout nand_oob_16 = { 64 .eccbytes = 6, 65 .eccpos = {0, 1, 2, 3, 6, 7}, 66 .oobfree = { 67 {.offset = 8, 68 . length = 8} } 69}; 70 71static struct nand_ecclayout nand_oob_64 = { 72 .eccbytes = 24, 73 .eccpos = { 74 40, 41, 42, 43, 44, 45, 46, 47, 75 48, 49, 50, 51, 52, 53, 54, 55, 76 56, 57, 58, 59, 60, 61, 62, 63}, 77 .oobfree = { 78 {.offset = 2, 79 .length = 38} } 80}; 81 82static struct nand_ecclayout nand_oob_128 = { 83 .eccbytes = 48, 84 .eccpos = { 85 80, 81, 82, 83, 84, 85, 86, 87, 86 88, 89, 90, 91, 92, 93, 94, 95, 87 96, 97, 98, 99, 100, 101, 102, 103, 88 104, 105, 106, 107, 108, 109, 110, 111, 89 112, 113, 114, 115, 116, 117, 118, 119, 90 120, 121, 122, 123, 124, 125, 126, 127}, 91 .oobfree = { 92 {.offset = 2, 93 .length = 78} } 94}; 95#endif 96 97static int nand_get_device(struct mtd_info *mtd, int new_state); 98 99static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, 100 struct mtd_oob_ops *ops); 101 102/* 103 * For devices which display every fart in the system on a separate LED. Is 104 * compiled away when LED support is disabled. 105 */ 106DEFINE_LED_TRIGGER(nand_led_trigger); 107 108static int check_offs_len(struct mtd_info *mtd, 109 loff_t ofs, uint64_t len) 110{ 111 struct nand_chip *chip = mtd_to_nand(mtd); 112 int ret = 0; 113 114 /* Start address must align on block boundary */ 115 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) { 116 pr_debug("%s: unaligned address\n", __func__); 117 ret = -EINVAL; 118 } 119 120 /* Length must align on block boundary */ 121 if (len & ((1ULL << chip->phys_erase_shift) - 1)) { 122 pr_debug("%s: length not block aligned\n", __func__); 123 ret = -EINVAL; 124 } 125 126 return ret; 127} 128 129/** 130 * nand_release_device - [GENERIC] release chip 131 * @mtd: MTD device structure 132 * 133 * Release chip lock and wake up anyone waiting on the device. 134 */ 135static void nand_release_device(struct mtd_info *mtd) 136{ 137 struct nand_chip *chip = mtd_to_nand(mtd); 138 139 /* De-select the NAND device */ 140 chip->select_chip(mtd, -1); 141} 142 143/** 144 * nand_read_byte - [DEFAULT] read one byte from the chip 145 * @mtd: MTD device structure 146 * 147 * Default read function for 8bit buswidth 148 */ 149uint8_t nand_read_byte(struct mtd_info *mtd) 150{ 151 struct nand_chip *chip = mtd_to_nand(mtd); 152 return readb(chip->IO_ADDR_R); 153} 154 155/** 156 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip 157 * @mtd: MTD device structure 158 * 159 * Default read function for 16bit buswidth with endianness conversion. 160 * 161 */ 162static uint8_t nand_read_byte16(struct mtd_info *mtd) 163{ 164 struct nand_chip *chip = mtd_to_nand(mtd); 165 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R)); 166} 167 168/** 169 * nand_read_word - [DEFAULT] read one word from the chip 170 * @mtd: MTD device structure 171 * 172 * Default read function for 16bit buswidth without endianness conversion. 173 */ 174static u16 nand_read_word(struct mtd_info *mtd) 175{ 176 struct nand_chip *chip = mtd_to_nand(mtd); 177 return readw(chip->IO_ADDR_R); 178} 179 180/** 181 * nand_select_chip - [DEFAULT] control CE line 182 * @mtd: MTD device structure 183 * @chipnr: chipnumber to select, -1 for deselect 184 * 185 * Default select function for 1 chip devices. 186 */ 187static void nand_select_chip(struct mtd_info *mtd, int chipnr) 188{ 189 struct nand_chip *chip = mtd_to_nand(mtd); 190 191 switch (chipnr) { 192 case -1: 193 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); 194 break; 195 case 0: 196 break; 197 198 default: 199 BUG(); 200 } 201} 202 203/** 204 * nand_write_byte - [DEFAULT] write single byte to chip 205 * @mtd: MTD device structure 206 * @byte: value to write 207 * 208 * Default function to write a byte to I/O[7:0] 209 */ 210static void nand_write_byte(struct mtd_info *mtd, uint8_t byte) 211{ 212 struct nand_chip *chip = mtd_to_nand(mtd); 213 214 chip->write_buf(mtd, &byte, 1); 215} 216 217/** 218 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16 219 * @mtd: MTD device structure 220 * @byte: value to write 221 * 222 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip. 223 */ 224static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte) 225{ 226 struct nand_chip *chip = mtd_to_nand(mtd); 227 uint16_t word = byte; 228 229 /* 230 * It's not entirely clear what should happen to I/O[15:8] when writing 231 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads: 232 * 233 * When the host supports a 16-bit bus width, only data is 234 * transferred at the 16-bit width. All address and command line 235 * transfers shall use only the lower 8-bits of the data bus. During 236 * command transfers, the host may place any value on the upper 237 * 8-bits of the data bus. During address transfers, the host shall 238 * set the upper 8-bits of the data bus to 00h. 239 * 240 * One user of the write_byte callback is nand_onfi_set_features. The 241 * four parameters are specified to be written to I/O[7:0], but this is 242 * neither an address nor a command transfer. Let's assume a 0 on the 243 * upper I/O lines is OK. 244 */ 245 chip->write_buf(mtd, (uint8_t *)&word, 2); 246} 247 248/** 249 * nand_write_buf - [DEFAULT] write buffer to chip 250 * @mtd: MTD device structure 251 * @buf: data buffer 252 * @len: number of bytes to write 253 * 254 * Default write function for 8bit buswidth. 255 */ 256void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) 257{ 258 struct nand_chip *chip = mtd_to_nand(mtd); 259 260 iowrite8_rep(chip->IO_ADDR_W, buf, len); 261} 262 263/** 264 * nand_read_buf - [DEFAULT] read chip data into buffer 265 * @mtd: MTD device structure 266 * @buf: buffer to store date 267 * @len: number of bytes to read 268 * 269 * Default read function for 8bit buswidth. 270 */ 271void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) 272{ 273 struct nand_chip *chip = mtd_to_nand(mtd); 274 275 ioread8_rep(chip->IO_ADDR_R, buf, len); 276} 277 278/** 279 * nand_write_buf16 - [DEFAULT] write buffer to chip 280 * @mtd: MTD device structure 281 * @buf: data buffer 282 * @len: number of bytes to write 283 * 284 * Default write function for 16bit buswidth. 285 */ 286void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len) 287{ 288 struct nand_chip *chip = mtd_to_nand(mtd); 289 u16 *p = (u16 *) buf; 290 291 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1); 292} 293 294/** 295 * nand_read_buf16 - [DEFAULT] read chip data into buffer 296 * @mtd: MTD device structure 297 * @buf: buffer to store date 298 * @len: number of bytes to read 299 * 300 * Default read function for 16bit buswidth. 301 */ 302void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) 303{ 304 struct nand_chip *chip = mtd_to_nand(mtd); 305 u16 *p = (u16 *) buf; 306 307 ioread16_rep(chip->IO_ADDR_R, p, len >> 1); 308} 309 310/** 311 * nand_block_bad - [DEFAULT] Read bad block marker from the chip 312 * @mtd: MTD device structure 313 * @ofs: offset from device start 314 * 315 * Check, if the block is bad. 316 */ 317static int nand_block_bad(struct mtd_info *mtd, loff_t ofs) 318{ 319 int page, res = 0, i = 0; 320 struct nand_chip *chip = mtd_to_nand(mtd); 321 u16 bad; 322 323 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) 324 ofs += mtd->erasesize - mtd->writesize; 325 326 page = (int)(ofs >> chip->page_shift) & chip->pagemask; 327 328 do { 329 if (chip->options & NAND_BUSWIDTH_16) { 330 chip->cmdfunc(mtd, NAND_CMD_READOOB, 331 chip->badblockpos & 0xFE, page); 332 bad = cpu_to_le16(chip->read_word(mtd)); 333 if (chip->badblockpos & 0x1) 334 bad >>= 8; 335 else 336 bad &= 0xFF; 337 } else { 338 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, 339 page); 340 bad = chip->read_byte(mtd); 341 } 342 343 if (likely(chip->badblockbits == 8)) 344 res = bad != 0xFF; 345 else 346 res = hweight8(bad) < chip->badblockbits; 347 ofs += mtd->writesize; 348 page = (int)(ofs >> chip->page_shift) & chip->pagemask; 349 i++; 350 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE)); 351 352 return res; 353} 354 355/** 356 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker 357 * @mtd: MTD device structure 358 * @ofs: offset from device start 359 * 360 * This is the default implementation, which can be overridden by a hardware 361 * specific driver. It provides the details for writing a bad block marker to a 362 * block. 363 */ 364static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) 365{ 366 struct nand_chip *chip = mtd_to_nand(mtd); 367 struct mtd_oob_ops ops; 368 uint8_t buf[2] = { 0, 0 }; 369 int ret = 0, res, i = 0; 370 371 memset(&ops, 0, sizeof(ops)); 372 ops.oobbuf = buf; 373 ops.ooboffs = chip->badblockpos; 374 if (chip->options & NAND_BUSWIDTH_16) { 375 ops.ooboffs &= ~0x01; 376 ops.len = ops.ooblen = 2; 377 } else { 378 ops.len = ops.ooblen = 1; 379 } 380 ops.mode = MTD_OPS_PLACE_OOB; 381 382 /* Write to first/last page(s) if necessary */ 383 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE) 384 ofs += mtd->erasesize - mtd->writesize; 385 do { 386 res = nand_do_write_oob(mtd, ofs, &ops); 387 if (!ret) 388 ret = res; 389 390 i++; 391 ofs += mtd->writesize; 392 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2); 393 394 return ret; 395} 396 397/** 398 * nand_block_markbad_lowlevel - mark a block bad 399 * @mtd: MTD device structure 400 * @ofs: offset from device start 401 * 402 * This function performs the generic NAND bad block marking steps (i.e., bad 403 * block table(s) and/or marker(s)). We only allow the hardware driver to 404 * specify how to write bad block markers to OOB (chip->block_markbad). 405 * 406 * We try operations in the following order: 407 * (1) erase the affected block, to allow OOB marker to be written cleanly 408 * (2) write bad block marker to OOB area of affected block (unless flag 409 * NAND_BBT_NO_OOB_BBM is present) 410 * (3) update the BBT 411 * Note that we retain the first error encountered in (2) or (3), finish the 412 * procedures, and dump the error in the end. 413*/ 414static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs) 415{ 416 struct nand_chip *chip = mtd_to_nand(mtd); 417 int ret = 0; 418#ifndef CONFIG_SPL_BUILD 419 int res; 420#endif 421 422 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) { 423 struct erase_info einfo; 424 425 /* Attempt erase before marking OOB */ 426 memset(&einfo, 0, sizeof(einfo)); 427 einfo.mtd = mtd; 428 einfo.addr = ofs; 429 einfo.len = 1ULL << chip->phys_erase_shift; 430 nand_erase_nand(mtd, &einfo, 0); 431 432 /* Write bad block marker to OOB */ 433 nand_get_device(mtd, FL_WRITING); 434 ret = chip->block_markbad(mtd, ofs); 435 nand_release_device(mtd); 436 } 437 438#ifndef CONFIG_SPL_BUILD 439 /* Mark block bad in BBT */ 440 if (chip->bbt) { 441 res = nand_markbad_bbt(mtd, ofs); 442 if (!ret) 443 ret = res; 444 } 445#endif 446 447 if (!ret) 448 mtd->ecc_stats.badblocks++; 449 450 return ret; 451} 452 453/** 454 * nand_check_wp - [GENERIC] check if the chip is write protected 455 * @mtd: MTD device structure 456 * 457 * Check, if the device is write protected. The function expects, that the 458 * device is already selected. 459 */ 460static int nand_check_wp(struct mtd_info *mtd) 461{ 462 struct nand_chip *chip = mtd_to_nand(mtd); 463 u8 status; 464 int ret; 465 466 /* Broken xD cards report WP despite being writable */ 467 if (chip->options & NAND_BROKEN_XD) 468 return 0; 469 470 /* Check the WP bit */ 471 ret = nand_status_op(chip, &status); 472 if (ret) 473 return ret; 474 475 return status & NAND_STATUS_WP ? 0 : 1; 476} 477 478/** 479 * nand_block_isreserved - [GENERIC] Check if a block is marked reserved. 480 * @mtd: MTD device structure 481 * @ofs: offset from device start 482 * 483 * Check if the block is marked as reserved. 484 */ 485static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs) 486{ 487 struct nand_chip *chip = mtd_to_nand(mtd); 488 489 if (!chip->bbt) 490 return 0; 491 /* Return info from the table */ 492#ifndef CONFIG_SPL_BUILD 493 return nand_isreserved_bbt(mtd, ofs); 494#else 495 return 0; 496#endif 497} 498 499/** 500 * nand_block_checkbad - [GENERIC] Check if a block is marked bad 501 * @mtd: MTD device structure 502 * @ofs: offset from device start 503 * @allowbbt: 1, if its allowed to access the bbt area 504 * 505 * Check, if the block is bad. Either by reading the bad block table or 506 * calling of the scan function. 507 */ 508static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt) 509{ 510 struct nand_chip *chip = mtd_to_nand(mtd); 511 512 if (!(chip->options & NAND_SKIP_BBTSCAN) && 513 !(chip->options & NAND_BBT_SCANNED)) { 514 chip->options |= NAND_BBT_SCANNED; 515 chip->scan_bbt(mtd); 516 } 517 518 if (!chip->bbt) 519 return chip->block_bad(mtd, ofs); 520 521 /* Return info from the table */ 522#ifndef CONFIG_SPL_BUILD 523 return nand_isbad_bbt(mtd, ofs, allowbbt); 524#else 525 return 0; 526#endif 527} 528 529/** 530 * nand_wait_ready - [GENERIC] Wait for the ready pin after commands. 531 * @mtd: MTD device structure 532 * 533 * Wait for the ready pin after a command, and warn if a timeout occurs. 534 */ 535void nand_wait_ready(struct mtd_info *mtd) 536{ 537 struct nand_chip *chip = mtd_to_nand(mtd); 538 u32 timeo = (CONFIG_SYS_HZ * 400) / 1000; 539 u32 time_start; 540 541 time_start = get_timer(0); 542 /* Wait until command is processed or timeout occurs */ 543 while (get_timer(time_start) < timeo) { 544 if (chip->dev_ready) 545 if (chip->dev_ready(mtd)) 546 break; 547 } 548 549 if (!chip->dev_ready(mtd)) 550 pr_warn("timeout while waiting for chip to become ready\n"); 551} 552EXPORT_SYMBOL_GPL(nand_wait_ready); 553 554/** 555 * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands. 556 * @mtd: MTD device structure 557 * @timeo: Timeout in ms 558 * 559 * Wait for status ready (i.e. command done) or timeout. 560 */ 561static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo) 562{ 563 register struct nand_chip *chip = mtd_to_nand(mtd); 564 u32 time_start; 565 int ret; 566 567 timeo = (CONFIG_SYS_HZ * timeo) / 1000; 568 time_start = get_timer(0); 569 while (get_timer(time_start) < timeo) { 570 u8 status; 571 572 ret = nand_read_data_op(chip, &status, sizeof(status), true); 573 if (ret) 574 return; 575 576 if (status & NAND_STATUS_READY) 577 break; 578 schedule(); 579 } 580}; 581 582/** 583 * nand_command - [DEFAULT] Send command to NAND device 584 * @mtd: MTD device structure 585 * @command: the command to be sent 586 * @column: the column address for this command, -1 if none 587 * @page_addr: the page address for this command, -1 if none 588 * 589 * Send command to NAND device. This function is used for small page devices 590 * (512 Bytes per page). 591 */ 592static void nand_command(struct mtd_info *mtd, unsigned int command, 593 int column, int page_addr) 594{ 595 register struct nand_chip *chip = mtd_to_nand(mtd); 596 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE; 597 598 /* Write out the command to the device */ 599 if (command == NAND_CMD_SEQIN) { 600 int readcmd; 601 602 if (column >= mtd->writesize) { 603 /* OOB area */ 604 column -= mtd->writesize; 605 readcmd = NAND_CMD_READOOB; 606 } else if (column < 256) { 607 /* First 256 bytes --> READ0 */ 608 readcmd = NAND_CMD_READ0; 609 } else { 610 column -= 256; 611 readcmd = NAND_CMD_READ1; 612 } 613 chip->cmd_ctrl(mtd, readcmd, ctrl); 614 ctrl &= ~NAND_CTRL_CHANGE; 615 } 616 chip->cmd_ctrl(mtd, command, ctrl); 617 618 /* Address cycle, when necessary */ 619 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE; 620 /* Serially input address */ 621 if (column != -1) { 622 /* Adjust columns for 16 bit buswidth */ 623 if (chip->options & NAND_BUSWIDTH_16 && 624 !nand_opcode_8bits(command)) 625 column >>= 1; 626 chip->cmd_ctrl(mtd, column, ctrl); 627 ctrl &= ~NAND_CTRL_CHANGE; 628 } 629 if (page_addr != -1) { 630 chip->cmd_ctrl(mtd, page_addr, ctrl); 631 ctrl &= ~NAND_CTRL_CHANGE; 632 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl); 633 if (chip->options & NAND_ROW_ADDR_3) 634 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl); 635 } 636 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); 637 638 /* 639 * Program and erase have their own busy handlers status and sequential 640 * in needs no delay 641 */ 642 switch (command) { 643 644 case NAND_CMD_PAGEPROG: 645 case NAND_CMD_ERASE1: 646 case NAND_CMD_ERASE2: 647 case NAND_CMD_SEQIN: 648 case NAND_CMD_STATUS: 649 case NAND_CMD_READID: 650 case NAND_CMD_SET_FEATURES: 651 return; 652 653 case NAND_CMD_RESET: 654 if (chip->dev_ready) 655 break; 656 udelay(chip->chip_delay); 657 chip->cmd_ctrl(mtd, NAND_CMD_STATUS, 658 NAND_CTRL_CLE | NAND_CTRL_CHANGE); 659 chip->cmd_ctrl(mtd, 660 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); 661 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */ 662 nand_wait_status_ready(mtd, 250); 663 return; 664 665 /* This applies to read commands */ 666 default: 667 /* 668 * If we don't have access to the busy pin, we apply the given 669 * command delay 670 */ 671 if (!chip->dev_ready) { 672 udelay(chip->chip_delay); 673 return; 674 } 675 } 676 /* 677 * Apply this short delay always to ensure that we do wait tWB in 678 * any case on any machine. 679 */ 680 ndelay(100); 681 682 nand_wait_ready(mtd); 683} 684 685/** 686 * nand_command_lp - [DEFAULT] Send command to NAND large page device 687 * @mtd: MTD device structure 688 * @command: the command to be sent 689 * @column: the column address for this command, -1 if none 690 * @page_addr: the page address for this command, -1 if none 691 * 692 * Send command to NAND device. This is the version for the new large page 693 * devices. We don't have the separate regions as we have in the small page 694 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible. 695 */ 696static void nand_command_lp(struct mtd_info *mtd, unsigned int command, 697 int column, int page_addr) 698{ 699 register struct nand_chip *chip = mtd_to_nand(mtd); 700 701 /* Emulate NAND_CMD_READOOB */ 702 if (command == NAND_CMD_READOOB) { 703 column += mtd->writesize; 704 command = NAND_CMD_READ0; 705 } 706 707 /* Command latch cycle */ 708 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); 709 710 if (column != -1 || page_addr != -1) { 711 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE; 712 713 /* Serially input address */ 714 if (column != -1) { 715 /* Adjust columns for 16 bit buswidth */ 716 if (chip->options & NAND_BUSWIDTH_16 && 717 !nand_opcode_8bits(command)) 718 column >>= 1; 719 chip->cmd_ctrl(mtd, column, ctrl); 720 ctrl &= ~NAND_CTRL_CHANGE; 721 chip->cmd_ctrl(mtd, column >> 8, ctrl); 722 } 723 if (page_addr != -1) { 724 chip->cmd_ctrl(mtd, page_addr, ctrl); 725 chip->cmd_ctrl(mtd, page_addr >> 8, 726 NAND_NCE | NAND_ALE); 727 if (chip->options & NAND_ROW_ADDR_3) 728 chip->cmd_ctrl(mtd, page_addr >> 16, 729 NAND_NCE | NAND_ALE); 730 } 731 } 732 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); 733 734 /* 735 * Program and erase have their own busy handlers status, sequential 736 * in and status need no delay. 737 */ 738 switch (command) { 739 740 case NAND_CMD_CACHEDPROG: 741 case NAND_CMD_PAGEPROG: 742 case NAND_CMD_ERASE1: 743 case NAND_CMD_ERASE2: 744 case NAND_CMD_SEQIN: 745 case NAND_CMD_RNDIN: 746 case NAND_CMD_STATUS: 747 case NAND_CMD_READID: 748 case NAND_CMD_SET_FEATURES: 749 return; 750 751 case NAND_CMD_RESET: 752 if (chip->dev_ready) 753 break; 754 udelay(chip->chip_delay); 755 chip->cmd_ctrl(mtd, NAND_CMD_STATUS, 756 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); 757 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 758 NAND_NCE | NAND_CTRL_CHANGE); 759 /* EZ-NAND can take upto 250ms as per ONFi v4.0 */ 760 nand_wait_status_ready(mtd, 250); 761 return; 762 763 case NAND_CMD_RNDOUT: 764 /* No ready / busy check necessary */ 765 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, 766 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); 767 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 768 NAND_NCE | NAND_CTRL_CHANGE); 769 return; 770 771 case NAND_CMD_READ0: 772 chip->cmd_ctrl(mtd, NAND_CMD_READSTART, 773 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); 774 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 775 NAND_NCE | NAND_CTRL_CHANGE); 776 777 /* This applies to read commands */ 778 default: 779 /* 780 * If we don't have access to the busy pin, we apply the given 781 * command delay. 782 */ 783 if (!chip->dev_ready) { 784 udelay(chip->chip_delay); 785 return; 786 } 787 } 788 789 /* 790 * Apply this short delay always to ensure that we do wait tWB in 791 * any case on any machine. 792 */ 793 ndelay(100); 794 795 nand_wait_ready(mtd); 796} 797 798/** 799 * panic_nand_get_device - [GENERIC] Get chip for selected access 800 * @chip: the nand chip descriptor 801 * @mtd: MTD device structure 802 * @new_state: the state which is requested 803 * 804 * Used when in panic, no locks are taken. 805 */ 806static void panic_nand_get_device(struct nand_chip *chip, 807 struct mtd_info *mtd, int new_state) 808{ 809 /* Hardware controller shared among independent devices */ 810 chip->controller->active = chip; 811 chip->state = new_state; 812} 813 814/** 815 * nand_get_device - [GENERIC] Get chip for selected access 816 * @mtd: MTD device structure 817 * @new_state: the state which is requested 818 * 819 * Get the device and lock it for exclusive access 820 */ 821static int 822nand_get_device(struct mtd_info *mtd, int new_state) 823{ 824 struct nand_chip *chip = mtd_to_nand(mtd); 825 chip->state = new_state; 826 return 0; 827} 828 829/** 830 * panic_nand_wait - [GENERIC] wait until the command is done 831 * @mtd: MTD device structure 832 * @chip: NAND chip structure 833 * @timeo: timeout 834 * 835 * Wait for command done. This is a helper function for nand_wait used when 836 * we are in interrupt context. May happen when in panic and trying to write 837 * an oops through mtdoops. 838 */ 839static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip, 840 unsigned long timeo) 841{ 842 int i; 843 for (i = 0; i < timeo; i++) { 844 if (chip->dev_ready) { 845 if (chip->dev_ready(mtd)) 846 break; 847 } else { 848 int ret; 849 u8 status; 850 851 ret = nand_read_data_op(chip, &status, sizeof(status), 852 true); 853 if (ret) 854 return; 855 856 if (status & NAND_STATUS_READY) 857 break; 858 } 859 mdelay(1); 860 } 861} 862 863/** 864 * nand_wait - [DEFAULT] wait until the command is done 865 * @mtd: MTD device structure 866 * @chip: NAND chip structure 867 * 868 * Wait for command done. This applies to erase and program only. 869 */ 870static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) 871{ 872 unsigned long timeo = 400; 873 u8 status; 874 int ret; 875 876 led_trigger_event(nand_led_trigger, LED_FULL); 877 878 /* 879 * Apply this short delay always to ensure that we do wait tWB in any 880 * case on any machine. 881 */ 882 ndelay(100); 883 884 ret = nand_status_op(chip, NULL); 885 if (ret) 886 return ret; 887 888 u32 timer = (CONFIG_SYS_HZ * timeo) / 1000; 889 u32 time_start; 890 891 time_start = get_timer(0); 892 while (get_timer(time_start) < timer) { 893 if (chip->dev_ready) { 894 if (chip->dev_ready(mtd)) 895 break; 896 } else { 897 ret = nand_read_data_op(chip, &status, 898 sizeof(status), true); 899 if (ret) 900 return ret; 901 902 if (status & NAND_STATUS_READY) 903 break; 904 } 905 } 906 led_trigger_event(nand_led_trigger, LED_OFF); 907 908 ret = nand_read_data_op(chip, &status, sizeof(status), true); 909 if (ret) 910 return ret; 911 912 /* This can happen if in case of timeout or buggy dev_ready */ 913 WARN_ON(!(status & NAND_STATUS_READY)); 914 return status; 915} 916 917/** 918 * nand_reset_data_interface - Reset data interface and timings 919 * @chip: The NAND chip 920 * @chipnr: Internal die id 921 * 922 * Reset the Data interface and timings to ONFI mode 0. 923 * 924 * Returns 0 for success or negative error code otherwise. 925 */ 926static int nand_reset_data_interface(struct nand_chip *chip, int chipnr) 927{ 928 struct mtd_info *mtd = nand_to_mtd(chip); 929 const struct nand_data_interface *conf; 930 int ret; 931 932 if (!chip->setup_data_interface) 933 return 0; 934 935 /* 936 * The ONFI specification says: 937 * " 938 * To transition from NV-DDR or NV-DDR2 to the SDR data 939 * interface, the host shall use the Reset (FFh) command 940 * using SDR timing mode 0. A device in any timing mode is 941 * required to recognize Reset (FFh) command issued in SDR 942 * timing mode 0. 943 * " 944 * 945 * Configure the data interface in SDR mode and set the 946 * timings to timing mode 0. 947 */ 948 949 conf = nand_get_default_data_interface(); 950 ret = chip->setup_data_interface(mtd, chipnr, conf); 951 if (ret) 952 pr_err("Failed to configure data interface to SDR timing mode 0\n"); 953 954 return ret; 955} 956 957static int nand_onfi_set_timings(struct mtd_info *mtd, struct nand_chip *chip) 958{ 959 if (!chip->onfi_version || 960 !(le16_to_cpu(chip->onfi_params.opt_cmd) 961 & ONFI_OPT_CMD_SET_GET_FEATURES)) 962 return 0; 963 964 u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = { 965 chip->onfi_timing_mode_default, 966 }; 967 968 return chip->onfi_set_features(mtd, chip, 969 ONFI_FEATURE_ADDR_TIMING_MODE, 970 tmode_param); 971} 972 973/** 974 * nand_setup_data_interface - Setup the best data interface and timings 975 * @chip: The NAND chip 976 * @chipnr: Internal die id 977 * 978 * Find and configure the best data interface and NAND timings supported by 979 * the chip and the driver. 980 * First tries to retrieve supported timing modes from ONFI information, 981 * and if the NAND chip does not support ONFI, relies on the 982 * ->onfi_timing_mode_default specified in the nand_ids table. 983 * 984 * Returns 0 for success or negative error code otherwise. 985 */ 986static int nand_setup_data_interface(struct nand_chip *chip, int chipnr) 987{ 988 struct mtd_info *mtd = nand_to_mtd(chip); 989 int ret; 990 991 if (!chip->setup_data_interface || !chip->data_interface) 992 return 0; 993 994 /* 995 * Ensure the timing mode has been changed on the chip side 996 * before changing timings on the controller side. 997 */ 998 ret = nand_onfi_set_timings(mtd, chip); 999 if (ret) 1000 goto err; 1001 1002 ret = chip->setup_data_interface(mtd, chipnr, chip->data_interface); 1003err: 1004 return ret; 1005} 1006 1007/** 1008 * nand_init_data_interface - find the best data interface and timings 1009 * @chip: The NAND chip 1010 * 1011 * Find the best data interface and NAND timings supported by the chip 1012 * and the driver. 1013 * First tries to retrieve supported timing modes from ONFI information, 1014 * and if the NAND chip does not support ONFI, relies on the 1015 * ->onfi_timing_mode_default specified in the nand_ids table. After this 1016 * function nand_chip->data_interface is initialized with the best timing mode 1017 * available. 1018 * 1019 * Returns 0 for success or negative error code otherwise. 1020 */ 1021static int nand_init_data_interface(struct nand_chip *chip) 1022{ 1023 struct mtd_info *mtd = nand_to_mtd(chip); 1024 int modes, mode, ret; 1025 1026 if (!chip->setup_data_interface) 1027 return 0; 1028 1029 /* 1030 * First try to identify the best timings from ONFI parameters and 1031 * if the NAND does not support ONFI, fallback to the default ONFI 1032 * timing mode. 1033 */ 1034 modes = onfi_get_async_timing_mode(chip); 1035 if (modes == ONFI_TIMING_MODE_UNKNOWN) { 1036 if (!chip->onfi_timing_mode_default) 1037 return 0; 1038 1039 modes = GENMASK(chip->onfi_timing_mode_default, 0); 1040 } 1041 1042 chip->data_interface = kzalloc(sizeof(*chip->data_interface), 1043 GFP_KERNEL); 1044 if (!chip->data_interface) 1045 return -ENOMEM; 1046 1047 for (mode = fls(modes) - 1; mode >= 0; mode--) { 1048 ret = onfi_init_data_interface(chip, chip->data_interface, 1049 NAND_SDR_IFACE, mode); 1050 if (ret) 1051 continue; 1052 1053 /* Pass -1 to only */ 1054 ret = chip->setup_data_interface(mtd, 1055 NAND_DATA_IFACE_CHECK_ONLY, 1056 chip->data_interface); 1057 if (!ret) { 1058 chip->onfi_timing_mode_default = mode; 1059 break; 1060 } 1061 } 1062 1063 return 0; 1064} 1065 1066static void __maybe_unused nand_release_data_interface(struct nand_chip *chip) 1067{ 1068 kfree(chip->data_interface); 1069} 1070 1071/** 1072 * nand_read_page_op - Do a READ PAGE operation 1073 * @chip: The NAND chip 1074 * @page: page to read 1075 * @offset_in_page: offset within the page 1076 * @buf: buffer used to store the data 1077 * @len: length of the buffer 1078 * 1079 * This function issues a READ PAGE operation. 1080 * This function does not select/unselect the CS line. 1081 * 1082 * Returns 0 on success, a negative error code otherwise. 1083 */ 1084int nand_read_page_op(struct nand_chip *chip, unsigned int page, 1085 unsigned int offset_in_page, void *buf, unsigned int len) 1086{ 1087 struct mtd_info *mtd = nand_to_mtd(chip); 1088 1089 if (len && !buf) 1090 return -EINVAL; 1091 1092 if (offset_in_page + len > mtd->writesize + mtd->oobsize) 1093 return -EINVAL; 1094 1095 chip->cmdfunc(mtd, NAND_CMD_READ0, offset_in_page, page); 1096 if (len) 1097 chip->read_buf(mtd, buf, len); 1098 1099 return 0; 1100} 1101EXPORT_SYMBOL_GPL(nand_read_page_op); 1102 1103/** 1104 * nand_read_param_page_op - Do a READ PARAMETER PAGE operation 1105 * @chip: The NAND chip 1106 * @page: parameter page to read 1107 * @buf: buffer used to store the data 1108 * @len: length of the buffer 1109 * 1110 * This function issues a READ PARAMETER PAGE operation. 1111 * This function does not select/unselect the CS line. 1112 * 1113 * Returns 0 on success, a negative error code otherwise. 1114 */ 1115static int nand_read_param_page_op(struct nand_chip *chip, u8 page, void *buf, 1116 unsigned int len) 1117{ 1118 struct mtd_info *mtd = nand_to_mtd(chip); 1119 unsigned int i; 1120 u8 *p = buf; 1121 1122 if (len && !buf) 1123 return -EINVAL; 1124 1125 chip->cmdfunc(mtd, NAND_CMD_PARAM, page, -1); 1126 for (i = 0; i < len; i++) 1127 p[i] = chip->read_byte(mtd); 1128 1129 return 0; 1130} 1131 1132/** 1133 * nand_change_read_column_op - Do a CHANGE READ COLUMN operation 1134 * @chip: The NAND chip 1135 * @offset_in_page: offset within the page 1136 * @buf: buffer used to store the data 1137 * @len: length of the buffer 1138 * @force_8bit: force 8-bit bus access 1139 * 1140 * This function issues a CHANGE READ COLUMN operation. 1141 * This function does not select/unselect the CS line. 1142 * 1143 * Returns 0 on success, a negative error code otherwise. 1144 */ 1145int nand_change_read_column_op(struct nand_chip *chip, 1146 unsigned int offset_in_page, void *buf, 1147 unsigned int len, bool force_8bit) 1148{ 1149 struct mtd_info *mtd = nand_to_mtd(chip); 1150 1151 if (len && !buf) 1152 return -EINVAL; 1153 1154 if (offset_in_page + len > mtd->writesize + mtd->oobsize) 1155 return -EINVAL; 1156 1157 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset_in_page, -1); 1158 if (len) 1159 chip->read_buf(mtd, buf, len); 1160 1161 return 0; 1162} 1163EXPORT_SYMBOL_GPL(nand_change_read_column_op); 1164 1165/** 1166 * nand_read_oob_op - Do a READ OOB operation 1167 * @chip: The NAND chip 1168 * @page: page to read 1169 * @offset_in_oob: offset within the OOB area 1170 * @buf: buffer used to store the data 1171 * @len: length of the buffer 1172 * 1173 * This function issues a READ OOB operation. 1174 * This function does not select/unselect the CS line. 1175 * 1176 * Returns 0 on success, a negative error code otherwise. 1177 */ 1178int nand_read_oob_op(struct nand_chip *chip, unsigned int page, 1179 unsigned int offset_in_oob, void *buf, unsigned int len) 1180{ 1181 struct mtd_info *mtd = nand_to_mtd(chip); 1182 1183 if (len && !buf) 1184 return -EINVAL; 1185 1186 if (offset_in_oob + len > mtd->oobsize) 1187 return -EINVAL; 1188 1189 chip->cmdfunc(mtd, NAND_CMD_READOOB, offset_in_oob, page); 1190 if (len) 1191 chip->read_buf(mtd, buf, len); 1192 1193 return 0; 1194} 1195EXPORT_SYMBOL_GPL(nand_read_oob_op); 1196 1197/** 1198 * nand_prog_page_begin_op - starts a PROG PAGE operation 1199 * @chip: The NAND chip 1200 * @page: page to write 1201 * @offset_in_page: offset within the page 1202 * @buf: buffer containing the data to write to the page 1203 * @len: length of the buffer 1204 * 1205 * This function issues the first half of a PROG PAGE operation. 1206 * This function does not select/unselect the CS line. 1207 * 1208 * Returns 0 on success, a negative error code otherwise. 1209 */ 1210int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page, 1211 unsigned int offset_in_page, const void *buf, 1212 unsigned int len) 1213{ 1214 struct mtd_info *mtd = nand_to_mtd(chip); 1215 1216 if (len && !buf) 1217 return -EINVAL; 1218 1219 if (offset_in_page + len > mtd->writesize + mtd->oobsize) 1220 return -EINVAL; 1221 1222 chip->cmdfunc(mtd, NAND_CMD_SEQIN, offset_in_page, page); 1223 1224 if (buf) 1225 chip->write_buf(mtd, buf, len); 1226 1227 return 0; 1228} 1229EXPORT_SYMBOL_GPL(nand_prog_page_begin_op); 1230 1231/** 1232 * nand_prog_page_end_op - ends a PROG PAGE operation 1233 * @chip: The NAND chip 1234 * 1235 * This function issues the second half of a PROG PAGE operation. 1236 * This function does not select/unselect the CS line. 1237 * 1238 * Returns 0 on success, a negative error code otherwise. 1239 */ 1240int nand_prog_page_end_op(struct nand_chip *chip) 1241{ 1242 struct mtd_info *mtd = nand_to_mtd(chip); 1243 int status; 1244 1245 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); 1246 1247 status = chip->waitfunc(mtd, chip); 1248 if (status & NAND_STATUS_FAIL) 1249 return -EIO; 1250 1251 return 0; 1252} 1253EXPORT_SYMBOL_GPL(nand_prog_page_end_op); 1254 1255/** 1256 * nand_prog_page_op - Do a full PROG PAGE operation 1257 * @chip: The NAND chip 1258 * @page: page to write 1259 * @offset_in_page: offset within the page 1260 * @buf: buffer containing the data to write to the page 1261 * @len: length of the buffer 1262 * 1263 * This function issues a full PROG PAGE operation. 1264 * This function does not select/unselect the CS line. 1265 * 1266 * Returns 0 on success, a negative error code otherwise. 1267 */ 1268int nand_prog_page_op(struct nand_chip *chip, unsigned int page, 1269 unsigned int offset_in_page, const void *buf, 1270 unsigned int len) 1271{ 1272 struct mtd_info *mtd = nand_to_mtd(chip); 1273 int status; 1274 1275 if (!len || !buf) 1276 return -EINVAL; 1277 1278 if (offset_in_page + len > mtd->writesize + mtd->oobsize) 1279 return -EINVAL; 1280 1281 chip->cmdfunc(mtd, NAND_CMD_SEQIN, offset_in_page, page); 1282 chip->write_buf(mtd, buf, len); 1283 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); 1284 1285 status = chip->waitfunc(mtd, chip); 1286 if (status & NAND_STATUS_FAIL) 1287 return -EIO; 1288 1289 return 0; 1290} 1291EXPORT_SYMBOL_GPL(nand_prog_page_op); 1292 1293/** 1294 * nand_change_write_column_op - Do a CHANGE WRITE COLUMN operation 1295 * @chip: The NAND chip 1296 * @offset_in_page: offset within the page 1297 * @buf: buffer containing the data to send to the NAND 1298 * @len: length of the buffer 1299 * @force_8bit: force 8-bit bus access 1300 * 1301 * This function issues a CHANGE WRITE COLUMN operation. 1302 * This function does not select/unselect the CS line. 1303 * 1304 * Returns 0 on success, a negative error code otherwise. 1305 */ 1306int nand_change_write_column_op(struct nand_chip *chip, 1307 unsigned int offset_in_page, 1308 const void *buf, unsigned int len, 1309 bool force_8bit) 1310{ 1311 struct mtd_info *mtd = nand_to_mtd(chip); 1312 1313 if (len && !buf) 1314 return -EINVAL; 1315 1316 if (offset_in_page + len > mtd->writesize + mtd->oobsize) 1317 return -EINVAL; 1318 1319 chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset_in_page, -1); 1320 if (len) 1321 chip->write_buf(mtd, buf, len); 1322 1323 return 0; 1324} 1325EXPORT_SYMBOL_GPL(nand_change_write_column_op); 1326 1327/** 1328 * nand_readid_op - Do a READID operation 1329 * @chip: The NAND chip 1330 * @addr: address cycle to pass after the READID command 1331 * @buf: buffer used to store the ID 1332 * @len: length of the buffer 1333 * 1334 * This function sends a READID command and reads back the ID returned by the 1335 * NAND. 1336 * This function does not select/unselect the CS line. 1337 * 1338 * Returns 0 on success, a negative error code otherwise. 1339 */ 1340int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf, 1341 unsigned int len) 1342{ 1343 struct mtd_info *mtd = nand_to_mtd(chip); 1344 unsigned int i; 1345 u8 *id = buf; 1346 1347 if (len && !buf) 1348 return -EINVAL; 1349 1350 chip->cmdfunc(mtd, NAND_CMD_READID, addr, -1); 1351 1352 for (i = 0; i < len; i++) 1353 id[i] = chip->read_byte(mtd); 1354 1355 return 0; 1356} 1357EXPORT_SYMBOL_GPL(nand_readid_op); 1358 1359/** 1360 * nand_status_op - Do a STATUS operation 1361 * @chip: The NAND chip 1362 * @status: out variable to store the NAND status 1363 * 1364 * This function sends a STATUS command and reads back the status returned by 1365 * the NAND. 1366 * This function does not select/unselect the CS line. 1367 * 1368 * Returns 0 on success, a negative error code otherwise. 1369 */ 1370int nand_status_op(struct nand_chip *chip, u8 *status) 1371{ 1372 struct mtd_info *mtd = nand_to_mtd(chip); 1373 1374 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1); 1375 if (status) 1376 *status = chip->read_byte(mtd); 1377 1378 return 0; 1379} 1380EXPORT_SYMBOL_GPL(nand_status_op); 1381 1382/** 1383 * nand_exit_status_op - Exit a STATUS operation 1384 * @chip: The NAND chip 1385 * 1386 * This function sends a READ0 command to cancel the effect of the STATUS 1387 * command to avoid reading only the status until a new read command is sent. 1388 * 1389 * This function does not select/unselect the CS line. 1390 * 1391 * Returns 0 on success, a negative error code otherwise. 1392 */ 1393int nand_exit_status_op(struct nand_chip *chip) 1394{ 1395 struct mtd_info *mtd = nand_to_mtd(chip); 1396 1397 chip->cmdfunc(mtd, NAND_CMD_READ0, -1, -1); 1398 1399 return 0; 1400} 1401EXPORT_SYMBOL_GPL(nand_exit_status_op); 1402 1403/** 1404 * nand_erase_op - Do an erase operation 1405 * @chip: The NAND chip 1406 * @eraseblock: block to erase 1407 * 1408 * This function sends an ERASE command and waits for the NAND to be ready 1409 * before returning. 1410 * This function does not select/unselect the CS line. 1411 * 1412 * Returns 0 on success, a negative error code otherwise. 1413 */ 1414int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock) 1415{ 1416 struct mtd_info *mtd = nand_to_mtd(chip); 1417 unsigned int page = eraseblock << 1418 (chip->phys_erase_shift - chip->page_shift); 1419 int status; 1420 1421 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page); 1422 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1); 1423 1424 status = chip->waitfunc(mtd, chip); 1425 if (status < 0) 1426 return status; 1427 1428 if (status & NAND_STATUS_FAIL) 1429 return -EIO; 1430 1431 return 0; 1432} 1433EXPORT_SYMBOL_GPL(nand_erase_op); 1434 1435/** 1436 * nand_set_features_op - Do a SET FEATURES operation 1437 * @chip: The NAND chip 1438 * @feature: feature id 1439 * @data: 4 bytes of data 1440 * 1441 * This function sends a SET FEATURES command and waits for the NAND to be 1442 * ready before returning. 1443 * This function does not select/unselect the CS line. 1444 * 1445 * Returns 0 on success, a negative error code otherwise. 1446 */ 1447static int nand_set_features_op(struct nand_chip *chip, u8 feature, 1448 const void *data) 1449{ 1450 struct mtd_info *mtd = nand_to_mtd(chip); 1451 const u8 *params = data; 1452 int i, status; 1453 1454 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, feature, -1); 1455 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) 1456 chip->write_byte(mtd, params[i]); 1457 1458 status = chip->waitfunc(mtd, chip); 1459 if (status & NAND_STATUS_FAIL) 1460 return -EIO; 1461 1462 return 0; 1463} 1464 1465/** 1466 * nand_get_features_op - Do a GET FEATURES operation 1467 * @chip: The NAND chip 1468 * @feature: feature id 1469 * @data: 4 bytes of data 1470 * 1471 * This function sends a GET FEATURES command and waits for the NAND to be 1472 * ready before returning. 1473 * This function does not select/unselect the CS line. 1474 * 1475 * Returns 0 on success, a negative error code otherwise. 1476 */ 1477static int nand_get_features_op(struct nand_chip *chip, u8 feature, 1478 void *data) 1479{ 1480 struct mtd_info *mtd = nand_to_mtd(chip); 1481 u8 *params = data; 1482 int i; 1483 1484 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, feature, -1); 1485 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i) 1486 params[i] = chip->read_byte(mtd); 1487 1488 return 0; 1489} 1490 1491/** 1492 * nand_reset_op - Do a reset operation 1493 * @chip: The NAND chip 1494 * 1495 * This function sends a RESET command and waits for the NAND to be ready 1496 * before returning. 1497 * This function does not select/unselect the CS line. 1498 * 1499 * Returns 0 on success, a negative error code otherwise. 1500 */ 1501int nand_reset_op(struct nand_chip *chip) 1502{ 1503 struct mtd_info *mtd = nand_to_mtd(chip); 1504 1505 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); 1506 1507 return 0; 1508} 1509EXPORT_SYMBOL_GPL(nand_reset_op); 1510 1511/** 1512 * nand_read_data_op - Read data from the NAND 1513 * @chip: The NAND chip 1514 * @buf: buffer used to store the data 1515 * @len: length of the buffer 1516 * @force_8bit: force 8-bit bus access 1517 * 1518 * This function does a raw data read on the bus. Usually used after launching 1519 * another NAND operation like nand_read_page_op(). 1520 * This function does not select/unselect the CS line. 1521 * 1522 * Returns 0 on success, a negative error code otherwise. 1523 */ 1524int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len, 1525 bool force_8bit) 1526{ 1527 struct mtd_info *mtd = nand_to_mtd(chip); 1528 1529 if (!len || !buf) 1530 return -EINVAL; 1531 1532 if (force_8bit) { 1533 u8 *p = buf; 1534 unsigned int i; 1535 1536 for (i = 0; i < len; i++) 1537 p[i] = chip->read_byte(mtd); 1538 } else { 1539 chip->read_buf(mtd, buf, len); 1540 } 1541 1542 return 0; 1543} 1544EXPORT_SYMBOL_GPL(nand_read_data_op); 1545 1546/** 1547 * nand_write_data_op - Write data from the NAND 1548 * @chip: The NAND chip 1549 * @buf: buffer containing the data to send on the bus 1550 * @len: length of the buffer 1551 * @force_8bit: force 8-bit bus access 1552 * 1553 * This function does a raw data write on the bus. Usually used after launching 1554 * another NAND operation like nand_write_page_begin_op(). 1555 * This function does not select/unselect the CS line. 1556 * 1557 * Returns 0 on success, a negative error code otherwise. 1558 */ 1559int nand_write_data_op(struct nand_chip *chip, const void *buf, 1560 unsigned int len, bool force_8bit) 1561{ 1562 struct mtd_info *mtd = nand_to_mtd(chip); 1563 1564 if (!len || !buf) 1565 return -EINVAL; 1566 1567 if (force_8bit) { 1568 const u8 *p = buf; 1569 unsigned int i; 1570 1571 for (i = 0; i < len; i++) 1572 chip->write_byte(mtd, p[i]); 1573 } else { 1574 chip->write_buf(mtd, buf, len); 1575 } 1576 1577 return 0; 1578} 1579EXPORT_SYMBOL_GPL(nand_write_data_op); 1580 1581/** 1582 * nand_reset - Reset and initialize a NAND device 1583 * @chip: The NAND chip 1584 * @chipnr: Internal die id 1585 * 1586 * Returns 0 for success or negative error code otherwise 1587 */ 1588int nand_reset(struct nand_chip *chip, int chipnr) 1589{ 1590 struct mtd_info *mtd = nand_to_mtd(chip); 1591 int ret; 1592 1593 ret = nand_reset_data_interface(chip, chipnr); 1594 if (ret) 1595 return ret; 1596 1597 /* 1598 * The CS line has to be released before we can apply the new NAND 1599 * interface settings, hence this weird ->select_chip() dance. 1600 */ 1601 chip->select_chip(mtd, chipnr); 1602 ret = nand_reset_op(chip); 1603 chip->select_chip(mtd, -1); 1604 if (ret) 1605 return ret; 1606 1607 chip->select_chip(mtd, chipnr); 1608 ret = nand_setup_data_interface(chip, chipnr); 1609 chip->select_chip(mtd, -1); 1610 if (ret) 1611 return ret; 1612 1613 return 0; 1614} 1615 1616/** 1617 * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data 1618 * @buf: buffer to test 1619 * @len: buffer length 1620 * @bitflips_threshold: maximum number of bitflips 1621 * 1622 * Check if a buffer contains only 0xff, which means the underlying region 1623 * has been erased and is ready to be programmed. 1624 * The bitflips_threshold specify the maximum number of bitflips before 1625 * considering the region is not erased. 1626 * Note: The logic of this function has been extracted from the memweight 1627 * implementation, except that nand_check_erased_buf function exit before 1628 * testing the whole buffer if the number of bitflips exceed the 1629 * bitflips_threshold value. 1630 * 1631 * Returns a positive number of bitflips less than or equal to 1632 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the 1633 * threshold. 1634 */ 1635static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold) 1636{ 1637 const unsigned char *bitmap = buf; 1638 int bitflips = 0; 1639 int weight; 1640 1641 for (; len && ((uintptr_t)bitmap) % sizeof(long); 1642 len--, bitmap++) { 1643 weight = hweight8(*bitmap); 1644 bitflips += BITS_PER_BYTE - weight; 1645 if (unlikely(bitflips > bitflips_threshold)) 1646 return -EBADMSG; 1647 } 1648 1649 for (; len >= 4; len -= 4, bitmap += 4) { 1650 weight = hweight32(*((u32 *)bitmap)); 1651 bitflips += 32 - weight; 1652 if (unlikely(bitflips > bitflips_threshold)) 1653 return -EBADMSG; 1654 } 1655 1656 for (; len > 0; len--, bitmap++) { 1657 weight = hweight8(*bitmap); 1658 bitflips += BITS_PER_BYTE - weight; 1659 if (unlikely(bitflips > bitflips_threshold)) 1660 return -EBADMSG; 1661 } 1662 1663 return bitflips; 1664} 1665 1666/** 1667 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only 1668 * 0xff data 1669 * @data: data buffer to test 1670 * @datalen: data length 1671 * @ecc: ECC buffer 1672 * @ecclen: ECC length 1673 * @extraoob: extra OOB buffer 1674 * @extraooblen: extra OOB length 1675 * @bitflips_threshold: maximum number of bitflips 1676 * 1677 * Check if a data buffer and its associated ECC and OOB data contains only 1678 * 0xff pattern, which means the underlying region has been erased and is 1679 * ready to be programmed. 1680 * The bitflips_threshold specify the maximum number of bitflips before 1681 * considering the region as not erased. 1682 * 1683 * Note: 1684 * 1/ ECC algorithms are working on pre-defined block sizes which are usually 1685 * different from the NAND page size. When fixing bitflips, ECC engines will 1686 * report the number of errors per chunk, and the NAND core infrastructure 1687 * expect you to return the maximum number of bitflips for the whole page. 1688 * This is why you should always use this function on a single chunk and 1689 * not on the whole page. After checking each chunk you should update your 1690 * max_bitflips value accordingly. 1691 * 2/ When checking for bitflips in erased pages you should not only check 1692 * the payload data but also their associated ECC data, because a user might 1693 * have programmed almost all bits to 1 but a few. In this case, we 1694 * shouldn't consider the chunk as erased, and checking ECC bytes prevent 1695 * this case. 1696 * 3/ The extraoob argument is optional, and should be used if some of your OOB 1697 * data are protected by the ECC engine. 1698 * It could also be used if you support subpages and want to attach some 1699 * extra OOB data to an ECC chunk. 1700 * 1701 * Returns a positive number of bitflips less than or equal to 1702 * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the 1703 * threshold. In case of success, the passed buffers are filled with 0xff. 1704 */ 1705int nand_check_erased_ecc_chunk(void *data, int datalen, 1706 void *ecc, int ecclen, 1707 void *extraoob, int extraooblen, 1708 int bitflips_threshold) 1709{ 1710 int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0; 1711 1712 data_bitflips = nand_check_erased_buf(data, datalen, 1713 bitflips_threshold); 1714 if (data_bitflips < 0) 1715 return data_bitflips; 1716 1717 bitflips_threshold -= data_bitflips; 1718 1719 ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold); 1720 if (ecc_bitflips < 0) 1721 return ecc_bitflips; 1722 1723 bitflips_threshold -= ecc_bitflips; 1724 1725 extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen, 1726 bitflips_threshold); 1727 if (extraoob_bitflips < 0) 1728 return extraoob_bitflips; 1729 1730 if (data_bitflips) 1731 memset(data, 0xff, datalen); 1732 1733 if (ecc_bitflips) 1734 memset(ecc, 0xff, ecclen); 1735 1736 if (extraoob_bitflips) 1737 memset(extraoob, 0xff, extraooblen); 1738 1739 return data_bitflips + ecc_bitflips + extraoob_bitflips; 1740} 1741EXPORT_SYMBOL(nand_check_erased_ecc_chunk); 1742 1743/** 1744 * nand_read_page_raw - [INTERN] read raw page data without ecc 1745 * @mtd: mtd info structure 1746 * @chip: nand chip info structure 1747 * @buf: buffer to store read data 1748 * @oob_required: caller requires OOB data read to chip->oob_poi 1749 * @page: page number to read 1750 * 1751 * Not for syndrome calculating ECC controllers, which use a special oob layout. 1752 */ 1753static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 1754 uint8_t *buf, int oob_required, int page) 1755{ 1756 int ret; 1757 1758 ret = nand_read_data_op(chip, buf, mtd->writesize, false); 1759 if (ret) 1760 return ret; 1761 1762 if (oob_required) { 1763 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, 1764 false); 1765 if (ret) 1766 return ret; 1767 } 1768 1769 return 0; 1770} 1771 1772/** 1773 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc 1774 * @mtd: mtd info structure 1775 * @chip: nand chip info structure 1776 * @buf: buffer to store read data 1777 * @oob_required: caller requires OOB data read to chip->oob_poi 1778 * @page: page number to read 1779 * 1780 * We need a special oob layout and handling even when OOB isn't used. 1781 */ 1782static int nand_read_page_raw_syndrome(struct mtd_info *mtd, 1783 struct nand_chip *chip, uint8_t *buf, 1784 int oob_required, int page) 1785{ 1786 int eccsize = chip->ecc.size; 1787 int eccbytes = chip->ecc.bytes; 1788 uint8_t *oob = chip->oob_poi; 1789 int steps, size, ret; 1790 1791 for (steps = chip->ecc.steps; steps > 0; steps--) { 1792 ret = nand_read_data_op(chip, buf, eccsize, false); 1793 if (ret) 1794 return ret; 1795 1796 buf += eccsize; 1797 1798 if (chip->ecc.prepad) { 1799 ret = nand_read_data_op(chip, oob, chip->ecc.prepad, 1800 false); 1801 if (ret) 1802 return ret; 1803 1804 oob += chip->ecc.prepad; 1805 } 1806 1807 ret = nand_read_data_op(chip, oob, eccbytes, false); 1808 if (ret) 1809 return ret; 1810 1811 oob += eccbytes; 1812 1813 if (chip->ecc.postpad) { 1814 ret = nand_read_data_op(chip, oob, chip->ecc.postpad, 1815 false); 1816 if (ret) 1817 return ret; 1818 1819 oob += chip->ecc.postpad; 1820 } 1821 } 1822 1823 size = mtd->oobsize - (oob - chip->oob_poi); 1824 if (size) { 1825 ret = nand_read_data_op(chip, oob, size, false); 1826 if (ret) 1827 return ret; 1828 } 1829 1830 return 0; 1831} 1832 1833/** 1834 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function 1835 * @mtd: mtd info structure 1836 * @chip: nand chip info structure 1837 * @buf: buffer to store read data 1838 * @oob_required: caller requires OOB data read to chip->oob_poi 1839 * @page: page number to read 1840 */ 1841static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, 1842 uint8_t *buf, int oob_required, int page) 1843{ 1844 int i, eccsize = chip->ecc.size; 1845 int eccbytes = chip->ecc.bytes; 1846 int eccsteps = chip->ecc.steps; 1847 uint8_t *p = buf; 1848 uint8_t *ecc_calc = chip->buffers->ecccalc; 1849 uint8_t *ecc_code = chip->buffers->ecccode; 1850 uint32_t *eccpos = chip->ecc.layout->eccpos; 1851 unsigned int max_bitflips = 0; 1852 1853 chip->ecc.read_page_raw(mtd, chip, buf, 1, page); 1854 1855 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) 1856 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 1857 1858 for (i = 0; i < chip->ecc.total; i++) 1859 ecc_code[i] = chip->oob_poi[eccpos[i]]; 1860 1861 eccsteps = chip->ecc.steps; 1862 p = buf; 1863 1864 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 1865 int stat; 1866 1867 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); 1868 if (stat < 0) { 1869 mtd->ecc_stats.failed++; 1870 } else { 1871 mtd->ecc_stats.corrected += stat; 1872 max_bitflips = max_t(unsigned int, max_bitflips, stat); 1873 } 1874 } 1875 return max_bitflips; 1876} 1877 1878/** 1879 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function 1880 * @mtd: mtd info structure 1881 * @chip: nand chip info structure 1882 * @data_offs: offset of requested data within the page 1883 * @readlen: data length 1884 * @bufpoi: buffer to store read data 1885 * @page: page number to read 1886 */ 1887static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, 1888 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi, 1889 int page) 1890{ 1891 int start_step, end_step, num_steps; 1892 uint32_t *eccpos = chip->ecc.layout->eccpos; 1893 uint8_t *p; 1894 int data_col_addr, i, gaps = 0; 1895 int datafrag_len, eccfrag_len, aligned_len, aligned_pos; 1896 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1; 1897 int index; 1898 unsigned int max_bitflips = 0; 1899 int ret; 1900 1901 /* Column address within the page aligned to ECC size (256bytes) */ 1902 start_step = data_offs / chip->ecc.size; 1903 end_step = (data_offs + readlen - 1) / chip->ecc.size; 1904 num_steps = end_step - start_step + 1; 1905 index = start_step * chip->ecc.bytes; 1906 1907 /* Data size aligned to ECC ecc.size */ 1908 datafrag_len = num_steps * chip->ecc.size; 1909 eccfrag_len = num_steps * chip->ecc.bytes; 1910 1911 data_col_addr = start_step * chip->ecc.size; 1912 /* If we read not a page aligned data */ 1913 if (data_col_addr != 0) 1914 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1); 1915 1916 p = bufpoi + data_col_addr; 1917 ret = nand_read_data_op(chip, p, datafrag_len, false); 1918 if (ret) 1919 return ret; 1920 1921 /* Calculate ECC */ 1922 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) 1923 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]); 1924 1925 /* 1926 * The performance is faster if we position offsets according to 1927 * ecc.pos. Let's make sure that there are no gaps in ECC positions. 1928 */ 1929 for (i = 0; i < eccfrag_len - 1; i++) { 1930 if (eccpos[i + index] + 1 != eccpos[i + index + 1]) { 1931 gaps = 1; 1932 break; 1933 } 1934 } 1935 if (gaps) { 1936 ret = nand_change_read_column_op(chip, mtd->writesize, 1937 chip->oob_poi, mtd->oobsize, 1938 false); 1939 if (ret) 1940 return ret; 1941 } else { 1942 /* 1943 * Send the command to read the particular ECC bytes take care 1944 * about buswidth alignment in read_buf. 1945 */ 1946 aligned_pos = eccpos[index] & ~(busw - 1); 1947 aligned_len = eccfrag_len; 1948 if (eccpos[index] & (busw - 1)) 1949 aligned_len++; 1950 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1)) 1951 aligned_len++; 1952 1953 ret = nand_change_read_column_op(chip, 1954 mtd->writesize + aligned_pos, 1955 &chip->oob_poi[aligned_pos], 1956 aligned_len, false); 1957 if (ret) 1958 return ret; 1959 } 1960 1961 for (i = 0; i < eccfrag_len; i++) 1962 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]]; 1963 1964 p = bufpoi + data_col_addr; 1965 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { 1966 int stat; 1967 1968 stat = chip->ecc.correct(mtd, p, 1969 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]); 1970 if (stat == -EBADMSG && 1971 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { 1972 /* check for empty pages with bitflips */ 1973 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, 1974 &chip->buffers->ecccode[i], 1975 chip->ecc.bytes, 1976 NULL, 0, 1977 chip->ecc.strength); 1978 } 1979 1980 if (stat < 0) { 1981 mtd->ecc_stats.failed++; 1982 } else { 1983 mtd->ecc_stats.corrected += stat; 1984 max_bitflips = max_t(unsigned int, max_bitflips, stat); 1985 } 1986 } 1987 return max_bitflips; 1988} 1989 1990/** 1991 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function 1992 * @mtd: mtd info structure 1993 * @chip: nand chip info structure 1994 * @buf: buffer to store read data 1995 * @oob_required: caller requires OOB data read to chip->oob_poi 1996 * @page: page number to read 1997 * 1998 * Not for syndrome calculating ECC controllers which need a special oob layout. 1999 */ 2000static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, 2001 uint8_t *buf, int oob_required, int page) 2002{ 2003 int i, eccsize = chip->ecc.size; 2004 int eccbytes = chip->ecc.bytes; 2005 int eccsteps = chip->ecc.steps; 2006 uint8_t *p = buf; 2007 uint8_t *ecc_calc = chip->buffers->ecccalc; 2008 uint8_t *ecc_code = chip->buffers->ecccode; 2009 uint32_t *eccpos = chip->ecc.layout->eccpos; 2010 unsigned int max_bitflips = 0; 2011 int ret; 2012 2013 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 2014 chip->ecc.hwctl(mtd, NAND_ECC_READ); 2015 2016 ret = nand_read_data_op(chip, p, eccsize, false); 2017 if (ret) 2018 return ret; 2019 2020 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 2021 } 2022 2023 ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false); 2024 if (ret) 2025 return ret; 2026 2027 for (i = 0; i < chip->ecc.total; i++) 2028 ecc_code[i] = chip->oob_poi[eccpos[i]]; 2029 2030 eccsteps = chip->ecc.steps; 2031 p = buf; 2032 2033 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 2034 int stat; 2035 2036 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); 2037 if (stat == -EBADMSG && 2038 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { 2039 /* check for empty pages with bitflips */ 2040 stat = nand_check_erased_ecc_chunk(p, eccsize, 2041 &ecc_code[i], eccbytes, 2042 NULL, 0, 2043 chip->ecc.strength); 2044 } 2045 2046 if (stat < 0) { 2047 mtd->ecc_stats.failed++; 2048 } else { 2049 mtd->ecc_stats.corrected += stat; 2050 max_bitflips = max_t(unsigned int, max_bitflips, stat); 2051 } 2052 } 2053 return max_bitflips; 2054} 2055 2056/** 2057 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first 2058 * @mtd: mtd info structure 2059 * @chip: nand chip info structure 2060 * @buf: buffer to store read data 2061 * @oob_required: caller requires OOB data read to chip->oob_poi 2062 * @page: page number to read 2063 * 2064 * Hardware ECC for large page chips, require OOB to be read first. For this 2065 * ECC mode, the write_page method is re-used from ECC_HW. These methods 2066 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with 2067 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from 2068 * the data area, by overwriting the NAND manufacturer bad block markings. 2069 */ 2070static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd, 2071 struct nand_chip *chip, uint8_t *buf, int oob_required, int page) 2072{ 2073 int i, eccsize = chip->ecc.size; 2074 int eccbytes = chip->ecc.bytes; 2075 int eccsteps = chip->ecc.steps; 2076 uint8_t *p = buf; 2077 uint8_t *ecc_code = chip->buffers->ecccode; 2078 uint32_t *eccpos = chip->ecc.layout->eccpos; 2079 uint8_t *ecc_calc = chip->buffers->ecccalc; 2080 unsigned int max_bitflips = 0; 2081 int ret; 2082 2083 /* Read the OOB area first */ 2084 ret = nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize); 2085 if (ret) 2086 return ret; 2087 2088 ret = nand_read_page_op(chip, page, 0, NULL, 0); 2089 if (ret) 2090 return ret; 2091 2092 for (i = 0; i < chip->ecc.total; i++) 2093 ecc_code[i] = chip->oob_poi[eccpos[i]]; 2094 2095 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 2096 int stat; 2097 2098 chip->ecc.hwctl(mtd, NAND_ECC_READ); 2099 2100 ret = nand_read_data_op(chip, p, eccsize, false); 2101 if (ret) 2102 return ret; 2103 2104 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 2105 2106 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL); 2107 if (stat == -EBADMSG && 2108 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { 2109 /* check for empty pages with bitflips */ 2110 stat = nand_check_erased_ecc_chunk(p, eccsize, 2111 &ecc_code[i], eccbytes, 2112 NULL, 0, 2113 chip->ecc.strength); 2114 } 2115 2116 if (stat < 0) { 2117 mtd->ecc_stats.failed++; 2118 } else { 2119 mtd->ecc_stats.corrected += stat; 2120 max_bitflips = max_t(unsigned int, max_bitflips, stat); 2121 } 2122 } 2123 return max_bitflips; 2124} 2125 2126/** 2127 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read 2128 * @mtd: mtd info structure 2129 * @chip: nand chip info structure 2130 * @buf: buffer to store read data 2131 * @oob_required: caller requires OOB data read to chip->oob_poi 2132 * @page: page number to read 2133 * 2134 * The hw generator calculates the error syndrome automatically. Therefore we 2135 * need a special oob layout and handling. 2136 */ 2137static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip, 2138 uint8_t *buf, int oob_required, int page) 2139{ 2140 int ret, i, eccsize = chip->ecc.size; 2141 int eccbytes = chip->ecc.bytes; 2142 int eccsteps = chip->ecc.steps; 2143 int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad; 2144 uint8_t *p = buf; 2145 uint8_t *oob = chip->oob_poi; 2146 unsigned int max_bitflips = 0; 2147 2148 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 2149 int stat; 2150 2151 chip->ecc.hwctl(mtd, NAND_ECC_READ); 2152 2153 ret = nand_read_data_op(chip, p, eccsize, false); 2154 if (ret) 2155 return ret; 2156 2157 if (chip->ecc.prepad) { 2158 ret = nand_read_data_op(chip, oob, chip->ecc.prepad, 2159 false); 2160 if (ret) 2161 return ret; 2162 2163 oob += chip->ecc.prepad; 2164 } 2165 2166 chip->ecc.hwctl(mtd, NAND_ECC_READSYN); 2167 2168 ret = nand_read_data_op(chip, oob, eccbytes, false); 2169 if (ret) 2170 return ret; 2171 2172 stat = chip->ecc.correct(mtd, p, oob, NULL); 2173 2174 oob += eccbytes; 2175 2176 if (chip->ecc.postpad) { 2177 ret = nand_read_data_op(chip, oob, chip->ecc.postpad, 2178 false); 2179 if (ret) 2180 return ret; 2181 2182 oob += chip->ecc.postpad; 2183 } 2184 2185 if (stat == -EBADMSG && 2186 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { 2187 /* check for empty pages with bitflips */ 2188 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, 2189 oob - eccpadbytes, 2190 eccpadbytes, 2191 NULL, 0, 2192 chip->ecc.strength); 2193 } 2194 2195 if (stat < 0) { 2196 mtd->ecc_stats.failed++; 2197 } else { 2198 mtd->ecc_stats.corrected += stat; 2199 max_bitflips = max_t(unsigned int, max_bitflips, stat); 2200 } 2201 } 2202 2203 /* Calculate remaining oob bytes */ 2204 i = mtd->oobsize - (oob - chip->oob_poi); 2205 if (i) { 2206 ret = nand_read_data_op(chip, oob, i, false); 2207 if (ret) 2208 return ret; 2209 } 2210 2211 return max_bitflips; 2212} 2213 2214/** 2215 * nand_transfer_oob - [INTERN] Transfer oob to client buffer 2216 * @chip: nand chip structure 2217 * @oob: oob destination address 2218 * @ops: oob ops structure 2219 * @len: size of oob to transfer 2220 */ 2221static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob, 2222 struct mtd_oob_ops *ops, size_t len) 2223{ 2224 switch (ops->mode) { 2225 2226 case MTD_OPS_PLACE_OOB: 2227 case MTD_OPS_RAW: 2228 memcpy(oob, chip->oob_poi + ops->ooboffs, len); 2229 return oob + len; 2230 2231 case MTD_OPS_AUTO_OOB: { 2232 struct nand_oobfree *free = chip->ecc.layout->oobfree; 2233 uint32_t boffs = 0, roffs = ops->ooboffs; 2234 size_t bytes = 0; 2235 2236 for (; free->length && len; free++, len -= bytes) { 2237 /* Read request not from offset 0? */ 2238 if (unlikely(roffs)) { 2239 if (roffs >= free->length) { 2240 roffs -= free->length; 2241 continue; 2242 } 2243 boffs = free->offset + roffs; 2244 bytes = min_t(size_t, len, 2245 (free->length - roffs)); 2246 roffs = 0; 2247 } else { 2248 bytes = min_t(size_t, len, free->length); 2249 boffs = free->offset; 2250 } 2251 memcpy(oob, chip->oob_poi + boffs, bytes); 2252 oob += bytes; 2253 } 2254 return oob; 2255 } 2256 default: 2257 BUG(); 2258 } 2259 return NULL; 2260} 2261 2262/** 2263 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode 2264 * @mtd: MTD device structure 2265 * @retry_mode: the retry mode to use 2266 * 2267 * Some vendors supply a special command to shift the Vt threshold, to be used 2268 * when there are too many bitflips in a page (i.e., ECC error). After setting 2269 * a new threshold, the host should retry reading the page. 2270 */ 2271static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode) 2272{ 2273 struct nand_chip *chip = mtd_to_nand(mtd); 2274 2275 pr_debug("setting READ RETRY mode %d\n", retry_mode); 2276 2277 if (retry_mode >= chip->read_retries) 2278 return -EINVAL; 2279 2280 if (!chip->setup_read_retry) 2281 return -EOPNOTSUPP; 2282 2283 return chip->setup_read_retry(mtd, retry_mode); 2284} 2285 2286/** 2287 * nand_do_read_ops - [INTERN] Read data with ECC 2288 * @mtd: MTD device structure 2289 * @from: offset to read from 2290 * @ops: oob ops structure 2291 * 2292 * Internal function. Called with chip held. 2293 */ 2294static int nand_do_read_ops(struct mtd_info *mtd, loff_t from, 2295 struct mtd_oob_ops *ops) 2296{ 2297 int chipnr, page, realpage, col, bytes, aligned, oob_required; 2298 struct nand_chip *chip = mtd_to_nand(mtd); 2299 int ret = 0; 2300 uint32_t readlen = ops->len; 2301 uint32_t oobreadlen = ops->ooblen; 2302 uint32_t max_oobsize = mtd_oobavail(mtd, ops); 2303 2304 uint8_t *bufpoi, *oob, *buf; 2305 int use_bufpoi; 2306 unsigned int max_bitflips = 0; 2307 int retry_mode = 0; 2308 bool ecc_fail = false; 2309 2310 chipnr = (int)(from >> chip->chip_shift); 2311 chip->select_chip(mtd, chipnr); 2312 2313 realpage = (int)(from >> chip->page_shift); 2314 page = realpage & chip->pagemask; 2315 2316 col = (int)(from & (mtd->writesize - 1)); 2317 2318 buf = ops->datbuf; 2319 oob = ops->oobbuf; 2320 oob_required = oob ? 1 : 0; 2321 2322 while (1) { 2323 unsigned int ecc_failures = mtd->ecc_stats.failed; 2324 2325 schedule(); 2326 bytes = min(mtd->writesize - col, readlen); 2327 aligned = (bytes == mtd->writesize); 2328 2329 if (!aligned) 2330 use_bufpoi = 1; 2331 else if (chip->options & NAND_USE_BOUNCE_BUFFER) 2332 use_bufpoi = !IS_ALIGNED((unsigned long)buf, 2333 chip->buf_align); 2334 else 2335 use_bufpoi = 0; 2336 2337 /* Is the current page in the buffer? */ 2338 if (realpage != chip->pagebuf || oob) { 2339 bufpoi = use_bufpoi ? chip->buffers->databuf : buf; 2340 2341 if (use_bufpoi && aligned) 2342 pr_debug("%s: using read bounce buffer for buf@%p\n", 2343 __func__, buf); 2344 2345read_retry: 2346 if (nand_standard_page_accessors(&chip->ecc)) { 2347 ret = nand_read_page_op(chip, page, 0, NULL, 0); 2348 if (ret) 2349 break; 2350 } 2351 2352 /* 2353 * Now read the page into the buffer. Absent an error, 2354 * the read methods return max bitflips per ecc step. 2355 */ 2356 if (unlikely(ops->mode == MTD_OPS_RAW)) 2357 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi, 2358 oob_required, 2359 page); 2360 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) && 2361 !oob) 2362 ret = chip->ecc.read_subpage(mtd, chip, 2363 col, bytes, bufpoi, 2364 page); 2365 else 2366 ret = chip->ecc.read_page(mtd, chip, bufpoi, 2367 oob_required, page); 2368 if (ret < 0) { 2369 if (use_bufpoi) 2370 /* Invalidate page cache */ 2371 chip->pagebuf = -1; 2372 break; 2373 } 2374 2375 max_bitflips = max_t(unsigned int, max_bitflips, ret); 2376 2377 /* Transfer not aligned data */ 2378 if (use_bufpoi) { 2379 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob && 2380 !(mtd->ecc_stats.failed - ecc_failures) && 2381 (ops->mode != MTD_OPS_RAW)) { 2382 chip->pagebuf = realpage; 2383 chip->pagebuf_bitflips = ret; 2384 } else { 2385 /* Invalidate page cache */ 2386 chip->pagebuf = -1; 2387 } 2388 memcpy(buf, chip->buffers->databuf + col, bytes); 2389 } 2390 2391 if (unlikely(oob)) { 2392 int toread = min(oobreadlen, max_oobsize); 2393 2394 if (toread) { 2395 oob = nand_transfer_oob(chip, 2396 oob, ops, toread); 2397 oobreadlen -= toread; 2398 } 2399 } 2400 2401 if (chip->options & NAND_NEED_READRDY) { 2402 /* Apply delay or wait for ready/busy pin */ 2403 if (!chip->dev_ready) 2404 udelay(chip->chip_delay); 2405 else 2406 nand_wait_ready(mtd); 2407 } 2408 2409 if (mtd->ecc_stats.failed - ecc_failures) { 2410 if (retry_mode + 1 < chip->read_retries) { 2411 retry_mode++; 2412 ret = nand_setup_read_retry(mtd, 2413 retry_mode); 2414 if (ret < 0) 2415 break; 2416 2417 /* Reset failures; retry */ 2418 mtd->ecc_stats.failed = ecc_failures; 2419 goto read_retry; 2420 } else { 2421 /* No more retry modes; real failure */ 2422 ecc_fail = true; 2423 } 2424 } 2425 2426 buf += bytes; 2427 } else { 2428 memcpy(buf, chip->buffers->databuf + col, bytes); 2429 buf += bytes; 2430 max_bitflips = max_t(unsigned int, max_bitflips, 2431 chip->pagebuf_bitflips); 2432 } 2433 2434 readlen -= bytes; 2435 2436 /* Reset to retry mode 0 */ 2437 if (retry_mode) { 2438 ret = nand_setup_read_retry(mtd, 0); 2439 if (ret < 0) 2440 break; 2441 retry_mode = 0; 2442 } 2443 2444 if (!readlen) 2445 break; 2446 2447 /* For subsequent reads align to page boundary */ 2448 col = 0; 2449 /* Increment page address */ 2450 realpage++; 2451 2452 page = realpage & chip->pagemask; 2453 /* Check, if we cross a chip boundary */ 2454 if (!page) { 2455 chipnr++; 2456 chip->select_chip(mtd, -1); 2457 chip->select_chip(mtd, chipnr); 2458 } 2459 } 2460 chip->select_chip(mtd, -1); 2461 2462 ops->retlen = ops->len - (size_t) readlen; 2463 if (oob) 2464 ops->oobretlen = ops->ooblen - oobreadlen; 2465 2466 if (ret < 0) 2467 return ret; 2468 2469 if (ecc_fail) 2470 return -EBADMSG; 2471 2472 return max_bitflips; 2473} 2474 2475/** 2476 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function 2477 * @mtd: mtd info structure 2478 * @chip: nand chip info structure 2479 * @page: page number to read 2480 */ 2481static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, 2482 int page) 2483{ 2484 return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize); 2485} 2486 2487/** 2488 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC 2489 * with syndromes 2490 * @mtd: mtd info structure 2491 * @chip: nand chip info structure 2492 * @page: page number to read 2493 */ 2494static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, 2495 int page) 2496{ 2497 int length = mtd->oobsize; 2498 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; 2499 int eccsize = chip->ecc.size; 2500 uint8_t *bufpoi = chip->oob_poi; 2501 int i, toread, sndrnd = 0, pos, ret; 2502 2503 ret = nand_read_page_op(chip, page, chip->ecc.size, NULL, 0); 2504 if (ret) 2505 return ret; 2506 2507 for (i = 0; i < chip->ecc.steps; i++) { 2508 if (sndrnd) { 2509 int ret; 2510 2511 pos = eccsize + i * (eccsize + chunk); 2512 if (mtd->writesize > 512) 2513 ret = nand_change_read_column_op(chip, pos, 2514 NULL, 0, 2515 false); 2516 else 2517 ret = nand_read_page_op(chip, page, pos, NULL, 2518 0); 2519 2520 if (ret) 2521 return ret; 2522 } else 2523 sndrnd = 1; 2524 toread = min_t(int, length, chunk); 2525 2526 ret = nand_read_data_op(chip, bufpoi, toread, false); 2527 if (ret) 2528 return ret; 2529 2530 bufpoi += toread; 2531 length -= toread; 2532 } 2533 if (length > 0) { 2534 ret = nand_read_data_op(chip, bufpoi, length, false); 2535 if (ret) 2536 return ret; 2537 } 2538 2539 return 0; 2540} 2541 2542/** 2543 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function 2544 * @mtd: mtd info structure 2545 * @chip: nand chip info structure 2546 * @page: page number to write 2547 */ 2548static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, 2549 int page) 2550{ 2551 return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi, 2552 mtd->oobsize); 2553} 2554 2555/** 2556 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC 2557 * with syndrome - only for large page flash 2558 * @mtd: mtd info structure 2559 * @chip: nand chip info structure 2560 * @page: page number to write 2561 */ 2562static int nand_write_oob_syndrome(struct mtd_info *mtd, 2563 struct nand_chip *chip, int page) 2564{ 2565 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; 2566 int eccsize = chip->ecc.size, length = mtd->oobsize; 2567 int ret, i, len, pos, sndcmd = 0, steps = chip->ecc.steps; 2568 const uint8_t *bufpoi = chip->oob_poi; 2569 2570 /* 2571 * data-ecc-data-ecc ... ecc-oob 2572 * or 2573 * data-pad-ecc-pad-data-pad .... ecc-pad-oob 2574 */ 2575 if (!chip->ecc.prepad && !chip->ecc.postpad) { 2576 pos = steps * (eccsize + chunk); 2577 steps = 0; 2578 } else 2579 pos = eccsize; 2580 2581 ret = nand_prog_page_begin_op(chip, page, pos, NULL, 0); 2582 if (ret) 2583 return ret; 2584 2585 for (i = 0; i < steps; i++) { 2586 if (sndcmd) { 2587 if (mtd->writesize <= 512) { 2588 uint32_t fill = 0xFFFFFFFF; 2589 2590 len = eccsize; 2591 while (len > 0) { 2592 int num = min_t(int, len, 4); 2593 2594 ret = nand_write_data_op(chip, &fill, 2595 num, false); 2596 if (ret) 2597 return ret; 2598 2599 len -= num; 2600 } 2601 } else { 2602 pos = eccsize + i * (eccsize + chunk); 2603 ret = nand_change_write_column_op(chip, pos, 2604 NULL, 0, 2605 false); 2606 if (ret) 2607 return ret; 2608 } 2609 } else 2610 sndcmd = 1; 2611 len = min_t(int, length, chunk); 2612 2613 ret = nand_write_data_op(chip, bufpoi, len, false); 2614 if (ret) 2615 return ret; 2616 2617 bufpoi += len; 2618 length -= len; 2619 } 2620 if (length > 0) { 2621 ret = nand_write_data_op(chip, bufpoi, length, false); 2622 if (ret) 2623 return ret; 2624 } 2625 2626 return nand_prog_page_end_op(chip); 2627} 2628 2629/** 2630 * nand_do_read_oob - [INTERN] NAND read out-of-band 2631 * @mtd: MTD device structure 2632 * @from: offset to read from 2633 * @ops: oob operations description structure 2634 * 2635 * NAND read out-of-band data from the spare area. 2636 */ 2637static int nand_do_read_oob(struct mtd_info *mtd, loff_t from, 2638 struct mtd_oob_ops *ops) 2639{ 2640 int page, realpage, chipnr; 2641 struct nand_chip *chip = mtd_to_nand(mtd); 2642 struct mtd_ecc_stats stats; 2643 int readlen = ops->ooblen; 2644 int len; 2645 uint8_t *buf = ops->oobbuf; 2646 int ret = 0; 2647 2648 pr_debug("%s: from = 0x%08Lx, len = %i\n", 2649 __func__, (unsigned long long)from, readlen); 2650 2651 stats = mtd->ecc_stats; 2652 2653 len = mtd_oobavail(mtd, ops); 2654 2655 if (unlikely(ops->ooboffs >= len)) { 2656 pr_debug("%s: attempt to start read outside oob\n", 2657 __func__); 2658 return -EINVAL; 2659 } 2660 2661 /* Do not allow reads past end of device */ 2662 if (unlikely(from >= mtd->size || 2663 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) - 2664 (from >> chip->page_shift)) * len)) { 2665 pr_debug("%s: attempt to read beyond end of device\n", 2666 __func__); 2667 return -EINVAL; 2668 } 2669 2670 chipnr = (int)(from >> chip->chip_shift); 2671 chip->select_chip(mtd, chipnr); 2672 2673 /* Shift to get page */ 2674 realpage = (int)(from >> chip->page_shift); 2675 page = realpage & chip->pagemask; 2676 2677 while (1) { 2678 schedule(); 2679 2680 if (ops->mode == MTD_OPS_RAW) 2681 ret = chip->ecc.read_oob_raw(mtd, chip, page); 2682 else 2683 ret = chip->ecc.read_oob(mtd, chip, page); 2684 2685 if (ret < 0) 2686 break; 2687 2688 len = min(len, readlen); 2689 buf = nand_transfer_oob(chip, buf, ops, len); 2690 2691 if (chip->options & NAND_NEED_READRDY) { 2692 /* Apply delay or wait for ready/busy pin */ 2693 if (!chip->dev_ready) 2694 udelay(chip->chip_delay); 2695 else 2696 nand_wait_ready(mtd); 2697 } 2698 2699 readlen -= len; 2700 if (!readlen) 2701 break; 2702 2703 /* Increment page address */ 2704 realpage++; 2705 2706 page = realpage & chip->pagemask; 2707 /* Check, if we cross a chip boundary */ 2708 if (!page) { 2709 chipnr++; 2710 chip->select_chip(mtd, -1); 2711 chip->select_chip(mtd, chipnr); 2712 } 2713 } 2714 chip->select_chip(mtd, -1); 2715 2716 ops->oobretlen = ops->ooblen - readlen; 2717 2718 if (ret < 0) 2719 return ret; 2720 2721 if (mtd->ecc_stats.failed - stats.failed) 2722 return -EBADMSG; 2723 2724 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; 2725} 2726 2727/** 2728 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band 2729 * @mtd: MTD device structure 2730 * @from: offset to read from 2731 * @ops: oob operation description structure 2732 * 2733 * NAND read data and/or out-of-band data. 2734 */ 2735static int nand_read_oob(struct mtd_info *mtd, loff_t from, 2736 struct mtd_oob_ops *ops) 2737{ 2738 int ret = -ENOTSUPP; 2739 2740 ops->retlen = 0; 2741 2742 /* Do not allow reads past end of device */ 2743 if (ops->datbuf && (from + ops->len) > mtd->size) { 2744 pr_debug("%s: attempt to read beyond end of device\n", 2745 __func__); 2746 return -EINVAL; 2747 } 2748 2749 nand_get_device(mtd, FL_READING); 2750 2751 switch (ops->mode) { 2752 case MTD_OPS_PLACE_OOB: 2753 case MTD_OPS_AUTO_OOB: 2754 case MTD_OPS_RAW: 2755 break; 2756 2757 default: 2758 goto out; 2759 } 2760 2761 if (!ops->datbuf) 2762 ret = nand_do_read_oob(mtd, from, ops); 2763 else 2764 ret = nand_do_read_ops(mtd, from, ops); 2765 2766out: 2767 nand_release_device(mtd); 2768 return ret; 2769} 2770 2771 2772/** 2773 * nand_write_page_raw - [INTERN] raw page write function 2774 * @mtd: mtd info structure 2775 * @chip: nand chip info structure 2776 * @buf: data buffer 2777 * @oob_required: must write chip->oob_poi to OOB 2778 * @page: page number to write 2779 * 2780 * Not for syndrome calculating ECC controllers, which use a special oob layout. 2781 */ 2782static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 2783 const uint8_t *buf, int oob_required, int page) 2784{ 2785 int ret; 2786 2787 ret = nand_write_data_op(chip, buf, mtd->writesize, false); 2788 if (ret) 2789 return ret; 2790 2791 if (oob_required) { 2792 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, 2793 false); 2794 if (ret) 2795 return ret; 2796 } 2797 2798 return 0; 2799} 2800 2801/** 2802 * nand_write_page_raw_syndrome - [INTERN] raw page write function 2803 * @mtd: mtd info structure 2804 * @chip: nand chip info structure 2805 * @buf: data buffer 2806 * @oob_required: must write chip->oob_poi to OOB 2807 * @page: page number to write 2808 * 2809 * We need a special oob layout and handling even when ECC isn't checked. 2810 */ 2811static int nand_write_page_raw_syndrome(struct mtd_info *mtd, 2812 struct nand_chip *chip, 2813 const uint8_t *buf, int oob_required, 2814 int page) 2815{ 2816 int eccsize = chip->ecc.size; 2817 int eccbytes = chip->ecc.bytes; 2818 uint8_t *oob = chip->oob_poi; 2819 int steps, size, ret; 2820 2821 for (steps = chip->ecc.steps; steps > 0; steps--) { 2822 ret = nand_write_data_op(chip, buf, eccsize, false); 2823 if (ret) 2824 return ret; 2825 2826 buf += eccsize; 2827 2828 if (chip->ecc.prepad) { 2829 ret = nand_write_data_op(chip, oob, chip->ecc.prepad, 2830 false); 2831 if (ret) 2832 return ret; 2833 2834 oob += chip->ecc.prepad; 2835 } 2836 2837 ret = nand_write_data_op(chip, oob, eccbytes, false); 2838 if (ret) 2839 return ret; 2840 2841 oob += eccbytes; 2842 2843 if (chip->ecc.postpad) { 2844 ret = nand_write_data_op(chip, oob, chip->ecc.postpad, 2845 false); 2846 if (ret) 2847 return ret; 2848 2849 oob += chip->ecc.postpad; 2850 } 2851 } 2852 2853 size = mtd->oobsize - (oob - chip->oob_poi); 2854 if (size) { 2855 ret = nand_write_data_op(chip, oob, size, false); 2856 if (ret) 2857 return ret; 2858 } 2859 2860 return 0; 2861} 2862/** 2863 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function 2864 * @mtd: mtd info structure 2865 * @chip: nand chip info structure 2866 * @buf: data buffer 2867 * @oob_required: must write chip->oob_poi to OOB 2868 * @page: page number to write 2869 */ 2870static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip, 2871 const uint8_t *buf, int oob_required, 2872 int page) 2873{ 2874 int i, eccsize = chip->ecc.size; 2875 int eccbytes = chip->ecc.bytes; 2876 int eccsteps = chip->ecc.steps; 2877 uint8_t *ecc_calc = chip->buffers->ecccalc; 2878 const uint8_t *p = buf; 2879 uint32_t *eccpos = chip->ecc.layout->eccpos; 2880 2881 /* Software ECC calculation */ 2882 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) 2883 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 2884 2885 for (i = 0; i < chip->ecc.total; i++) 2886 chip->oob_poi[eccpos[i]] = ecc_calc[i]; 2887 2888 return chip->ecc.write_page_raw(mtd, chip, buf, 1, page); 2889} 2890 2891/** 2892 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function 2893 * @mtd: mtd info structure 2894 * @chip: nand chip info structure 2895 * @buf: data buffer 2896 * @oob_required: must write chip->oob_poi to OOB 2897 * @page: page number to write 2898 */ 2899static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, 2900 const uint8_t *buf, int oob_required, 2901 int page) 2902{ 2903 int i, eccsize = chip->ecc.size; 2904 int eccbytes = chip->ecc.bytes; 2905 int eccsteps = chip->ecc.steps; 2906 uint8_t *ecc_calc = chip->buffers->ecccalc; 2907 const uint8_t *p = buf; 2908 uint32_t *eccpos = chip->ecc.layout->eccpos; 2909 int ret; 2910 2911 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 2912 chip->ecc.hwctl(mtd, NAND_ECC_WRITE); 2913 2914 ret = nand_write_data_op(chip, p, eccsize, false); 2915 if (ret) 2916 return ret; 2917 2918 chip->ecc.calculate(mtd, p, &ecc_calc[i]); 2919 } 2920 2921 for (i = 0; i < chip->ecc.total; i++) 2922 chip->oob_poi[eccpos[i]] = ecc_calc[i]; 2923 2924 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false); 2925 if (ret) 2926 return ret; 2927 2928 return 0; 2929} 2930 2931 2932/** 2933 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write 2934 * @mtd: mtd info structure 2935 * @chip: nand chip info structure 2936 * @offset: column address of subpage within the page 2937 * @data_len: data length 2938 * @buf: data buffer 2939 * @oob_required: must write chip->oob_poi to OOB 2940 * @page: page number to write 2941 */ 2942static int nand_write_subpage_hwecc(struct mtd_info *mtd, 2943 struct nand_chip *chip, uint32_t offset, 2944 uint32_t data_len, const uint8_t *buf, 2945 int oob_required, int page) 2946{ 2947 uint8_t *oob_buf = chip->oob_poi; 2948 uint8_t *ecc_calc = chip->buffers->ecccalc; 2949 int ecc_size = chip->ecc.size; 2950 int ecc_bytes = chip->ecc.bytes; 2951 int ecc_steps = chip->ecc.steps; 2952 uint32_t *eccpos = chip->ecc.layout->eccpos; 2953 uint32_t start_step = offset / ecc_size; 2954 uint32_t end_step = (offset + data_len - 1) / ecc_size; 2955 int oob_bytes = mtd->oobsize / ecc_steps; 2956 int step, i; 2957 int ret; 2958 2959 for (step = 0; step < ecc_steps; step++) { 2960 /* configure controller for WRITE access */ 2961 chip->ecc.hwctl(mtd, NAND_ECC_WRITE); 2962 2963 /* write data (untouched subpages already masked by 0xFF) */ 2964 ret = nand_write_data_op(chip, buf, ecc_size, false); 2965 if (ret) 2966 return ret; 2967 2968 /* mask ECC of un-touched subpages by padding 0xFF */ 2969 if ((step < start_step) || (step > end_step)) 2970 memset(ecc_calc, 0xff, ecc_bytes); 2971 else 2972 chip->ecc.calculate(mtd, buf, ecc_calc); 2973 2974 /* mask OOB of un-touched subpages by padding 0xFF */ 2975 /* if oob_required, preserve OOB metadata of written subpage */ 2976 if (!oob_required || (step < start_step) || (step > end_step)) 2977 memset(oob_buf, 0xff, oob_bytes); 2978 2979 buf += ecc_size; 2980 ecc_calc += ecc_bytes; 2981 oob_buf += oob_bytes; 2982 } 2983 2984 /* copy calculated ECC for whole page to chip->buffer->oob */ 2985 /* this include masked-value(0xFF) for unwritten subpages */ 2986 ecc_calc = chip->buffers->ecccalc; 2987 for (i = 0; i < chip->ecc.total; i++) 2988 chip->oob_poi[eccpos[i]] = ecc_calc[i]; 2989 2990 /* write OOB buffer to NAND device */ 2991 ret = nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false); 2992 if (ret) 2993 return ret; 2994 2995 return 0; 2996} 2997 2998 2999/** 3000 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write 3001 * @mtd: mtd info structure 3002 * @chip: nand chip info structure 3003 * @buf: data buffer 3004 * @oob_required: must write chip->oob_poi to OOB 3005 * @page: page number to write 3006 * 3007 * The hw generator calculates the error syndrome automatically. Therefore we 3008 * need a special oob layout and handling. 3009 */ 3010static int nand_write_page_syndrome(struct mtd_info *mtd, 3011 struct nand_chip *chip, 3012 const uint8_t *buf, int oob_required, 3013 int page) 3014{ 3015 int i, eccsize = chip->ecc.size; 3016 int eccbytes = chip->ecc.bytes; 3017 int eccsteps = chip->ecc.steps; 3018 const uint8_t *p = buf; 3019 uint8_t *oob = chip->oob_poi; 3020 int ret; 3021 3022 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { 3023 chip->ecc.hwctl(mtd, NAND_ECC_WRITE); 3024 3025 ret = nand_write_data_op(chip, p, eccsize, false); 3026 if (ret) 3027 return ret; 3028 3029 if (chip->ecc.prepad) { 3030 ret = nand_write_data_op(chip, oob, chip->ecc.prepad, 3031 false); 3032 if (ret) 3033 return ret; 3034 3035 oob += chip->ecc.prepad; 3036 } 3037 3038 chip->ecc.calculate(mtd, p, oob); 3039 3040 ret = nand_write_data_op(chip, oob, eccbytes, false); 3041 if (ret) 3042 return ret; 3043 3044 oob += eccbytes; 3045 3046 if (chip->ecc.postpad) { 3047 ret = nand_write_data_op(chip, oob, chip->ecc.postpad, 3048 false); 3049 if (ret) 3050 return ret; 3051 3052 oob += chip->ecc.postpad; 3053 } 3054 } 3055 3056 /* Calculate remaining oob bytes */ 3057 i = mtd->oobsize - (oob - chip->oob_poi); 3058 if (i) { 3059 ret = nand_write_data_op(chip, oob, i, false); 3060 if (ret) 3061 return ret; 3062 } 3063 3064 return 0; 3065} 3066 3067/** 3068 * nand_write_page - [REPLACEABLE] write one page 3069 * @mtd: MTD device structure 3070 * @chip: NAND chip descriptor 3071 * @offset: address offset within the page 3072 * @data_len: length of actual data to be written 3073 * @buf: the data to write 3074 * @oob_required: must write chip->oob_poi to OOB 3075 * @page: page number to write 3076 * @raw: use _raw version of write_page 3077 */ 3078static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, 3079 uint32_t offset, int data_len, const uint8_t *buf, 3080 int oob_required, int page, int raw) 3081{ 3082 int status, subpage; 3083 3084 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && 3085 chip->ecc.write_subpage) 3086 subpage = offset || (data_len < mtd->writesize); 3087 else 3088 subpage = 0; 3089 3090 if (nand_standard_page_accessors(&chip->ecc)) { 3091 status = nand_prog_page_begin_op(chip, page, 0, NULL, 0); 3092 if (status) 3093 return status; 3094 } 3095 3096 if (unlikely(raw)) 3097 status = chip->ecc.write_page_raw(mtd, chip, buf, 3098 oob_required, page); 3099 else if (subpage) 3100 status = chip->ecc.write_subpage(mtd, chip, offset, data_len, 3101 buf, oob_required, page); 3102 else 3103 status = chip->ecc.write_page(mtd, chip, buf, oob_required, 3104 page); 3105 3106 if (status < 0) 3107 return status; 3108 3109 if (nand_standard_page_accessors(&chip->ecc)) 3110 return nand_prog_page_end_op(chip); 3111 3112 return 0; 3113} 3114 3115/** 3116 * nand_fill_oob - [INTERN] Transfer client buffer to oob 3117 * @mtd: MTD device structure 3118 * @oob: oob data buffer 3119 * @len: oob data write length 3120 * @ops: oob ops structure 3121 */ 3122static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len, 3123 struct mtd_oob_ops *ops) 3124{ 3125 struct nand_chip *chip = mtd_to_nand(mtd); 3126 3127 /* 3128 * Initialise to all 0xFF, to avoid the possibility of left over OOB 3129 * data from a previous OOB read. 3130 */ 3131 memset(chip->oob_poi, 0xff, mtd->oobsize); 3132 3133 switch (ops->mode) { 3134 3135 case MTD_OPS_PLACE_OOB: 3136 case MTD_OPS_RAW: 3137 memcpy(chip->oob_poi + ops->ooboffs, oob, len); 3138 return oob + len; 3139 3140 case MTD_OPS_AUTO_OOB: { 3141 struct nand_oobfree *free = chip->ecc.layout->oobfree; 3142 uint32_t boffs = 0, woffs = ops->ooboffs; 3143 size_t bytes = 0; 3144 3145 for (; free->length && len; free++, len -= bytes) { 3146 /* Write request not from offset 0? */ 3147 if (unlikely(woffs)) { 3148 if (woffs >= free->length) { 3149 woffs -= free->length; 3150 continue; 3151 } 3152 boffs = free->offset + woffs; 3153 bytes = min_t(size_t, len, 3154 (free->length - woffs)); 3155 woffs = 0; 3156 } else { 3157 bytes = min_t(size_t, len, free->length); 3158 boffs = free->offset; 3159 } 3160 memcpy(chip->oob_poi + boffs, oob, bytes); 3161 oob += bytes; 3162 } 3163 return oob; 3164 } 3165 default: 3166 BUG(); 3167 } 3168 return NULL; 3169} 3170 3171#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0) 3172 3173/** 3174 * nand_do_write_ops - [INTERN] NAND write with ECC 3175 * @mtd: MTD device structure 3176 * @to: offset to write to 3177 * @ops: oob operations description structure 3178 * 3179 * NAND write with ECC. 3180 */ 3181static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, 3182 struct mtd_oob_ops *ops) 3183{ 3184 int chipnr, realpage, page, column; 3185 struct nand_chip *chip = mtd_to_nand(mtd); 3186 uint32_t writelen = ops->len; 3187 3188 uint32_t oobwritelen = ops->ooblen; 3189 uint32_t oobmaxlen = mtd_oobavail(mtd, ops); 3190 3191 uint8_t *oob = ops->oobbuf; 3192 uint8_t *buf = ops->datbuf; 3193 int ret; 3194 int oob_required = oob ? 1 : 0; 3195 3196 ops->retlen = 0; 3197 if (!writelen) 3198 return 0; 3199 3200 /* Reject writes, which are not page aligned */ 3201 if (NOTALIGNED(to)) { 3202 pr_notice("%s: attempt to write non page aligned data\n", 3203 __func__); 3204 return -EINVAL; 3205 } 3206 3207 column = to & (mtd->writesize - 1); 3208 3209 chipnr = (int)(to >> chip->chip_shift); 3210 chip->select_chip(mtd, chipnr); 3211 3212 /* Check, if it is write protected */ 3213 if (nand_check_wp(mtd)) { 3214 ret = -EIO; 3215 goto err_out; 3216 } 3217 3218 realpage = (int)(to >> chip->page_shift); 3219 page = realpage & chip->pagemask; 3220 3221 /* Invalidate the page cache, when we write to the cached page */ 3222 if (to <= ((loff_t)chip->pagebuf << chip->page_shift) && 3223 ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len)) 3224 chip->pagebuf = -1; 3225 3226 /* Don't allow multipage oob writes with offset */ 3227 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) { 3228 ret = -EINVAL; 3229 goto err_out; 3230 } 3231 3232 while (1) { 3233 int bytes = mtd->writesize; 3234 uint8_t *wbuf = buf; 3235 int use_bufpoi; 3236 int part_pagewr = (column || writelen < mtd->writesize); 3237 3238 if (part_pagewr) 3239 use_bufpoi = 1; 3240 else if (chip->options & NAND_USE_BOUNCE_BUFFER) 3241 use_bufpoi = !IS_ALIGNED((unsigned long)buf, 3242 chip->buf_align); 3243 else 3244 use_bufpoi = 0; 3245 3246 schedule(); 3247 /* Partial page write?, or need to use bounce buffer */ 3248 if (use_bufpoi) { 3249 pr_debug("%s: using write bounce buffer for buf@%p\n", 3250 __func__, buf); 3251 if (part_pagewr) 3252 bytes = min_t(int, bytes - column, writelen); 3253 chip->pagebuf = -1; 3254 memset(chip->buffers->databuf, 0xff, mtd->writesize); 3255 memcpy(&chip->buffers->databuf[column], buf, bytes); 3256 wbuf = chip->buffers->databuf; 3257 } 3258 3259 if (unlikely(oob)) { 3260 size_t len = min(oobwritelen, oobmaxlen); 3261 oob = nand_fill_oob(mtd, oob, len, ops); 3262 oobwritelen -= len; 3263 } else { 3264 /* We still need to erase leftover OOB data */ 3265 memset(chip->oob_poi, 0xff, mtd->oobsize); 3266 } 3267 ret = chip->write_page(mtd, chip, column, bytes, wbuf, 3268 oob_required, page, 3269 (ops->mode == MTD_OPS_RAW)); 3270 if (ret) 3271 break; 3272 3273 writelen -= bytes; 3274 if (!writelen) 3275 break; 3276 3277 column = 0; 3278 buf += bytes; 3279 realpage++; 3280 3281 page = realpage & chip->pagemask; 3282 /* Check, if we cross a chip boundary */ 3283 if (!page) { 3284 chipnr++; 3285 chip->select_chip(mtd, -1); 3286 chip->select_chip(mtd, chipnr); 3287 } 3288 } 3289 3290 ops->retlen = ops->len - writelen; 3291 if (unlikely(oob)) 3292 ops->oobretlen = ops->ooblen; 3293 3294err_out: 3295 chip->select_chip(mtd, -1); 3296 return ret; 3297} 3298 3299/** 3300 * panic_nand_write - [MTD Interface] NAND write with ECC 3301 * @mtd: MTD device structure 3302 * @to: offset to write to 3303 * @len: number of bytes to write 3304 * @retlen: pointer to variable to store the number of written bytes 3305 * @buf: the data to write 3306 * 3307 * NAND write with ECC. Used when performing writes in interrupt context, this 3308 * may for example be called by mtdoops when writing an oops while in panic. 3309 */ 3310static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len, 3311 size_t *retlen, const uint8_t *buf) 3312{ 3313 struct nand_chip *chip = mtd_to_nand(mtd); 3314 struct mtd_oob_ops ops; 3315 int ret; 3316 3317 /* Wait for the device to get ready */ 3318 panic_nand_wait(mtd, chip, 400); 3319 3320 /* Grab the device */ 3321 panic_nand_get_device(chip, mtd, FL_WRITING); 3322 3323 memset(&ops, 0, sizeof(ops)); 3324 ops.len = len; 3325 ops.datbuf = (uint8_t *)buf; 3326 ops.mode = MTD_OPS_PLACE_OOB; 3327 3328 ret = nand_do_write_ops(mtd, to, &ops); 3329 3330 *retlen = ops.retlen; 3331 return ret; 3332} 3333 3334/** 3335 * nand_do_write_oob - [MTD Interface] NAND write out-of-band 3336 * @mtd: MTD device structure 3337 * @to: offset to write to 3338 * @ops: oob operation description structure 3339 * 3340 * NAND write out-of-band. 3341 */ 3342static int nand_do_write_oob(struct mtd_info *mtd, loff_t to, 3343 struct mtd_oob_ops *ops) 3344{ 3345 int chipnr, page, status, len; 3346 struct nand_chip *chip = mtd_to_nand(mtd); 3347 3348 pr_debug("%s: to = 0x%08x, len = %i\n", 3349 __func__, (unsigned int)to, (int)ops->ooblen); 3350 3351 len = mtd_oobavail(mtd, ops); 3352 3353 /* Do not allow write past end of page */ 3354 if ((ops->ooboffs + ops->ooblen) > len) { 3355 pr_debug("%s: attempt to write past end of page\n", 3356 __func__); 3357 return -EINVAL; 3358 } 3359 3360 if (unlikely(ops->ooboffs >= len)) { 3361 pr_debug("%s: attempt to start write outside oob\n", 3362 __func__); 3363 return -EINVAL; 3364 } 3365 3366 /* Do not allow write past end of device */ 3367 if (unlikely(to >= mtd->size || 3368 ops->ooboffs + ops->ooblen > 3369 ((mtd->size >> chip->page_shift) - 3370 (to >> chip->page_shift)) * len)) { 3371 pr_debug("%s: attempt to write beyond end of device\n", 3372 __func__); 3373 return -EINVAL; 3374 } 3375 3376 chipnr = (int)(to >> chip->chip_shift); 3377 3378 /* 3379 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one 3380 * of my DiskOnChip 2000 test units) will clear the whole data page too 3381 * if we don't do this. I have no clue why, but I seem to have 'fixed' 3382 * it in the doc2000 driver in August 1999. dwmw2. 3383 */ 3384 nand_reset(chip, chipnr); 3385 3386 chip->select_chip(mtd, chipnr); 3387 3388 /* Shift to get page */ 3389 page = (int)(to >> chip->page_shift); 3390 3391 /* Check, if it is write protected */ 3392 if (nand_check_wp(mtd)) { 3393 chip->select_chip(mtd, -1); 3394 return -EROFS; 3395 } 3396 3397 /* Invalidate the page cache, if we write to the cached page */ 3398 if (page == chip->pagebuf) 3399 chip->pagebuf = -1; 3400 3401 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops); 3402 3403 if (ops->mode == MTD_OPS_RAW) 3404 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask); 3405 else 3406 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask); 3407 3408 chip->select_chip(mtd, -1); 3409 3410 if (status) 3411 return status; 3412 3413 ops->oobretlen = ops->ooblen; 3414 3415 return 0; 3416} 3417 3418/** 3419 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band 3420 * @mtd: MTD device structure 3421 * @to: offset to write to 3422 * @ops: oob operation description structure 3423 */ 3424static int nand_write_oob(struct mtd_info *mtd, loff_t to, 3425 struct mtd_oob_ops *ops) 3426{ 3427 int ret = -ENOTSUPP; 3428 3429 ops->retlen = 0; 3430 3431 /* Do not allow writes past end of device */ 3432 if (ops->datbuf && (to + ops->len) > mtd->size) { 3433 pr_debug("%s: attempt to write beyond end of device\n", 3434 __func__); 3435 return -EINVAL; 3436 } 3437 3438 nand_get_device(mtd, FL_WRITING); 3439 3440 switch (ops->mode) { 3441 case MTD_OPS_PLACE_OOB: 3442 case MTD_OPS_AUTO_OOB: 3443 case MTD_OPS_RAW: 3444 break; 3445 3446 default: 3447 goto out; 3448 } 3449 3450 if (!ops->datbuf) 3451 ret = nand_do_write_oob(mtd, to, ops); 3452 else 3453 ret = nand_do_write_ops(mtd, to, ops); 3454 3455out: 3456 nand_release_device(mtd); 3457 return ret; 3458} 3459 3460/** 3461 * single_erase - [GENERIC] NAND standard block erase command function 3462 * @mtd: MTD device structure 3463 * @page: the page address of the block which will be erased 3464 * 3465 * Standard erase command for NAND chips. Returns NAND status. 3466 */ 3467static int single_erase(struct mtd_info *mtd, int page) 3468{ 3469 struct nand_chip *chip = mtd_to_nand(mtd); 3470 unsigned int eraseblock; 3471 3472 /* Send commands to erase a block */ 3473 eraseblock = page >> (chip->phys_erase_shift - chip->page_shift); 3474 3475 return nand_erase_op(chip, eraseblock); 3476} 3477 3478/** 3479 * nand_erase - [MTD Interface] erase block(s) 3480 * @mtd: MTD device structure 3481 * @instr: erase instruction 3482 * 3483 * Erase one ore more blocks. 3484 */ 3485static int nand_erase(struct mtd_info *mtd, struct erase_info *instr) 3486{ 3487 return nand_erase_nand(mtd, instr, 0); 3488} 3489 3490/** 3491 * nand_erase_nand - [INTERN] erase block(s) 3492 * @mtd: MTD device structure 3493 * @instr: erase instruction 3494 * @allowbbt: allow erasing the bbt area 3495 * 3496 * Erase one ore more blocks. 3497 */ 3498int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 3499 int allowbbt) 3500{ 3501 int page, status, pages_per_block, ret, chipnr; 3502 struct nand_chip *chip = mtd_to_nand(mtd); 3503 loff_t len; 3504 3505 pr_debug("%s: start = 0x%012llx, len = %llu\n", 3506 __func__, (unsigned long long)instr->addr, 3507 (unsigned long long)instr->len); 3508 3509 if (check_offs_len(mtd, instr->addr, instr->len)) 3510 return -EINVAL; 3511 3512 /* Grab the lock and see if the device is available */ 3513 nand_get_device(mtd, FL_ERASING); 3514 3515 /* Shift to get first page */ 3516 page = (int)(instr->addr >> chip->page_shift); 3517 chipnr = (int)(instr->addr >> chip->chip_shift); 3518 3519 /* Calculate pages in each block */ 3520 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift); 3521 3522 /* Select the NAND device */ 3523 chip->select_chip(mtd, chipnr); 3524 3525 /* Check, if it is write protected */ 3526 if (nand_check_wp(mtd)) { 3527 pr_debug("%s: device is write protected!\n", 3528 __func__); 3529 instr->state = MTD_ERASE_FAILED; 3530 goto erase_exit; 3531 } 3532 3533 /* Loop through the pages */ 3534 len = instr->len; 3535 3536 instr->state = MTD_ERASING; 3537 3538 while (len) { 3539 schedule(); 3540 3541 /* Check if we have a bad block, we do not erase bad blocks! */ 3542 if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) << 3543 chip->page_shift, allowbbt)) { 3544 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n", 3545 __func__, page); 3546 instr->state = MTD_ERASE_FAILED; 3547 instr->fail_addr = 3548 ((loff_t)page << chip->page_shift); 3549 goto erase_exit; 3550 } 3551 3552 /* 3553 * Invalidate the page cache, if we erase the block which 3554 * contains the current cached page. 3555 */ 3556 if (page <= chip->pagebuf && chip->pagebuf < 3557 (page + pages_per_block)) 3558 chip->pagebuf = -1; 3559 3560 status = chip->erase(mtd, page & chip->pagemask); 3561 3562 /* See if block erase succeeded */ 3563 if (status & NAND_STATUS_FAIL) { 3564 pr_debug("%s: failed erase, page 0x%08x\n", 3565 __func__, page); 3566 instr->state = MTD_ERASE_FAILED; 3567 instr->fail_addr = 3568 ((loff_t)page << chip->page_shift); 3569 goto erase_exit; 3570 } 3571 3572 /* Increment page address and decrement length */ 3573 len -= (1ULL << chip->phys_erase_shift); 3574 page += pages_per_block; 3575 3576 /* Check, if we cross a chip boundary */ 3577 if (len && !(page & chip->pagemask)) { 3578 chipnr++; 3579 chip->select_chip(mtd, -1); 3580 chip->select_chip(mtd, chipnr); 3581 } 3582 } 3583 instr->state = MTD_ERASE_DONE; 3584 3585erase_exit: 3586 3587 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; 3588 3589 /* Deselect and wake up anyone waiting on the device */ 3590 chip->select_chip(mtd, -1); 3591 nand_release_device(mtd); 3592 3593 /* Return more or less happy */ 3594 return ret; 3595} 3596 3597/** 3598 * nand_sync - [MTD Interface] sync 3599 * @mtd: MTD device structure 3600 * 3601 * Sync is actually a wait for chip ready function. 3602 */ 3603static void nand_sync(struct mtd_info *mtd) 3604{ 3605 pr_debug("%s: called\n", __func__); 3606 3607 /* Grab the lock and see if the device is available */ 3608 nand_get_device(mtd, FL_SYNCING); 3609 /* Release it and go back */ 3610 nand_release_device(mtd); 3611} 3612 3613/** 3614 * nand_block_isbad - [MTD Interface] Check if block at offset is bad 3615 * @mtd: MTD device structure 3616 * @offs: offset relative to mtd start 3617 */ 3618static int nand_block_isbad(struct mtd_info *mtd, loff_t offs) 3619{ 3620 struct nand_chip *chip = mtd_to_nand(mtd); 3621 int chipnr = (int)(offs >> chip->chip_shift); 3622 int ret; 3623 3624 /* Select the NAND device */ 3625 nand_get_device(mtd, FL_READING); 3626 chip->select_chip(mtd, chipnr); 3627 3628 ret = nand_block_checkbad(mtd, offs, 0); 3629 3630 chip->select_chip(mtd, -1); 3631 nand_release_device(mtd); 3632 3633 return ret; 3634} 3635 3636/** 3637 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad 3638 * @mtd: MTD device structure 3639 * @ofs: offset relative to mtd start 3640 */ 3641static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs) 3642{ 3643 int ret; 3644 3645 ret = nand_block_isbad(mtd, ofs); 3646 if (ret) { 3647 /* If it was bad already, return success and do nothing */ 3648 if (ret > 0) 3649 return 0; 3650 return ret; 3651 } 3652 3653 return nand_block_markbad_lowlevel(mtd, ofs); 3654} 3655 3656/** 3657 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand 3658 * @mtd: MTD device structure 3659 * @chip: nand chip info structure 3660 * @addr: feature address. 3661 * @subfeature_param: the subfeature parameters, a four bytes array. 3662 */ 3663static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip, 3664 int addr, uint8_t *subfeature_param) 3665{ 3666#ifdef CONFIG_SYS_NAND_ONFI_DETECTION 3667 if (!chip->onfi_version || 3668 !(le16_to_cpu(chip->onfi_params.opt_cmd) 3669 & ONFI_OPT_CMD_SET_GET_FEATURES)) 3670 return -ENOTSUPP; 3671#endif 3672 3673 return nand_set_features_op(chip, addr, subfeature_param); 3674} 3675 3676/** 3677 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand 3678 * @mtd: MTD device structure 3679 * @chip: nand chip info structure 3680 * @addr: feature address. 3681 * @subfeature_param: the subfeature parameters, a four bytes array. 3682 */ 3683static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip, 3684 int addr, uint8_t *subfeature_param) 3685{ 3686#ifdef CONFIG_SYS_NAND_ONFI_DETECTION 3687 if (!chip->onfi_version || 3688 !(le16_to_cpu(chip->onfi_params.opt_cmd) 3689 & ONFI_OPT_CMD_SET_GET_FEATURES)) 3690 return -ENOTSUPP; 3691#endif 3692 3693 return nand_get_features_op(chip, addr, subfeature_param); 3694} 3695 3696/* Set default functions */ 3697static void nand_set_defaults(struct nand_chip *chip, int busw) 3698{ 3699 /* check for proper chip_delay setup, set 20us if not */ 3700 if (!chip->chip_delay) 3701 chip->chip_delay = 20; 3702 3703 /* check, if a user supplied command function given */ 3704 if (chip->cmdfunc == NULL) 3705 chip->cmdfunc = nand_command; 3706 3707 /* check, if a user supplied wait function given */ 3708 if (chip->waitfunc == NULL) 3709 chip->waitfunc = nand_wait; 3710 3711 if (!chip->select_chip) 3712 chip->select_chip = nand_select_chip; 3713 3714 /* set for ONFI nand */ 3715 if (!chip->onfi_set_features) 3716 chip->onfi_set_features = nand_onfi_set_features; 3717 if (!chip->onfi_get_features) 3718 chip->onfi_get_features = nand_onfi_get_features; 3719 3720 /* If called twice, pointers that depend on busw may need to be reset */ 3721 if (!chip->read_byte || chip->read_byte == nand_read_byte) 3722 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; 3723 if (!chip->read_word) 3724 chip->read_word = nand_read_word; 3725 if (!chip->block_bad) 3726 chip->block_bad = nand_block_bad; 3727 if (!chip->block_markbad) 3728 chip->block_markbad = nand_default_block_markbad; 3729 if (!chip->write_buf || chip->write_buf == nand_write_buf) 3730 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; 3731 if (!chip->write_byte || chip->write_byte == nand_write_byte) 3732 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte; 3733 if (!chip->read_buf || chip->read_buf == nand_read_buf) 3734 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; 3735 3736#ifndef CONFIG_SPL_BUILD 3737 if (!chip->scan_bbt) 3738 chip->scan_bbt = nand_default_bbt; 3739#endif 3740 3741 if (!chip->controller) { 3742 chip->controller = &chip->hwcontrol; 3743 spin_lock_init(&chip->controller->lock); 3744 init_waitqueue_head(&chip->controller->wq); 3745 } 3746 3747 if (!chip->buf_align) 3748 chip->buf_align = 1; 3749} 3750 3751/* Sanitize ONFI strings so we can safely print them */ 3752static void sanitize_string(char *s, size_t len) 3753{ 3754 ssize_t i; 3755 3756 /* Null terminate */ 3757 s[len - 1] = 0; 3758 3759 /* Remove non printable chars */ 3760 for (i = 0; i < len - 1; i++) { 3761 if (s[i] < ' ' || s[i] > 127) 3762 s[i] = '?'; 3763 } 3764 3765 /* Remove trailing spaces */ 3766 strim(s); 3767} 3768 3769static u16 onfi_crc16(u16 crc, u8 const *p, size_t len) 3770{ 3771 int i; 3772 while (len--) { 3773 crc ^= *p++ << 8; 3774 for (i = 0; i < 8; i++) 3775 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0); 3776 } 3777 3778 return crc; 3779} 3780 3781#ifdef CONFIG_SYS_NAND_ONFI_DETECTION 3782/* Parse the Extended Parameter Page. */ 3783static int nand_flash_detect_ext_param_page(struct mtd_info *mtd, 3784 struct nand_chip *chip, struct nand_onfi_params *p) 3785{ 3786 struct onfi_ext_param_page *ep; 3787 struct onfi_ext_section *s; 3788 struct onfi_ext_ecc_info *ecc; 3789 uint8_t *cursor; 3790 int ret; 3791 int len; 3792 int i; 3793 3794 len = le16_to_cpu(p->ext_param_page_length) * 16; 3795 ep = kmalloc(len, GFP_KERNEL); 3796 if (!ep) 3797 return -ENOMEM; 3798 3799 /* Send our own NAND_CMD_PARAM. */ 3800 ret = nand_read_param_page_op(chip, 0, NULL, 0); 3801 if (ret) 3802 goto ext_out; 3803 3804 /* Use the Change Read Column command to skip the ONFI param pages. */ 3805 ret = nand_change_read_column_op(chip, 3806 sizeof(*p) * p->num_of_param_pages, 3807 ep, len, true); 3808 if (ret) 3809 goto ext_out; 3810 3811 ret = -EINVAL; 3812 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2) 3813 != le16_to_cpu(ep->crc))) { 3814 pr_debug("fail in the CRC.\n"); 3815 goto ext_out; 3816 } 3817 3818 /* 3819 * Check the signature. 3820 * Do not strictly follow the ONFI spec, maybe changed in future. 3821 */ 3822 if (strncmp((char *)ep->sig, "EPPS", 4)) { 3823 pr_debug("The signature is invalid.\n"); 3824 goto ext_out; 3825 } 3826 3827 /* find the ECC section. */ 3828 cursor = (uint8_t *)(ep + 1); 3829 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) { 3830 s = ep->sections + i; 3831 if (s->type == ONFI_SECTION_TYPE_2) 3832 break; 3833 cursor += s->length * 16; 3834 } 3835 if (i == ONFI_EXT_SECTION_MAX) { 3836 pr_debug("We can not find the ECC section.\n"); 3837 goto ext_out; 3838 } 3839 3840 /* get the info we want. */ 3841 ecc = (struct onfi_ext_ecc_info *)cursor; 3842 3843 if (!ecc->codeword_size) { 3844 pr_debug("Invalid codeword size\n"); 3845 goto ext_out; 3846 } 3847 3848 chip->ecc_strength_ds = ecc->ecc_bits; 3849 chip->ecc_step_ds = 1 << ecc->codeword_size; 3850 ret = 0; 3851 3852ext_out: 3853 kfree(ep); 3854 return ret; 3855} 3856 3857/* 3858 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise. 3859 */ 3860static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip) 3861{ 3862 struct nand_onfi_params *p = &chip->onfi_params; 3863 char id[4]; 3864 int i, ret, val; 3865 3866 /* Try ONFI for unknown chip or LP */ 3867 ret = nand_readid_op(chip, 0x20, id, sizeof(id)); 3868 if (ret || strncmp(id, "ONFI", 4)) 3869 return 0; 3870 3871 ret = nand_read_param_page_op(chip, 0, NULL, 0); 3872 if (ret) 3873 return 0; 3874 3875 for (i = 0; i < 3; i++) { 3876 ret = nand_read_data_op(chip, p, sizeof(*p), true); 3877 if (ret) 3878 return 0; 3879 3880 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) == 3881 le16_to_cpu(p->crc)) { 3882 break; 3883 } 3884 } 3885 3886 if (i == 3) { 3887 pr_err("Could not find valid ONFI parameter page; aborting\n"); 3888 return 0; 3889 } 3890 3891 /* Check version */ 3892 val = le16_to_cpu(p->revision); 3893 if (val & (1 << 5)) 3894 chip->onfi_version = 23; 3895 else if (val & (1 << 4)) 3896 chip->onfi_version = 22; 3897 else if (val & (1 << 3)) 3898 chip->onfi_version = 21; 3899 else if (val & (1 << 2)) 3900 chip->onfi_version = 20; 3901 else if (val & (1 << 1)) 3902 chip->onfi_version = 10; 3903 3904 if (!chip->onfi_version) { 3905 pr_info("unsupported ONFI version: %d\n", val); 3906 return 0; 3907 } 3908 3909 sanitize_string(p->manufacturer, sizeof(p->manufacturer)); 3910 sanitize_string(p->model, sizeof(p->model)); 3911 if (!mtd->name) 3912 mtd->name = p->model; 3913 3914 mtd->writesize = le32_to_cpu(p->byte_per_page); 3915 3916 /* 3917 * pages_per_block and blocks_per_lun may not be a power-of-2 size 3918 * (don't ask me who thought of this...). MTD assumes that these 3919 * dimensions will be power-of-2, so just truncate the remaining area. 3920 */ 3921 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); 3922 mtd->erasesize *= mtd->writesize; 3923 3924 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); 3925 3926 /* See erasesize comment */ 3927 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); 3928 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; 3929 chip->bits_per_cell = p->bits_per_cell; 3930 3931 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS) 3932 chip->options |= NAND_BUSWIDTH_16; 3933 3934 if (p->ecc_bits != 0xff) { 3935 chip->ecc_strength_ds = p->ecc_bits; 3936 chip->ecc_step_ds = 512; 3937 } else if (chip->onfi_version >= 21 && 3938 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) { 3939 3940 /* 3941 * The nand_flash_detect_ext_param_page() uses the 3942 * Change Read Column command which maybe not supported 3943 * by the chip->cmdfunc. So try to update the chip->cmdfunc 3944 * now. We do not replace user supplied command function. 3945 */ 3946 if (mtd->writesize > 512 && chip->cmdfunc == nand_command) 3947 chip->cmdfunc = nand_command_lp; 3948 3949 /* The Extended Parameter Page is supported since ONFI 2.1. */ 3950 if (nand_flash_detect_ext_param_page(mtd, chip, p)) 3951 pr_warn("Failed to detect ONFI extended param page\n"); 3952 } else { 3953 pr_warn("Could not retrieve ONFI ECC requirements\n"); 3954 } 3955 3956 return 1; 3957} 3958#else 3959static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip) 3960{ 3961 return 0; 3962} 3963#endif 3964 3965/* 3966 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise. 3967 */ 3968static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip) 3969{ 3970 struct nand_jedec_params *p = &chip->jedec_params; 3971 struct jedec_ecc_info *ecc; 3972 char id[5]; 3973 int i, val, ret; 3974 3975 /* Try JEDEC for unknown chip or LP */ 3976 ret = nand_readid_op(chip, 0x40, id, sizeof(id)); 3977 if (ret || strncmp(id, "JEDEC", sizeof(id))) 3978 return 0; 3979 3980 ret = nand_read_param_page_op(chip, 0x40, NULL, 0); 3981 if (ret) 3982 return 0; 3983 3984 for (i = 0; i < 3; i++) { 3985 ret = nand_read_data_op(chip, p, sizeof(*p), true); 3986 if (ret) 3987 return 0; 3988 3989 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) == 3990 le16_to_cpu(p->crc)) 3991 break; 3992 } 3993 3994 if (i == 3) { 3995 pr_err("Could not find valid JEDEC parameter page; aborting\n"); 3996 return 0; 3997 } 3998 3999 /* Check version */ 4000 val = le16_to_cpu(p->revision); 4001 if (val & (1 << 2)) 4002 chip->jedec_version = 10; 4003 else if (val & (1 << 1)) 4004 chip->jedec_version = 1; /* vendor specific version */ 4005 4006 if (!chip->jedec_version) { 4007 pr_info("unsupported JEDEC version: %d\n", val); 4008 return 0; 4009 } 4010 4011 sanitize_string(p->manufacturer, sizeof(p->manufacturer)); 4012 sanitize_string(p->model, sizeof(p->model)); 4013 if (!mtd->name) 4014 mtd->name = p->model; 4015 4016 mtd->writesize = le32_to_cpu(p->byte_per_page); 4017 4018 /* Please reference to the comment for nand_flash_detect_onfi. */ 4019 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1); 4020 mtd->erasesize *= mtd->writesize; 4021 4022 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page); 4023 4024 /* Please reference to the comment for nand_flash_detect_onfi. */ 4025 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1); 4026 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count; 4027 chip->bits_per_cell = p->bits_per_cell; 4028 4029 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS) 4030 chip->options |= NAND_BUSWIDTH_16; 4031 4032 /* ECC info */ 4033 ecc = &p->ecc_info[0]; 4034 4035 if (ecc->codeword_size >= 9) { 4036 chip->ecc_strength_ds = ecc->ecc_bits; 4037 chip->ecc_step_ds = 1 << ecc->codeword_size; 4038 } else { 4039 pr_warn("Invalid codeword size\n"); 4040 } 4041 4042 return 1; 4043} 4044 4045/* 4046 * nand_id_has_period - Check if an ID string has a given wraparound period 4047 * @id_data: the ID string 4048 * @arrlen: the length of the @id_data array 4049 * @period: the period of repitition 4050 * 4051 * Check if an ID string is repeated within a given sequence of bytes at 4052 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a 4053 * period of 3). This is a helper function for nand_id_len(). Returns non-zero 4054 * if the repetition has a period of @period; otherwise, returns zero. 4055 */ 4056static int nand_id_has_period(u8 *id_data, int arrlen, int period) 4057{ 4058 int i, j; 4059 for (i = 0; i < period; i++) 4060 for (j = i + period; j < arrlen; j += period) 4061 if (id_data[i] != id_data[j]) 4062 return 0; 4063 return 1; 4064} 4065 4066/* 4067 * nand_id_len - Get the length of an ID string returned by CMD_READID 4068 * @id_data: the ID string 4069 * @arrlen: the length of the @id_data array 4070 4071 * Returns the length of the ID string, according to known wraparound/trailing 4072 * zero patterns. If no pattern exists, returns the length of the array. 4073 */ 4074static int nand_id_len(u8 *id_data, int arrlen) 4075{ 4076 int last_nonzero, period; 4077 4078 /* Find last non-zero byte */ 4079 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--) 4080 if (id_data[last_nonzero]) 4081 break; 4082 4083 /* All zeros */ 4084 if (last_nonzero < 0) 4085 return 0; 4086 4087 /* Calculate wraparound period */ 4088 for (period = 1; period < arrlen; period++) 4089 if (nand_id_has_period(id_data, arrlen, period)) 4090 break; 4091 4092 /* There's a repeated pattern */ 4093 if (period < arrlen) 4094 return period; 4095 4096 /* There are trailing zeros */ 4097 if (last_nonzero < arrlen - 1) 4098 return last_nonzero + 1; 4099 4100 /* No pattern detected */ 4101 return arrlen; 4102} 4103 4104/* Extract the bits of per cell from the 3rd byte of the extended ID */ 4105static int nand_get_bits_per_cell(u8 cellinfo) 4106{ 4107 int bits; 4108 4109 bits = cellinfo & NAND_CI_CELLTYPE_MSK; 4110 bits >>= NAND_CI_CELLTYPE_SHIFT; 4111 return bits + 1; 4112} 4113 4114/* 4115 * Many new NAND share similar device ID codes, which represent the size of the 4116 * chip. The rest of the parameters must be decoded according to generic or 4117 * manufacturer-specific "extended ID" decoding patterns. 4118 */ 4119void nand_decode_ext_id(struct nand_chip *chip) 4120{ 4121 struct mtd_info *mtd = nand_to_mtd(chip); 4122 int extid; 4123 /* The 3rd id byte holds MLC / multichip data */ 4124 chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); 4125 /* The 4th id byte is the important one */ 4126 extid = chip->id.data[3]; 4127 4128 /* Calc pagesize */ 4129 mtd->writesize = 1024 << (extid & 0x03); 4130 extid >>= 2; 4131 /* Calc oobsize */ 4132 mtd->oobsize = (8 << (extid & 0x01)) * 4133 (mtd->writesize >> 9); 4134 extid >>= 2; 4135 /* Calc blocksize. Blocksize is multiples of 64KiB */ 4136 mtd->erasesize = (64 * 1024) << (extid & 0x03); 4137 extid >>= 2; 4138 /* Get buswidth information */ 4139 /* Get buswidth information */ 4140 if (extid & 0x1) 4141 chip->options |= NAND_BUSWIDTH_16; 4142} 4143EXPORT_SYMBOL_GPL(nand_decode_ext_id); 4144 4145/* 4146 * Manufacturer detection. Only used when the NAND is not ONFI or JEDEC 4147 * compliant and does not have a full-id or legacy-id entry in the nand_ids 4148 * table. 4149 */ 4150static void nand_manufacturer_detect(struct nand_chip *chip) 4151{ 4152 /* 4153 * Try manufacturer detection if available and use 4154 * nand_decode_ext_id() otherwise. 4155 */ 4156 if (chip->manufacturer.desc && chip->manufacturer.desc->ops && 4157 chip->manufacturer.desc->ops->detect) { 4158 /* The 3rd id byte holds MLC / multichip data */ 4159 chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); 4160 chip->manufacturer.desc->ops->detect(chip); 4161 } else { 4162 nand_decode_ext_id(chip); 4163 } 4164} 4165 4166/* 4167 * Manufacturer initialization. This function is called for all NANDs including 4168 * ONFI and JEDEC compliant ones. 4169 * Manufacturer drivers should put all their specific initialization code in 4170 * their ->init() hook. 4171 */ 4172static int nand_manufacturer_init(struct nand_chip *chip) 4173{ 4174 if (!chip->manufacturer.desc || !chip->manufacturer.desc->ops || 4175 !chip->manufacturer.desc->ops->init) 4176 return 0; 4177 4178 return chip->manufacturer.desc->ops->init(chip); 4179} 4180 4181/* 4182 * Old devices have chip data hardcoded in the device ID table. nand_decode_id 4183 * decodes a matching ID table entry and assigns the MTD size parameters for 4184 * the chip. 4185 */ 4186static void nand_decode_id(struct nand_chip *chip, struct nand_flash_dev *type) 4187{ 4188 struct mtd_info *mtd = nand_to_mtd(chip); 4189 4190 mtd->erasesize = type->erasesize; 4191 mtd->writesize = type->pagesize; 4192 mtd->oobsize = mtd->writesize / 32; 4193 4194 /* All legacy ID NAND are small-page, SLC */ 4195 chip->bits_per_cell = 1; 4196} 4197 4198/* 4199 * Set the bad block marker/indicator (BBM/BBI) patterns according to some 4200 * heuristic patterns using various detected parameters (e.g., manufacturer, 4201 * page size, cell-type information). 4202 */ 4203static void nand_decode_bbm_options(struct mtd_info *mtd, 4204 struct nand_chip *chip) 4205{ 4206 /* Set the bad block position */ 4207 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16)) 4208 chip->badblockpos = NAND_LARGE_BADBLOCK_POS; 4209 else 4210 chip->badblockpos = NAND_SMALL_BADBLOCK_POS; 4211} 4212 4213static inline bool is_full_id_nand(struct nand_flash_dev *type) 4214{ 4215 return type->id_len; 4216} 4217 4218static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip, 4219 struct nand_flash_dev *type) 4220{ 4221 if (!strncmp((char *)type->id, (char *)chip->id.data, type->id_len)) { 4222 mtd->writesize = type->pagesize; 4223 mtd->erasesize = type->erasesize; 4224 mtd->oobsize = type->oobsize; 4225 4226 chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); 4227 chip->chipsize = (uint64_t)type->chipsize << 20; 4228 chip->options |= type->options; 4229 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type); 4230 chip->ecc_step_ds = NAND_ECC_STEP(type); 4231 chip->onfi_timing_mode_default = 4232 type->onfi_timing_mode_default; 4233 4234 if (!mtd->name) 4235 mtd->name = type->name; 4236 4237 return true; 4238 } 4239 return false; 4240} 4241 4242/** 4243 * nand_get_manufacturer_desc - Get manufacturer information from the 4244 * manufacturer ID 4245 * @id: manufacturer ID 4246 * 4247 * Returns a nand_manufacturer_desc object if the manufacturer is defined 4248 * in the NAND manufacturers database, NULL otherwise. 4249 */ 4250static const struct nand_manufacturer *nand_get_manufacturer_desc(u8 id) 4251{ 4252 int i; 4253 4254 for (i = 0; nand_manuf_ids[i].id != 0x0; i++) { 4255 if (nand_manuf_ids[i].id == id) 4256 return &nand_manuf_ids[i]; 4257 } 4258 4259 return NULL; 4260} 4261 4262/* 4263 * Get the flash and manufacturer id and lookup if the type is supported. 4264 */ 4265int nand_detect(struct nand_chip *chip, int *maf_id, 4266 int *dev_id, struct nand_flash_dev *type) 4267{ 4268 struct mtd_info *mtd = nand_to_mtd(chip); 4269 const struct nand_manufacturer *manufacturer_desc; 4270 int busw, ret; 4271 u8 *id_data = chip->id.data; 4272 4273 /* 4274 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) 4275 * after power-up. 4276 */ 4277 ret = nand_reset(chip, 0); 4278 if (ret) 4279 return ret; 4280 4281 /* Select the device */ 4282 chip->select_chip(mtd, 0); 4283 4284 /* Send the command for reading device ID */ 4285 ret = nand_readid_op(chip, 0, id_data, 2); 4286 if (ret) 4287 return ret; 4288 4289 /* Read manufacturer and device IDs */ 4290 *maf_id = id_data[0]; 4291 *dev_id = id_data[1]; 4292 4293 /* 4294 * Try again to make sure, as some systems the bus-hold or other 4295 * interface concerns can cause random data which looks like a 4296 * possibly credible NAND flash to appear. If the two results do 4297 * not match, ignore the device completely. 4298 */ 4299 4300 /* Read entire ID string */ 4301 ret = nand_readid_op(chip, 0, id_data, 8); 4302 if (ret) 4303 return ret; 4304 4305 if (id_data[0] != *maf_id || id_data[1] != *dev_id) { 4306 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n", 4307 *maf_id, *dev_id, id_data[0], id_data[1]); 4308 return -ENODEV; 4309 } 4310 4311 chip->id.len = nand_id_len(id_data, ARRAY_SIZE(chip->id.data)); 4312 4313 /* Try to identify manufacturer */ 4314 manufacturer_desc = nand_get_manufacturer_desc(*maf_id); 4315 chip->manufacturer.desc = manufacturer_desc; 4316 4317 if (!type) 4318 type = nand_flash_ids; 4319 4320 /* 4321 * Save the NAND_BUSWIDTH_16 flag before letting auto-detection logic 4322 * override it. 4323 * This is required to make sure initial NAND bus width set by the 4324 * NAND controller driver is coherent with the real NAND bus width 4325 * (extracted by auto-detection code). 4326 */ 4327 busw = chip->options & NAND_BUSWIDTH_16; 4328 4329 /* 4330 * The flag is only set (never cleared), reset it to its default value 4331 * before starting auto-detection. 4332 */ 4333 chip->options &= ~NAND_BUSWIDTH_16; 4334 4335 for (; type->name != NULL; type++) { 4336 if (is_full_id_nand(type)) { 4337 if (find_full_id_nand(mtd, chip, type)) 4338 goto ident_done; 4339 } else if (*dev_id == type->dev_id) { 4340 break; 4341 } 4342 } 4343 4344 chip->onfi_version = 0; 4345 if (!type->name || !type->pagesize) { 4346 /* Check if the chip is ONFI compliant */ 4347 if (nand_flash_detect_onfi(mtd, chip)) 4348 goto ident_done; 4349 4350 /* Check if the chip is JEDEC compliant */ 4351 if (nand_flash_detect_jedec(mtd, chip)) 4352 goto ident_done; 4353 } 4354 4355 if (!type->name) 4356 return -ENODEV; 4357 4358 if (!mtd->name) 4359 mtd->name = type->name; 4360 4361 chip->chipsize = (uint64_t)type->chipsize << 20; 4362 4363 if (!type->pagesize) { 4364 nand_manufacturer_detect(chip); 4365 } else { 4366 nand_decode_id(chip, type); 4367 } 4368 4369 /* Get chip options */ 4370 chip->options |= type->options; 4371 4372ident_done: 4373 4374 if (chip->options & NAND_BUSWIDTH_AUTO) { 4375 WARN_ON(chip->options & NAND_BUSWIDTH_16); 4376 chip->options |= busw; 4377 nand_set_defaults(chip, busw); 4378 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) { 4379 /* 4380 * Check, if buswidth is correct. Hardware drivers should set 4381 * chip correct! 4382 */ 4383 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", 4384 *maf_id, *dev_id); 4385 pr_info("%s %s\n", manufacturer_desc->name, mtd->name); 4386 pr_warn("bus width %d instead %d bit\n", 4387 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8, 4388 busw ? 16 : 8); 4389 return -EINVAL; 4390 } 4391 4392 nand_decode_bbm_options(mtd, chip); 4393 4394 /* Calculate the address shift from the page size */ 4395 chip->page_shift = ffs(mtd->writesize) - 1; 4396 /* Convert chipsize to number of pages per chip -1 */ 4397 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1; 4398 4399 chip->bbt_erase_shift = chip->phys_erase_shift = 4400 ffs(mtd->erasesize) - 1; 4401 if (chip->chipsize & 0xffffffff) 4402 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1; 4403 else { 4404 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)); 4405 chip->chip_shift += 32 - 1; 4406 } 4407 4408 if (chip->chip_shift - chip->page_shift > 16) 4409 chip->options |= NAND_ROW_ADDR_3; 4410 4411 chip->badblockbits = 8; 4412 chip->erase = single_erase; 4413 4414 /* Do not replace user supplied command function! */ 4415 if (mtd->writesize > 512 && chip->cmdfunc == nand_command) 4416 chip->cmdfunc = nand_command_lp; 4417 4418 ret = nand_manufacturer_init(chip); 4419 if (ret) 4420 return ret; 4421 4422 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n", 4423 *maf_id, *dev_id); 4424 4425#ifdef CONFIG_SYS_NAND_ONFI_DETECTION 4426 if (chip->onfi_version) 4427 pr_info("%s %s\n", manufacturer_desc->name, 4428 chip->onfi_params.model); 4429 else if (chip->jedec_version) 4430 pr_info("%s %s\n", manufacturer_desc->name, 4431 chip->jedec_params.model); 4432 else if (manufacturer_desc) 4433 pr_info("%s %s\n", manufacturer_desc->name, type->name); 4434#else 4435 if (chip->jedec_version) 4436 pr_info("%s %s\n", manufacturer_desc->name, 4437 chip->jedec_params.model); 4438 else if (manufacturer_desc) 4439 pr_info("%s %s\n", manufacturer_desc->name, type->name); 4440#endif 4441 4442 pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n", 4443 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC", 4444 mtd->erasesize >> 10, mtd->writesize, mtd->oobsize); 4445 return 0; 4446} 4447EXPORT_SYMBOL(nand_detect); 4448 4449#if CONFIG_IS_ENABLED(OF_CONTROL) 4450 4451static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode node) 4452{ 4453 int ret, ecc_mode = -1, ecc_strength, ecc_step; 4454 int ecc_algo = NAND_ECC_UNKNOWN; 4455 const char *str; 4456 4457 ret = ofnode_read_s32_default(node, "nand-bus-width", -1); 4458 if (ret == 16) 4459 chip->options |= NAND_BUSWIDTH_16; 4460 4461 if (ofnode_read_bool(node, "nand-on-flash-bbt")) 4462 chip->bbt_options |= NAND_BBT_USE_FLASH; 4463 4464 str = ofnode_read_string(node, "nand-ecc-mode"); 4465 if (str) { 4466 if (!strcmp(str, "none")) 4467 ecc_mode = NAND_ECC_NONE; 4468 else if (!strcmp(str, "soft")) 4469 ecc_mode = NAND_ECC_SOFT; 4470 else if (!strcmp(str, "hw")) 4471 ecc_mode = NAND_ECC_HW; 4472 else if (!strcmp(str, "hw_syndrome")) 4473 ecc_mode = NAND_ECC_HW_SYNDROME; 4474 else if (!strcmp(str, "hw_oob_first")) 4475 ecc_mode = NAND_ECC_HW_OOB_FIRST; 4476 else if (!strcmp(str, "soft_bch")) 4477 ecc_mode = NAND_ECC_SOFT_BCH; 4478 } 4479 4480 str = ofnode_read_string(node, "nand-ecc-algo"); 4481 if (str) { 4482 /* 4483 * If we are in NAND_ECC_SOFT mode, just alter the 4484 * soft mode to BCH here. No change of algorithm. 4485 */ 4486 if (ecc_mode == NAND_ECC_SOFT) { 4487 if (!strcmp(str, "bch")) 4488 ecc_mode = NAND_ECC_SOFT_BCH; 4489 } else { 4490 if (!strcmp(str, "bch")) { 4491 ecc_algo = NAND_ECC_BCH; 4492 } else if (!strcmp(str, "hamming")) { 4493 ecc_algo = NAND_ECC_HAMMING; 4494 } 4495 } 4496 } 4497 4498 ecc_strength = ofnode_read_s32_default(node, 4499 "nand-ecc-strength", -1); 4500 ecc_step = ofnode_read_s32_default(node, 4501 "nand-ecc-step-size", -1); 4502 4503 if ((ecc_step >= 0 && !(ecc_strength >= 0)) || 4504 (!(ecc_step >= 0) && ecc_strength >= 0)) { 4505 pr_err("must set both strength and step size in DT\n"); 4506 return -EINVAL; 4507 } 4508 4509 /* 4510 * Chip drivers may have assigned default algorithms here, 4511 * onlt override it if we have found something explicitly 4512 * specified in the device tree. 4513 */ 4514 if (ecc_algo != NAND_ECC_UNKNOWN) 4515 chip->ecc.algo = ecc_algo; 4516 4517 if (ecc_mode >= 0) 4518 chip->ecc.mode = ecc_mode; 4519 4520 if (ecc_strength >= 0) 4521 chip->ecc.strength = ecc_strength; 4522 4523 if (ecc_step > 0) 4524 chip->ecc.size = ecc_step; 4525 4526 if (ofnode_read_bool(node, "nand-ecc-maximize")) 4527 chip->ecc.options |= NAND_ECC_MAXIMIZE; 4528 4529 return 0; 4530} 4531#else 4532static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode node) 4533{ 4534 return 0; 4535} 4536#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */ 4537 4538/** 4539 * nand_scan_ident - [NAND Interface] Scan for the NAND device 4540 * @mtd: MTD device structure 4541 * @maxchips: number of chips to scan for 4542 * @table: alternative NAND ID table 4543 * 4544 * This is the first phase of the normal nand_scan() function. It reads the 4545 * flash ID and sets up MTD fields accordingly. 4546 * 4547 */ 4548int nand_scan_ident(struct mtd_info *mtd, int maxchips, 4549 struct nand_flash_dev *table) 4550{ 4551 int i, nand_maf_id, nand_dev_id; 4552 struct nand_chip *chip = mtd_to_nand(mtd); 4553 int ret; 4554 4555 if (ofnode_valid(chip->flash_node)) { 4556 ret = nand_dt_init(mtd, chip, chip->flash_node); 4557 if (ret) 4558 return ret; 4559 } 4560 4561 /* Set the default functions */ 4562 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16); 4563 4564 /* Read the flash type */ 4565 ret = nand_detect(chip, &nand_maf_id, &nand_dev_id, table); 4566 4567 if (ret) { 4568 if (!(chip->options & NAND_SCAN_SILENT_NODEV)) 4569 pr_warn("No NAND device found\n"); 4570 chip->select_chip(mtd, -1); 4571 return ret; 4572 } 4573 4574 /* Initialize the ->data_interface field. */ 4575 ret = nand_init_data_interface(chip); 4576 if (ret) 4577 return ret; 4578 4579 /* 4580 * Setup the data interface correctly on the chip and controller side. 4581 * This explicit call to nand_setup_data_interface() is only required 4582 * for the first die, because nand_reset() has been called before 4583 * ->data_interface and ->default_onfi_timing_mode were set. 4584 * For the other dies, nand_reset() will automatically switch to the 4585 * best mode for us. 4586 */ 4587 ret = nand_setup_data_interface(chip, 0); 4588 if (ret) 4589 return ret; 4590 4591 chip->select_chip(mtd, -1); 4592 4593 /* Check for a chip array */ 4594 for (i = 1; i < maxchips; i++) { 4595 u8 id[2]; 4596 4597 /* See comment in nand_detect for reset */ 4598 nand_reset(chip, i); 4599 4600 chip->select_chip(mtd, i); 4601 /* Send the command for reading device ID */ 4602 nand_readid_op(chip, 0, id, sizeof(id)); 4603 4604 /* Read manufacturer and device IDs */ 4605 if (nand_maf_id != id[0] || nand_dev_id != id[1]) { 4606 chip->select_chip(mtd, -1); 4607 break; 4608 } 4609 chip->select_chip(mtd, -1); 4610 } 4611 4612#ifdef DEBUG 4613 if (i > 1) 4614 pr_info("%d chips detected\n", i); 4615#endif 4616 4617 /* Store the number of chips and calc total size for mtd */ 4618 chip->numchips = i; 4619 mtd->size = i * chip->chipsize; 4620 4621 return 0; 4622} 4623EXPORT_SYMBOL(nand_scan_ident); 4624 4625/** 4626 * nand_check_ecc_caps - check the sanity of preset ECC settings 4627 * @chip: nand chip info structure 4628 * @caps: ECC caps info structure 4629 * @oobavail: OOB size that the ECC engine can use 4630 * 4631 * When ECC step size and strength are already set, check if they are supported 4632 * by the controller and the calculated ECC bytes fit within the chip's OOB. 4633 * On success, the calculated ECC bytes is set. 4634 */ 4635int nand_check_ecc_caps(struct nand_chip *chip, 4636 const struct nand_ecc_caps *caps, int oobavail) 4637{ 4638 struct mtd_info *mtd = nand_to_mtd(chip); 4639 const struct nand_ecc_step_info *stepinfo; 4640 int preset_step = chip->ecc.size; 4641 int preset_strength = chip->ecc.strength; 4642 int nsteps, ecc_bytes; 4643 int i, j; 4644 4645 if (WARN_ON(oobavail < 0)) 4646 return -EINVAL; 4647 4648 if (!preset_step || !preset_strength) 4649 return -ENODATA; 4650 4651 nsteps = mtd->writesize / preset_step; 4652 4653 for (i = 0; i < caps->nstepinfos; i++) { 4654 stepinfo = &caps->stepinfos[i]; 4655 4656 if (stepinfo->stepsize != preset_step) 4657 continue; 4658 4659 for (j = 0; j < stepinfo->nstrengths; j++) { 4660 if (stepinfo->strengths[j] != preset_strength) 4661 continue; 4662 4663 ecc_bytes = caps->calc_ecc_bytes(preset_step, 4664 preset_strength); 4665 if (WARN_ON_ONCE(ecc_bytes < 0)) 4666 return ecc_bytes; 4667 4668 if (ecc_bytes * nsteps > oobavail) { 4669 pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB", 4670 preset_step, preset_strength); 4671 return -ENOSPC; 4672 } 4673 4674 chip->ecc.bytes = ecc_bytes; 4675 4676 return 0; 4677 } 4678 } 4679 4680 pr_err("ECC (step, strength) = (%d, %d) not supported on this controller", 4681 preset_step, preset_strength); 4682 4683 return -ENOTSUPP; 4684} 4685EXPORT_SYMBOL_GPL(nand_check_ecc_caps); 4686 4687/** 4688 * nand_match_ecc_req - meet the chip's requirement with least ECC bytes 4689 * @chip: nand chip info structure 4690 * @caps: ECC engine caps info structure 4691 * @oobavail: OOB size that the ECC engine can use 4692 * 4693 * If a chip's ECC requirement is provided, try to meet it with the least 4694 * number of ECC bytes (i.e. with the largest number of OOB-free bytes). 4695 * On success, the chosen ECC settings are set. 4696 */ 4697int nand_match_ecc_req(struct nand_chip *chip, 4698 const struct nand_ecc_caps *caps, int oobavail) 4699{ 4700 struct mtd_info *mtd = nand_to_mtd(chip); 4701 const struct nand_ecc_step_info *stepinfo; 4702 int req_step = chip->ecc_step_ds; 4703 int req_strength = chip->ecc_strength_ds; 4704 int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total; 4705 int best_step, best_strength, best_ecc_bytes; 4706 int best_ecc_bytes_total = INT_MAX; 4707 int i, j; 4708 4709 if (WARN_ON(oobavail < 0)) 4710 return -EINVAL; 4711 4712 /* No information provided by the NAND chip */ 4713 if (!req_step || !req_strength) 4714 return -ENOTSUPP; 4715 4716 /* number of correctable bits the chip requires in a page */ 4717 req_corr = mtd->writesize / req_step * req_strength; 4718 4719 for (i = 0; i < caps->nstepinfos; i++) { 4720 stepinfo = &caps->stepinfos[i]; 4721 step_size = stepinfo->stepsize; 4722 4723 for (j = 0; j < stepinfo->nstrengths; j++) { 4724 strength = stepinfo->strengths[j]; 4725 4726 /* 4727 * If both step size and strength are smaller than the 4728 * chip's requirement, it is not easy to compare the 4729 * resulted reliability. 4730 */ 4731 if (step_size < req_step && strength < req_strength) 4732 continue; 4733 4734 if (mtd->writesize % step_size) 4735 continue; 4736 4737 nsteps = mtd->writesize / step_size; 4738 4739 ecc_bytes = caps->calc_ecc_bytes(step_size, strength); 4740 if (WARN_ON_ONCE(ecc_bytes < 0)) 4741 continue; 4742 ecc_bytes_total = ecc_bytes * nsteps; 4743 4744 if (ecc_bytes_total > oobavail || 4745 strength * nsteps < req_corr) 4746 continue; 4747 4748 /* 4749 * We assume the best is to meet the chip's requrement 4750 * with the least number of ECC bytes. 4751 */ 4752 if (ecc_bytes_total < best_ecc_bytes_total) { 4753 best_ecc_bytes_total = ecc_bytes_total; 4754 best_step = step_size; 4755 best_strength = strength; 4756 best_ecc_bytes = ecc_bytes; 4757 } 4758 } 4759 } 4760 4761 if (best_ecc_bytes_total == INT_MAX) 4762 return -ENOTSUPP; 4763 4764 chip->ecc.size = best_step; 4765 chip->ecc.strength = best_strength; 4766 chip->ecc.bytes = best_ecc_bytes; 4767 4768 return 0; 4769} 4770EXPORT_SYMBOL_GPL(nand_match_ecc_req); 4771 4772/** 4773 * nand_maximize_ecc - choose the max ECC strength available 4774 * @chip: nand chip info structure 4775 * @caps: ECC engine caps info structure 4776 * @oobavail: OOB size that the ECC engine can use 4777 * 4778 * Choose the max ECC strength that is supported on the controller, and can fit 4779 * within the chip's OOB. On success, the chosen ECC settings are set. 4780 */ 4781int nand_maximize_ecc(struct nand_chip *chip, 4782 const struct nand_ecc_caps *caps, int oobavail) 4783{ 4784 struct mtd_info *mtd = nand_to_mtd(chip); 4785 const struct nand_ecc_step_info *stepinfo; 4786 int step_size, strength, nsteps, ecc_bytes, corr; 4787 int best_corr = 0; 4788 int best_step = 0; 4789 int best_strength, best_ecc_bytes; 4790 int i, j; 4791 4792 if (WARN_ON(oobavail < 0)) 4793 return -EINVAL; 4794 4795 for (i = 0; i < caps->nstepinfos; i++) { 4796 stepinfo = &caps->stepinfos[i]; 4797 step_size = stepinfo->stepsize; 4798 4799 /* If chip->ecc.size is already set, respect it */ 4800 if (chip->ecc.size && step_size != chip->ecc.size) 4801 continue; 4802 4803 for (j = 0; j < stepinfo->nstrengths; j++) { 4804 strength = stepinfo->strengths[j]; 4805 4806 if (mtd->writesize % step_size) 4807 continue; 4808 4809 nsteps = mtd->writesize / step_size; 4810 4811 ecc_bytes = caps->calc_ecc_bytes(step_size, strength); 4812 if (WARN_ON_ONCE(ecc_bytes < 0)) 4813 continue; 4814 4815 if (ecc_bytes * nsteps > oobavail) 4816 continue; 4817 4818 corr = strength * nsteps; 4819 4820 /* 4821 * If the number of correctable bits is the same, 4822 * bigger step_size has more reliability. 4823 */ 4824 if (corr > best_corr || 4825 (corr == best_corr && step_size > best_step)) { 4826 best_corr = corr; 4827 best_step = step_size; 4828 best_strength = strength; 4829 best_ecc_bytes = ecc_bytes; 4830 } 4831 } 4832 } 4833 4834 if (!best_corr) 4835 return -ENOTSUPP; 4836 4837 chip->ecc.size = best_step; 4838 chip->ecc.strength = best_strength; 4839 chip->ecc.bytes = best_ecc_bytes; 4840 4841 return 0; 4842} 4843EXPORT_SYMBOL_GPL(nand_maximize_ecc); 4844 4845/* 4846 * Check if the chip configuration meet the datasheet requirements. 4847 4848 * If our configuration corrects A bits per B bytes and the minimum 4849 * required correction level is X bits per Y bytes, then we must ensure 4850 * both of the following are true: 4851 * 4852 * (1) A / B >= X / Y 4853 * (2) A >= X 4854 * 4855 * Requirement (1) ensures we can correct for the required bitflip density. 4856 * Requirement (2) ensures we can correct even when all bitflips are clumped 4857 * in the same sector. 4858 */ 4859static bool nand_ecc_strength_good(struct mtd_info *mtd) 4860{ 4861 struct nand_chip *chip = mtd_to_nand(mtd); 4862 struct nand_ecc_ctrl *ecc = &chip->ecc; 4863 int corr, ds_corr; 4864 4865 if (ecc->size == 0 || chip->ecc_step_ds == 0) 4866 /* Not enough information */ 4867 return true; 4868 4869 /* 4870 * We get the number of corrected bits per page to compare 4871 * the correction density. 4872 */ 4873 corr = (mtd->writesize * ecc->strength) / ecc->size; 4874 ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds; 4875 4876 return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds; 4877} 4878 4879static bool invalid_ecc_page_accessors(struct nand_chip *chip) 4880{ 4881 struct nand_ecc_ctrl *ecc = &chip->ecc; 4882 4883 if (nand_standard_page_accessors(ecc)) 4884 return false; 4885 4886 /* 4887 * NAND_ECC_CUSTOM_PAGE_ACCESS flag is set, make sure the NAND 4888 * controller driver implements all the page accessors because 4889 * default helpers are not suitable when the core does not 4890 * send the READ0/PAGEPROG commands. 4891 */ 4892 return (!ecc->read_page || !ecc->write_page || 4893 !ecc->read_page_raw || !ecc->write_page_raw || 4894 (NAND_HAS_SUBPAGE_READ(chip) && !ecc->read_subpage) || 4895 (NAND_HAS_SUBPAGE_WRITE(chip) && !ecc->write_subpage && 4896 ecc->hwctl && ecc->calculate)); 4897} 4898 4899/** 4900 * nand_scan_tail - [NAND Interface] Scan for the NAND device 4901 * @mtd: MTD device structure 4902 * 4903 * This is the second phase of the normal nand_scan() function. It fills out 4904 * all the uninitialized function pointers with the defaults and scans for a 4905 * bad block table if appropriate. 4906 */ 4907int nand_scan_tail(struct mtd_info *mtd) 4908{ 4909 int i; 4910 struct nand_chip *chip = mtd_to_nand(mtd); 4911 struct nand_ecc_ctrl *ecc = &chip->ecc; 4912 struct nand_buffers *nbuf; 4913 4914 /* New bad blocks should be marked in OOB, flash-based BBT, or both */ 4915 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) && 4916 !(chip->bbt_options & NAND_BBT_USE_FLASH)); 4917 4918 if (invalid_ecc_page_accessors(chip)) { 4919 pr_err("Invalid ECC page accessors setup\n"); 4920 return -EINVAL; 4921 } 4922 4923 if (!(chip->options & NAND_OWN_BUFFERS)) { 4924 nbuf = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL); 4925 chip->buffers = nbuf; 4926 } else { 4927 if (!chip->buffers) 4928 return -ENOMEM; 4929 } 4930 4931 /* Set the internal oob buffer location, just after the page data */ 4932 chip->oob_poi = chip->buffers->databuf + mtd->writesize; 4933 4934 /* 4935 * If no default placement scheme is given, select an appropriate one. 4936 */ 4937 if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) { 4938 switch (mtd->oobsize) { 4939#ifndef CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT 4940 case 8: 4941 ecc->layout = &nand_oob_8; 4942 break; 4943 case 16: 4944 ecc->layout = &nand_oob_16; 4945 break; 4946 case 64: 4947 ecc->layout = &nand_oob_64; 4948 break; 4949 case 128: 4950 ecc->layout = &nand_oob_128; 4951 break; 4952#endif 4953 default: 4954 pr_warn("No oob scheme defined for oobsize %d\n", 4955 mtd->oobsize); 4956 BUG(); 4957 } 4958 } 4959 4960 if (!chip->write_page) 4961 chip->write_page = nand_write_page; 4962 4963 /* 4964 * Check ECC mode, default to software if 3byte/512byte hardware ECC is 4965 * selected and we have 256 byte pagesize fallback to software ECC 4966 */ 4967 4968 switch (ecc->mode) { 4969 case NAND_ECC_HW_OOB_FIRST: 4970 /* Similar to NAND_ECC_HW, but a separate read_page handle */ 4971 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) { 4972 pr_warn("No ECC functions supplied; hardware ECC not possible\n"); 4973 BUG(); 4974 } 4975 if (!ecc->read_page) 4976 ecc->read_page = nand_read_page_hwecc_oob_first; 4977 4978 case NAND_ECC_HW: 4979 /* Use standard hwecc read page function? */ 4980 if (!ecc->read_page) 4981 ecc->read_page = nand_read_page_hwecc; 4982 if (!ecc->write_page) 4983 ecc->write_page = nand_write_page_hwecc; 4984 if (!ecc->read_page_raw) 4985 ecc->read_page_raw = nand_read_page_raw; 4986 if (!ecc->write_page_raw) 4987 ecc->write_page_raw = nand_write_page_raw; 4988 if (!ecc->read_oob) 4989 ecc->read_oob = nand_read_oob_std; 4990 if (!ecc->write_oob) 4991 ecc->write_oob = nand_write_oob_std; 4992 if (!ecc->read_subpage) 4993 ecc->read_subpage = nand_read_subpage; 4994 if (!ecc->write_subpage && ecc->hwctl && ecc->calculate) 4995 ecc->write_subpage = nand_write_subpage_hwecc; 4996 4997 case NAND_ECC_HW_SYNDROME: 4998 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) && 4999 (!ecc->read_page || 5000 ecc->read_page == nand_read_page_hwecc || 5001 !ecc->write_page || 5002 ecc->write_page == nand_write_page_hwecc)) { 5003 pr_warn("No ECC functions supplied; hardware ECC not possible\n"); 5004 BUG(); 5005 } 5006 /* Use standard syndrome read/write page function? */ 5007 if (!ecc->read_page) 5008 ecc->read_page = nand_read_page_syndrome; 5009 if (!ecc->write_page) 5010 ecc->write_page = nand_write_page_syndrome; 5011 if (!ecc->read_page_raw) 5012 ecc->read_page_raw = nand_read_page_raw_syndrome; 5013 if (!ecc->write_page_raw) 5014 ecc->write_page_raw = nand_write_page_raw_syndrome; 5015 if (!ecc->read_oob) 5016 ecc->read_oob = nand_read_oob_syndrome; 5017 if (!ecc->write_oob) 5018 ecc->write_oob = nand_write_oob_syndrome; 5019 5020 if (mtd->writesize >= ecc->size) { 5021 if (!ecc->strength) { 5022 pr_warn("Driver must set ecc.strength when using hardware ECC\n"); 5023 BUG(); 5024 } 5025 break; 5026 } 5027 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n", 5028 ecc->size, mtd->writesize); 5029 ecc->mode = NAND_ECC_SOFT; 5030 5031 case NAND_ECC_SOFT: 5032 ecc->calculate = nand_calculate_ecc; 5033 ecc->correct = nand_correct_data; 5034 ecc->read_page = nand_read_page_swecc; 5035 ecc->read_subpage = nand_read_subpage; 5036 ecc->write_page = nand_write_page_swecc; 5037 ecc->read_page_raw = nand_read_page_raw; 5038 ecc->write_page_raw = nand_write_page_raw; 5039 ecc->read_oob = nand_read_oob_std; 5040 ecc->write_oob = nand_write_oob_std; 5041 if (!ecc->size) 5042 ecc->size = 256; 5043 ecc->bytes = 3; 5044 ecc->strength = 1; 5045 break; 5046 5047 case NAND_ECC_SOFT_BCH: 5048 if (!mtd_nand_has_bch()) { 5049 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n"); 5050 BUG(); 5051 } 5052 ecc->calculate = nand_bch_calculate_ecc; 5053 ecc->correct = nand_bch_correct_data; 5054 ecc->read_page = nand_read_page_swecc; 5055 ecc->read_subpage = nand_read_subpage; 5056 ecc->write_page = nand_write_page_swecc; 5057 ecc->read_page_raw = nand_read_page_raw; 5058 ecc->write_page_raw = nand_write_page_raw; 5059 ecc->read_oob = nand_read_oob_std; 5060 ecc->write_oob = nand_write_oob_std; 5061 /* 5062 * Board driver should supply ecc.size and ecc.strength values 5063 * to select how many bits are correctable. Otherwise, default 5064 * to 4 bits for large page devices. 5065 */ 5066 if (!ecc->size && (mtd->oobsize >= 64)) { 5067 ecc->size = 512; 5068 ecc->strength = 4; 5069 } 5070 5071 /* See nand_bch_init() for details. */ 5072 ecc->bytes = 0; 5073 ecc->priv = nand_bch_init(mtd); 5074 if (!ecc->priv) { 5075 pr_warn("BCH ECC initialization failed!\n"); 5076 BUG(); 5077 } 5078 break; 5079 5080 case NAND_ECC_NONE: 5081 pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n"); 5082 ecc->read_page = nand_read_page_raw; 5083 ecc->write_page = nand_write_page_raw; 5084 ecc->read_oob = nand_read_oob_std; 5085 ecc->read_page_raw = nand_read_page_raw; 5086 ecc->write_page_raw = nand_write_page_raw; 5087 ecc->write_oob = nand_write_oob_std; 5088 ecc->size = mtd->writesize; 5089 ecc->bytes = 0; 5090 ecc->strength = 0; 5091 break; 5092 5093 default: 5094 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode); 5095 BUG(); 5096 } 5097 5098 /* For many systems, the standard OOB write also works for raw */ 5099 if (!ecc->read_oob_raw) 5100 ecc->read_oob_raw = ecc->read_oob; 5101 if (!ecc->write_oob_raw) 5102 ecc->write_oob_raw = ecc->write_oob; 5103 5104 /* 5105 * The number of bytes available for a client to place data into 5106 * the out of band area. 5107 */ 5108 mtd->oobavail = 0; 5109 if (ecc->layout) { 5110 for (i = 0; ecc->layout->oobfree[i].length; i++) 5111 mtd->oobavail += ecc->layout->oobfree[i].length; 5112 } 5113 5114 /* ECC sanity check: warn if it's too weak */ 5115 if (!nand_ecc_strength_good(mtd)) 5116 pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n", 5117 mtd->name); 5118 5119 /* 5120 * Set the number of read / write steps for one page depending on ECC 5121 * mode. 5122 */ 5123 ecc->steps = mtd->writesize / ecc->size; 5124 if (ecc->steps * ecc->size != mtd->writesize) { 5125 pr_warn("Invalid ECC parameters\n"); 5126 BUG(); 5127 } 5128 ecc->total = ecc->steps * ecc->bytes; 5129 5130 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ 5131 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) { 5132 switch (ecc->steps) { 5133 case 2: 5134 mtd->subpage_sft = 1; 5135 break; 5136 case 4: 5137 case 8: 5138 case 16: 5139 mtd->subpage_sft = 2; 5140 break; 5141 } 5142 } 5143 chip->subpagesize = mtd->writesize >> mtd->subpage_sft; 5144 5145 /* Initialize state */ 5146 chip->state = FL_READY; 5147 5148 /* Invalidate the pagebuffer reference */ 5149 chip->pagebuf = -1; 5150 5151 /* Large page NAND with SOFT_ECC should support subpage reads */ 5152 switch (ecc->mode) { 5153 case NAND_ECC_SOFT: 5154 case NAND_ECC_SOFT_BCH: 5155 if (chip->page_shift > 9) 5156 chip->options |= NAND_SUBPAGE_READ; 5157 break; 5158 5159 default: 5160 break; 5161 } 5162 5163 mtd->flash_node = chip->flash_node; 5164 /* Fill in remaining MTD driver data */ 5165 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH; 5166 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM : 5167 MTD_CAP_NANDFLASH; 5168 mtd->_erase = nand_erase; 5169 mtd->_panic_write = panic_nand_write; 5170 mtd->_read_oob = nand_read_oob; 5171 mtd->_write_oob = nand_write_oob; 5172 mtd->_sync = nand_sync; 5173 mtd->_lock = NULL; 5174 mtd->_unlock = NULL; 5175 mtd->_block_isreserved = nand_block_isreserved; 5176 mtd->_block_isbad = nand_block_isbad; 5177 mtd->_block_markbad = nand_block_markbad; 5178 mtd->writebufsize = mtd->writesize; 5179 5180 /* propagate ecc info to mtd_info */ 5181 mtd->ecclayout = ecc->layout; 5182 mtd->ecc_strength = ecc->strength; 5183 mtd->ecc_step_size = ecc->size; 5184 /* 5185 * Initialize bitflip_threshold to its default prior scan_bbt() call. 5186 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be 5187 * properly set. 5188 */ 5189 if (!mtd->bitflip_threshold) 5190 mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4); 5191 5192 return 0; 5193} 5194EXPORT_SYMBOL(nand_scan_tail); 5195 5196/** 5197 * nand_scan - [NAND Interface] Scan for the NAND device 5198 * @mtd: MTD device structure 5199 * @maxchips: number of chips to scan for 5200 * 5201 * This fills out all the uninitialized function pointers with the defaults. 5202 * The flash ID is read and the mtd/chip structures are filled with the 5203 * appropriate values. 5204 */ 5205int nand_scan(struct mtd_info *mtd, int maxchips) 5206{ 5207 int ret; 5208 5209 ret = nand_scan_ident(mtd, maxchips, NULL); 5210 if (!ret) 5211 ret = nand_scan_tail(mtd); 5212 return ret; 5213} 5214EXPORT_SYMBOL(nand_scan); 5215 5216MODULE_LICENSE("GPL"); 5217MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>"); 5218MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>"); 5219MODULE_DESCRIPTION("Generic NAND flash driver code"); 5220