1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (c) 2009 Magnus Lilja <lilja.magnus@gmail.com> 4 */ 5 6#ifndef __MXC_NAND_H 7#define __MXC_NAND_H 8 9/* 10 * Register map and bit definitions for the Freescale NAND Flash Controller 11 * present in various i.MX devices. 12 * 13 * MX31 and MX27 have version 1, which has: 14 * 4 512-byte main buffers and 15 * 4 16-byte spare buffers 16 * to support up to 2K byte pagesize nand. 17 * Reading or writing a 2K page requires 4 FDI/FDO cycles. 18 * 19 * MX25 and MX35 have version 2.1, and MX51 and MX53 have version 3.2, which 20 * have: 21 * 8 512-byte main buffers and 22 * 8 64-byte spare buffers 23 * to support up to 4K byte pagesize nand. 24 * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle. 25 * Also some of registers are moved and/or changed meaning as seen below. 26 */ 27#if defined(CONFIG_MX31) 28#define MXC_NFC_V1 29#define is_mxc_nfc_1() 1 30#define is_mxc_nfc_21() 0 31#define is_mxc_nfc_32() 0 32#elif defined(CONFIG_MX51) || defined(CONFIG_MX53) 33#define MXC_NFC_V3 34#define MXC_NFC_V3_2 35#define is_mxc_nfc_1() 0 36#define is_mxc_nfc_21() 0 37#define is_mxc_nfc_32() 1 38#else 39#error "MXC NFC implementation not supported" 40#endif 41#define is_mxc_nfc_3() is_mxc_nfc_32() 42 43#if defined(MXC_NFC_V1) 44#define NAND_MXC_NR_BUFS 4 45#define NAND_MXC_SPARE_BUF_SIZE 16 46#define NAND_MXC_REG_OFFSET 0xe00 47#define NAND_MXC_2K_MULTI_CYCLE 48#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2) 49#define NAND_MXC_NR_BUFS 8 50#define NAND_MXC_SPARE_BUF_SIZE 64 51#define NAND_MXC_REG_OFFSET 0x1e00 52#endif 53 54struct mxc_nand_regs { 55 u8 main_area[NAND_MXC_NR_BUFS][0x200]; 56 u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE]; 57 /* 58 * reserved size is offset of nfc registers 59 * minus total main and spare sizes 60 */ 61 u8 reserved1[NAND_MXC_REG_OFFSET 62 - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)]; 63#if defined(MXC_NFC_V1) 64 u16 buf_size; 65 u16 reserved2; 66 u16 buf_addr; 67 u16 flash_addr; 68 u16 flash_cmd; 69 u16 config; 70 u16 ecc_status_result; 71 u16 rsltmain_area; 72 u16 rsltspare_area; 73 u16 wrprot; 74 u16 unlockstart_blkaddr; 75 u16 unlockend_blkaddr; 76 u16 nf_wrprst; 77 u16 config1; 78 u16 config2; 79#elif defined(MXC_NFC_V2_1) 80 u16 reserved2[2]; 81 u16 buf_addr; 82 u16 flash_addr; 83 u16 flash_cmd; 84 u16 config; 85 u32 ecc_status_result; 86 u16 spare_area_size; 87 u16 wrprot; 88 u16 reserved3[2]; 89 u16 nf_wrprst; 90 u16 config1; 91 u16 config2; 92 u16 reserved4; 93 u16 unlockstart_blkaddr; 94 u16 unlockend_blkaddr; 95 u16 unlockstart_blkaddr1; 96 u16 unlockend_blkaddr1; 97 u16 unlockstart_blkaddr2; 98 u16 unlockend_blkaddr2; 99 u16 unlockstart_blkaddr3; 100 u16 unlockend_blkaddr3; 101#elif defined(MXC_NFC_V3_2) 102 u32 flash_cmd; 103 u32 flash_addr[12]; 104 u32 config1; 105 u32 ecc_status_result; 106 u32 status_sum; 107 u32 launch; 108#endif 109}; 110 111#ifdef MXC_NFC_V3_2 112struct mxc_nand_ip_regs { 113 u32 wrprot; 114 u32 wrprot_unlock_blkaddr[8]; 115 u32 config2; 116 u32 config3; 117 u32 ipc; 118 u32 err_addr; 119 u32 delay_line; 120}; 121#endif 122 123/* Set FCMD to 1, rest to 0 for Command operation */ 124#define NFC_CMD 0x1 125 126/* Set FADD to 1, rest to 0 for Address operation */ 127#define NFC_ADDR 0x2 128 129/* Set FDI to 1, rest to 0 for Input operation */ 130#define NFC_INPUT 0x4 131 132/* Set FDO to 001, rest to 0 for Data Output operation */ 133#define NFC_OUTPUT 0x8 134 135/* Set FDO to 010, rest to 0 for Read ID operation */ 136#define NFC_ID 0x10 137 138/* Set FDO to 100, rest to 0 for Read Status operation */ 139#define NFC_STATUS 0x20 140 141#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) 142#define NFC_CONFIG1_SP_EN (1 << 2) 143#define NFC_CONFIG1_RST (1 << 6) 144#define NFC_CONFIG1_CE (1 << 7) 145#elif defined(MXC_NFC_V3_2) 146#define NFC_CONFIG1_SP_EN (1 << 0) 147#define NFC_CONFIG1_CE (1 << 1) 148#define NFC_CONFIG1_RST (1 << 2) 149#endif 150#define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3) 151#define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4) 152#define NFC_V1_V2_CONFIG1_BIG (1 << 5) 153#define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0) 154#define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8) 155#define NFC_V2_CONFIG1_FP_INT (1 << 11) 156#define NFC_V3_CONFIG1_RBA_MASK (0x7 << 4) 157#define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7) << 4) 158 159#define NFC_V1_V2_CONFIG2_INT (1 << 15) 160#define NFC_V3_CONFIG2_PS_MASK (0x3 << 0) 161#define NFC_V3_CONFIG2_PS_512 (0 << 0) 162#define NFC_V3_CONFIG2_PS_2048 (1 << 0) 163#define NFC_V3_CONFIG2_PS_4096 (2 << 0) 164#define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2) 165#define NFC_V3_CONFIG2_ECC_EN (1 << 3) 166#define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4) 167#define NFC_V3_CONFIG2_NUM_ADDR_PH0 (1 << 5) 168#define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6) 169#define NFC_V3_CONFIG2_PPB_MASK (0x3 << 7) 170#define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7) 171#define NFC_V3_CONFIG2_EDC_MASK (0x7 << 9) 172#define NFC_V3_CONFIG2_EDC(x) (((x) & 0x7) << 9) 173#define NFC_V3_CONFIG2_NUM_ADDR_PH1(x) (((x) & 0x3) << 12) 174#define NFC_V3_CONFIG2_INT_MSK (1 << 15) 175#define NFC_V3_CONFIG2_SPAS_MASK (0xff << 16) 176#define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16) 177#define NFC_V3_CONFIG2_ST_CMD_MASK (0xff << 24) 178#define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24) 179 180#define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0) 181#define NFC_V3_CONFIG3_FW8 (1 << 3) 182#define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8) 183#define NFC_V3_CONFIG3_NUM_OF_DEVS(x) (((x) & 0x7) << 12) 184#define NFC_V3_CONFIG3_RBB_MODE (1 << 15) 185#define NFC_V3_CONFIG3_NO_SDMA (1 << 20) 186 187#define NFC_V3_WRPROT_UNLOCK (1 << 2) 188#define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6) 189 190#define NFC_V3_IPC_CREQ (1 << 0) 191#define NFC_V3_IPC_INT (1 << 31) 192 193#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) 194#define operation config2 195#define readnfc readw 196#define writenfc writew 197#elif defined(MXC_NFC_V3_2) 198#define operation launch 199#define readnfc readl 200#define writenfc writel 201#endif 202 203#endif /* __MXC_NAND_H */ 204