11541Srgrimes// SPDX-License-Identifier: GPL-2.0+ 21541Srgrimes/* 31541Srgrimes * Arasan NAND Flash Controller Driver 41541Srgrimes * 51541Srgrimes * Copyright (C) 2014 - 2015 Xilinx, Inc. 61541Srgrimes */ 71541Srgrimes 81541Srgrimes#include <common.h> 91541Srgrimes#include <malloc.h> 101541Srgrimes#include <asm/io.h> 111541Srgrimes#include <linux/delay.h> 121541Srgrimes#include <linux/errno.h> 131541Srgrimes#include <linux/mtd/mtd.h> 141541Srgrimes#include <linux/mtd/rawnand.h> 151541Srgrimes#include <linux/mtd/partitions.h> 161541Srgrimes#include <linux/mtd/nand_ecc.h> 171541Srgrimes#include <asm/arch/hardware.h> 181541Srgrimes#include <asm/arch/sys_proto.h> 191541Srgrimes#include <dm.h> 201541Srgrimes#include <nand.h> 211541Srgrimes#include <linux/printk.h> 221541Srgrimes 231541Srgrimesstruct nand_config { 241541Srgrimes u32 page; 251541Srgrimes bool on_die_ecc_enabled; 261541Srgrimes}; 271541Srgrimes 281541Srgrimesstruct nand_drv { 291541Srgrimes struct nand_regs *reg; 301541Srgrimes struct nand_config config; 311541Srgrimes}; 321541Srgrimes 331541Srgrimesstruct arasan_nand_info { 341541Srgrimes struct udevice *dev; 351541Srgrimes struct nand_drv nand_ctrl; 361541Srgrimes struct nand_chip nand_chip; 371541Srgrimes}; 381541Srgrimes 3912569Sbdestruct nand_regs { 401541Srgrimes u32 pkt_reg; 411541Srgrimes u32 memadr_reg1; 421541Srgrimes u32 memadr_reg2; 431541Srgrimes u32 cmd_reg; 442112Swollman u32 pgm_reg; 452946Swollman u32 intsts_enr; 461541Srgrimes u32 intsig_enr; 471541Srgrimes u32 intsts_reg; 481541Srgrimes u32 rdy_busy; 491541Srgrimes u32 cms_sysadr_reg; 501541Srgrimes u32 flash_sts_reg; 511541Srgrimes u32 tmg_reg; 521541Srgrimes u32 buf_dataport; 531541Srgrimes u32 ecc_reg; 541541Srgrimes u32 ecc_errcnt_reg; 552946Swollman u32 ecc_sprcmd_reg; 562946Swollman u32 errcnt_1bitreg; 572946Swollman u32 errcnt_2bitreg; 581541Srgrimes u32 errcnt_3bitreg; 5910653Sdg u32 errcnt_4bitreg; 6010358Sjulian u32 dma_sysadr0_reg; 6110358Sjulian u32 dma_bufbdry_reg; 6212569Sbde u32 cpu_rls_reg; 6312569Sbde u32 errcnt_5bitreg; 6410358Sjulian u32 errcnt_6bitreg; 651541Srgrimes u32 errcnt_7bitreg; 661541Srgrimes u32 errcnt_8bitreg; 671541Srgrimes u32 data_if_reg; 681541Srgrimes}; 691541Srgrimes 701541Srgrimesstruct arasan_nand_command_format { 711541Srgrimes u8 cmd1; 721541Srgrimes u8 cmd2; 732946Swollman u8 addr_cycles; 742946Swollman u32 pgm; 752946Swollman}; 762946Swollman 772946Swollman#define ONDIE_ECC_FEATURE_ADDR 0x90 782946Swollman#define ENABLE_ONDIE_ECC 0x08 792946Swollman 802946Swollman#define ARASAN_PROG_RD_MASK 0x00000001 812946Swollman#define ARASAN_PROG_BLK_ERS_MASK 0x00000004 821541Srgrimes#define ARASAN_PROG_RD_ID_MASK 0x00000040 831541Srgrimes#define ARASAN_PROG_RD_STS_MASK 0x00000008 841541Srgrimes#define ARASAN_PROG_PG_PROG_MASK 0x00000010 851541Srgrimes#define ARASAN_PROG_RD_PARAM_PG_MASK 0x00000080 861541Srgrimes#define ARASAN_PROG_RST_MASK 0x00000100 871541Srgrimes#define ARASAN_PROG_GET_FTRS_MASK 0x00000200 881541Srgrimes#define ARASAN_PROG_SET_FTRS_MASK 0x00000400 891541Srgrimes#define ARASAN_PROG_CHNG_ROWADR_END_MASK 0x00400000 901541Srgrimes 911541Srgrimes#define ARASAN_NAND_CMD_ECC_ON_MASK 0x80000000 921541Srgrimes#define ARASAN_NAND_CMD_CMD12_MASK 0xFFFF 931541Srgrimes#define ARASAN_NAND_CMD_PG_SIZE_MASK 0x3800000 941541Srgrimes#define ARASAN_NAND_CMD_PG_SIZE_SHIFT 23 951541Srgrimes#define ARASAN_NAND_CMD_CMD2_SHIFT 8 961541Srgrimes#define ARASAN_NAND_CMD_ADDR_CYCL_MASK 0x70000000 971541Srgrimes#define ARASAN_NAND_CMD_ADDR_CYCL_SHIFT 28 981541Srgrimes 991541Srgrimes#define ARASAN_NAND_MEM_ADDR1_PAGE_MASK 0xFFFF0000 1001541Srgrimes#define ARASAN_NAND_MEM_ADDR1_COL_MASK 0xFFFF 1011541Srgrimes#define ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT 16 1021541Srgrimes#define ARASAN_NAND_MEM_ADDR2_PAGE_MASK 0xFF 1031541Srgrimes#define ARASAN_NAND_MEM_ADDR2_CS_MASK 0xC0000000 1041541Srgrimes#define ARASAN_NAND_MEM_ADDR2_CS0_MASK (0x3 << 30) 1051541Srgrimes#define ARASAN_NAND_MEM_ADDR2_CS1_MASK (0x1 << 30) 1061541Srgrimes#define ARASAN_NAND_MEM_ADDR2_BCH_MASK 0xE000000 1071541Srgrimes#define ARASAN_NAND_MEM_ADDR2_BCH_SHIFT 25 1081541Srgrimes 1091541Srgrimes#define ARASAN_NAND_INT_STS_ERR_EN_MASK 0x10 1101541Srgrimes#define ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK 0x08 1111541Srgrimes#define ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK 0x02 1121541Srgrimes#define ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK 0x01 1131541Srgrimes#define ARASAN_NAND_INT_STS_XFR_CMPLT_MASK 0x04 1141541Srgrimes 1151541Srgrimes#define ARASAN_NAND_PKT_REG_PKT_CNT_MASK 0xFFF000 1161541Srgrimes#define ARASAN_NAND_PKT_REG_PKT_SIZE_MASK 0x7FF 1171541Srgrimes#define ARASAN_NAND_PKT_REG_PKT_CNT_SHFT 12 1181541Srgrimes 1191541Srgrimes#define ARASAN_NAND_ROW_ADDR_CYCL_MASK 0x0F 1202946Swollman#define ARASAN_NAND_COL_ADDR_CYCL_MASK 0xF0 1211541Srgrimes#define ARASAN_NAND_COL_ADDR_CYCL_SHIFT 4 1221541Srgrimes 12312158Sbde#define ARASAN_NAND_ECC_SIZE_SHIFT 16 12412158Sbde#define ARASAN_NAND_ECC_BCH_SHIFT 27 1251541Srgrimes 1261541Srgrimes#define ARASAN_NAND_PKTSIZE_1K 1024 1271541Srgrimes#define ARASAN_NAND_PKTSIZE_512 512 1281541Srgrimes 1291541Srgrimes#define ARASAN_NAND_POLL_TIMEOUT 1000000 1302946Swollman#define ARASAN_NAND_INVALID_ADDR_CYCL 0xFF 1312946Swollman 1321541Srgrimes#define ERR_ADDR_CYCLE -1 1331541Srgrimes#define READ_BUFF_SIZE 0x4000 1341541Srgrimes 1351541Srgrimesstatic struct arasan_nand_command_format *curr_cmd; 1361541Srgrimes 1371541Srgrimesenum addr_cycles { 13812158Sbde NAND_ADDR_CYCL_NONE, 13912158Sbde NAND_ADDR_CYCL_ONE, 14012158Sbde NAND_ADDR_CYCL_ROW, 14112158Sbde NAND_ADDR_CYCL_COL, 14212158Sbde NAND_ADDR_CYCL_BOTH, 1431541Srgrimes}; 1441541Srgrimes 1451541Srgrimesstatic struct arasan_nand_command_format arasan_nand_commands[] = { 1461541Srgrimes {NAND_CMD_READ0, NAND_CMD_READSTART, NAND_ADDR_CYCL_BOTH, 1472946Swollman ARASAN_PROG_RD_MASK}, 1482946Swollman {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, NAND_ADDR_CYCL_COL, 1491541Srgrimes ARASAN_PROG_RD_MASK}, 1501541Srgrimes {NAND_CMD_READID, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE, 1511541Srgrimes ARASAN_PROG_RD_ID_MASK}, 1521541Srgrimes {NAND_CMD_STATUS, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE, 1531541Srgrimes ARASAN_PROG_RD_STS_MASK}, 1541541Srgrimes {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, NAND_ADDR_CYCL_BOTH, 1551541Srgrimes ARASAN_PROG_PG_PROG_MASK}, 1561541Srgrimes {NAND_CMD_RNDIN, NAND_CMD_NONE, NAND_ADDR_CYCL_COL, 1571541Srgrimes ARASAN_PROG_CHNG_ROWADR_END_MASK}, 1581541Srgrimes {NAND_CMD_ERASE1, NAND_CMD_ERASE2, NAND_ADDR_CYCL_ROW, 1591541Srgrimes ARASAN_PROG_BLK_ERS_MASK}, 1601541Srgrimes {NAND_CMD_RESET, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE, 1611541Srgrimes ARASAN_PROG_RST_MASK}, 1621541Srgrimes {NAND_CMD_PARAM, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE, 1631541Srgrimes ARASAN_PROG_RD_PARAM_PG_MASK}, 1641541Srgrimes {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE, 1651541Srgrimes ARASAN_PROG_GET_FTRS_MASK}, 1661541Srgrimes {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE, 1671541Srgrimes ARASAN_PROG_SET_FTRS_MASK}, 1681541Srgrimes {NAND_CMD_NONE, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE, 0}, 1691541Srgrimes}; 1701541Srgrimes 1711541Srgrimesstruct arasan_ecc_matrix { 1721541Srgrimes u32 pagesize; 1731541Srgrimes u32 ecc_codeword_size; 1741541Srgrimes u8 eccbits; 1751541Srgrimes u8 bch; 1761541Srgrimes u8 bchval; 1771541Srgrimes u16 eccaddr; 1781541Srgrimes u16 eccsize; 1791541Srgrimes}; 1801541Srgrimes 1811541Srgrimesstatic const struct arasan_ecc_matrix ecc_matrix[] = { 1821541Srgrimes {512, 512, 1, 0, 0, 0x20D, 0x3}, 1831541Srgrimes {512, 512, 4, 1, 3, 0x209, 0x7}, 1841541Srgrimes {512, 512, 8, 1, 2, 0x203, 0xD}, 1851541Srgrimes /* 1861541Srgrimes * 2K byte page 1872946Swollman */ 1882946Swollman {2048, 512, 1, 0, 0, 0x834, 0xC}, 1891541Srgrimes {2048, 512, 4, 1, 3, 0x826, 0x1A}, 1901541Srgrimes {2048, 512, 8, 1, 2, 0x80c, 0x34}, 1911541Srgrimes {2048, 512, 12, 1, 1, 0x822, 0x4E}, 1921541Srgrimes {2048, 512, 16, 1, 0, 0x808, 0x68}, 1931541Srgrimes {2048, 1024, 24, 1, 4, 0x81c, 0x54}, 1941541Srgrimes /* 1951541Srgrimes * 4K byte page 1961541Srgrimes */ 1978876Srgrimes {4096, 512, 1, 0, 0, 0x1068, 0x18}, 1981541Srgrimes {4096, 512, 4, 1, 3, 0x104c, 0x34}, 1991541Srgrimes {4096, 512, 8, 1, 2, 0x1018, 0x68}, 2001541Srgrimes {4096, 512, 12, 1, 1, 0x1044, 0x9C}, 2011541Srgrimes {4096, 512, 16, 1, 0, 0x1010, 0xD0}, 2021541Srgrimes {4096, 1024, 24, 1, 4, 0x1038, 0xA8}, 2031541Srgrimes /* 2041541Srgrimes * 8K byte page 2051541Srgrimes */ 2061541Srgrimes {8192, 512, 1, 0, 0, 0x20d0, 0x30}, 2071541Srgrimes {8192, 512, 4, 1, 3, 0x2098, 0x68}, 2081541Srgrimes {8192, 512, 8, 1, 2, 0x2030, 0xD0}, 2091541Srgrimes {8192, 512, 12, 1, 1, 0x2088, 0x138}, 2101541Srgrimes {8192, 512, 16, 1, 0, 0x2020, 0x1A0}, 2111541Srgrimes {8192, 1024, 24, 1, 4, 0x2070, 0x150}, 2121541Srgrimes /* 2131541Srgrimes * 16K byte page 2141541Srgrimes */ 2151541Srgrimes {16384, 512, 1, 0, 0, 0x4460, 0x60}, 2161541Srgrimes {16384, 512, 4, 1, 3, 0x43f0, 0xD0}, 2171541Srgrimes {16384, 512, 8, 1, 2, 0x4320, 0x1A0}, 2181541Srgrimes {16384, 512, 12, 1, 1, 0x4250, 0x270}, 2191541Srgrimes {16384, 512, 16, 1, 0, 0x4180, 0x340}, 2201541Srgrimes {16384, 1024, 24, 1, 4, 0x4220, 0x2A0} 2211541Srgrimes}; 2221541Srgrimes 2231541Srgrimesstatic struct nand_ecclayout ondie_nand_oob_64 = { 2241541Srgrimes .eccbytes = 32, 2251541Srgrimes 2261541Srgrimes .eccpos = { 2271541Srgrimes 8, 9, 10, 11, 12, 13, 14, 15, 2281541Srgrimes 24, 25, 26, 27, 28, 29, 30, 31, 2291541Srgrimes 40, 41, 42, 43, 44, 45, 46, 47, 2301541Srgrimes 56, 57, 58, 59, 60, 61, 62, 63 2311541Srgrimes }, 2321541Srgrimes 2331541Srgrimes .oobfree = { 2341541Srgrimes { .offset = 4, .length = 4 }, 2351541Srgrimes { .offset = 20, .length = 4 }, 2361541Srgrimes { .offset = 36, .length = 4 }, 2371541Srgrimes { .offset = 52, .length = 4 } 23810358Sjulian } 23910358Sjulian}; 24012569Sbde 24112569Sbde/* 2421541Srgrimes * bbt decriptors for chips with on-die ECC and 2431541Srgrimes * chips with 64-byte OOB 2442946Swollman */ 2452946Swollmanstatic u8 bbt_pattern[] = {'B', 'b', 't', '0' }; 2461541Srgrimesstatic u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; 2471541Srgrimes 2482946Swollmanstatic struct nand_bbt_descr bbt_main_descr = { 2492946Swollman .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | 2502946Swollman NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, 2512946Swollman .offs = 4, 2522946Swollman .len = 4, 2532946Swollman .veroffs = 20, 2542946Swollman .maxblocks = 4, 2552946Swollman .pattern = bbt_pattern 2562946Swollman}; 2572946Swollman 2582946Swollmanstatic struct nand_bbt_descr bbt_mirror_descr = { 2592946Swollman .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | 2608876Srgrimes NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, 2612946Swollman .offs = 4, 2621541Srgrimes .len = 4, 2631541Srgrimes .veroffs = 20, 2641541Srgrimes .maxblocks = 4, 2651541Srgrimes .pattern = mirror_pattern 2661541Srgrimes}; 2671541Srgrimes 2681541Srgrimesstatic u8 buf_data[READ_BUFF_SIZE]; 2691541Srgrimesstatic u32 buf_index; 2701541Srgrimes 2711541Srgrimesstatic struct nand_ecclayout nand_oob; 2721541Srgrimes 2732946Swollmanstatic void arasan_nand_select_chip(struct mtd_info *mtd, int chip) 2741541Srgrimes{ 2751541Srgrimes struct nand_chip *nand_chip = mtd_to_nand(mtd); 2761541Srgrimes struct nand_drv *info = nand_get_controller_data(nand_chip); 2771541Srgrimes u32 reg_val; 2781541Srgrimes 2791541Srgrimes reg_val = readl(&info->reg->memadr_reg2); 2801541Srgrimes if (chip == 0) { 2811541Srgrimes reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS0_MASK; 2821541Srgrimes writel(reg_val, &info->reg->memadr_reg2); 2831541Srgrimes } else if (chip == 1) { 2842946Swollman reg_val |= ARASAN_NAND_MEM_ADDR2_CS1_MASK; 2852946Swollman writel(reg_val, &info->reg->memadr_reg2); 2862946Swollman } 2872946Swollman} 28812429Sphk 28912429Sphkstatic void arasan_nand_enable_ecc(struct mtd_info *mtd) 29012429Sphk{ 2912946Swollman struct nand_chip *chip = mtd_to_nand(mtd); 29212429Sphk struct nand_drv *info = nand_get_controller_data(chip); 2932946Swollman u32 reg_val; 29412429Sphk 29512429Sphk reg_val = readl(&info->reg->cmd_reg); 29612429Sphk reg_val |= ARASAN_NAND_CMD_ECC_ON_MASK; 29712429Sphk 29812429Sphk writel(reg_val, &info->reg->cmd_reg); 29912429Sphk} 30012429Sphk 30112429Sphkstatic u8 arasan_nand_get_addrcycle(struct mtd_info *mtd) 3022946Swollman{ 30312429Sphk u8 addrcycles; 3042946Swollman struct nand_chip *chip = mtd_to_nand(mtd); 30512429Sphk 30612429Sphk switch (curr_cmd->addr_cycles) { 3072946Swollman case NAND_ADDR_CYCL_NONE: 3082997Swollman addrcycles = 0; 3092997Swollman break; 3102997Swollman case NAND_ADDR_CYCL_ONE: 3112997Swollman addrcycles = 1; 3122997Swollman break; 3132997Swollman case NAND_ADDR_CYCL_ROW: 3142997Swollman addrcycles = chip->onfi_params.addr_cycles & 3152997Swollman ARASAN_NAND_ROW_ADDR_CYCL_MASK; 316 break; 317 case NAND_ADDR_CYCL_COL: 318 addrcycles = (chip->onfi_params.addr_cycles & 319 ARASAN_NAND_COL_ADDR_CYCL_MASK) >> 320 ARASAN_NAND_COL_ADDR_CYCL_SHIFT; 321 break; 322 case NAND_ADDR_CYCL_BOTH: 323 addrcycles = chip->onfi_params.addr_cycles & 324 ARASAN_NAND_ROW_ADDR_CYCL_MASK; 325 addrcycles += (chip->onfi_params.addr_cycles & 326 ARASAN_NAND_COL_ADDR_CYCL_MASK) >> 327 ARASAN_NAND_COL_ADDR_CYCL_SHIFT; 328 break; 329 default: 330 addrcycles = ARASAN_NAND_INVALID_ADDR_CYCL; 331 break; 332 } 333 return addrcycles; 334} 335 336static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size) 337{ 338 struct nand_chip *chip = mtd_to_nand(mtd); 339 struct nand_drv *info = nand_get_controller_data(chip); 340 struct nand_config *nand = &info->config; 341 u32 reg_val, i, pktsize, pktnum; 342 u32 *bufptr = (u32 *)buf; 343 u32 timeout; 344 u32 rdcount = 0; 345 u8 addr_cycles; 346 347 if (chip->ecc_step_ds >= ARASAN_NAND_PKTSIZE_1K) 348 pktsize = ARASAN_NAND_PKTSIZE_1K; 349 else 350 pktsize = ARASAN_NAND_PKTSIZE_512; 351 352 if (size % pktsize) 353 pktnum = size/pktsize + 1; 354 else 355 pktnum = size/pktsize; 356 357 reg_val = readl(&info->reg->intsts_enr); 358 reg_val |= ARASAN_NAND_INT_STS_ERR_EN_MASK | 359 ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK; 360 writel(reg_val, &info->reg->intsts_enr); 361 362 reg_val = readl(&info->reg->pkt_reg); 363 reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK | 364 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK); 365 reg_val |= (pktnum << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | 366 pktsize; 367 writel(reg_val, &info->reg->pkt_reg); 368 369 if (!nand->on_die_ecc_enabled) { 370 arasan_nand_enable_ecc(mtd); 371 addr_cycles = arasan_nand_get_addrcycle(mtd); 372 if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL) 373 return ERR_ADDR_CYCLE; 374 375 writel((NAND_CMD_RNDOUTSTART << ARASAN_NAND_CMD_CMD2_SHIFT) | 376 NAND_CMD_RNDOUT | (addr_cycles << 377 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT), 378 &info->reg->ecc_sprcmd_reg); 379 } 380 writel(curr_cmd->pgm, &info->reg->pgm_reg); 381 382 while (rdcount < pktnum) { 383 timeout = ARASAN_NAND_POLL_TIMEOUT; 384 while (!(readl(&info->reg->intsts_reg) & 385 ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK) && timeout) { 386 udelay(1); 387 timeout--; 388 } 389 if (!timeout) { 390 puts("arasan_read_page: timedout:Buff RDY\n"); 391 return -ETIMEDOUT; 392 } 393 394 rdcount++; 395 396 if (pktnum == rdcount) { 397 reg_val = readl(&info->reg->intsts_enr); 398 reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK; 399 writel(reg_val, &info->reg->intsts_enr); 400 } else { 401 reg_val = readl(&info->reg->intsts_enr); 402 writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, 403 &info->reg->intsts_enr); 404 } 405 reg_val = readl(&info->reg->intsts_reg); 406 writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, 407 &info->reg->intsts_reg); 408 409 for (i = 0; i < pktsize/4; i++) 410 bufptr[i] = readl(&info->reg->buf_dataport); 411 412 413 bufptr += pktsize/4; 414 415 if (rdcount >= pktnum) 416 break; 417 418 writel(ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, 419 &info->reg->intsts_enr); 420 } 421 422 timeout = ARASAN_NAND_POLL_TIMEOUT; 423 424 while (!(readl(&info->reg->intsts_reg) & 425 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { 426 udelay(1); 427 timeout--; 428 } 429 if (!timeout) { 430 puts("arasan rd_page timedout:Xfer CMPLT\n"); 431 return -ETIMEDOUT; 432 } 433 434 reg_val = readl(&info->reg->intsts_enr); 435 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 436 &info->reg->intsts_enr); 437 reg_val = readl(&info->reg->intsts_reg); 438 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 439 &info->reg->intsts_reg); 440 441 if (!nand->on_die_ecc_enabled) { 442 if (readl(&info->reg->intsts_reg) & 443 ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK) { 444 printf("arasan rd_page:sbiterror\n"); 445 return -1; 446 } 447 448 if (readl(&info->reg->intsts_reg) & 449 ARASAN_NAND_INT_STS_ERR_EN_MASK) { 450 mtd->ecc_stats.failed++; 451 printf("arasan rd_page:multibiterror\n"); 452 return -1; 453 } 454 } 455 456 return 0; 457} 458 459static int arasan_nand_read_page_hwecc(struct mtd_info *mtd, 460 struct nand_chip *chip, u8 *buf, int oob_required, int page) 461{ 462 int status; 463 464 status = arasan_nand_read_page(mtd, buf, (mtd->writesize)); 465 466 if (oob_required) 467 chip->ecc.read_oob(mtd, chip, page); 468 469 return status; 470} 471 472static void arasan_nand_fill_tx(struct mtd_info *mtd, const u8 *buf, int len) 473{ 474 struct nand_chip *chip = mtd_to_nand(mtd); 475 struct nand_drv *info = nand_get_controller_data(chip); 476 u32 __iomem *nand = &info->reg->buf_dataport; 477 478 if (((unsigned long)buf & 0x3) != 0) { 479 if (((unsigned long)buf & 0x1) != 0) { 480 if (len) { 481 writeb(*buf, nand); 482 buf += 1; 483 len--; 484 } 485 } 486 487 if (((unsigned long)buf & 0x3) != 0) { 488 if (len >= 2) { 489 writew(*(u16 *)buf, nand); 490 buf += 2; 491 len -= 2; 492 } 493 } 494 } 495 496 while (len >= 4) { 497 writel(*(u32 *)buf, nand); 498 buf += 4; 499 len -= 4; 500 } 501 502 if (len) { 503 if (len >= 2) { 504 writew(*(u16 *)buf, nand); 505 buf += 2; 506 len -= 2; 507 } 508 509 if (len) 510 writeb(*buf, nand); 511 } 512} 513 514static int arasan_nand_write_page_hwecc(struct mtd_info *mtd, 515 struct nand_chip *chip, const u8 *buf, int oob_required, 516 int page) 517{ 518 struct nand_drv *info = nand_get_controller_data(chip); 519 struct nand_config *nand = &info->config; 520 u32 reg_val, i, pktsize, pktnum; 521 const u32 *bufptr = (const u32 *)buf; 522 u32 timeout = ARASAN_NAND_POLL_TIMEOUT; 523 u32 size = mtd->writesize; 524 u32 rdcount = 0; 525 u8 column_addr_cycles; 526 527 if (chip->ecc_step_ds >= ARASAN_NAND_PKTSIZE_1K) 528 pktsize = ARASAN_NAND_PKTSIZE_1K; 529 else 530 pktsize = ARASAN_NAND_PKTSIZE_512; 531 532 if (size % pktsize) 533 pktnum = size/pktsize + 1; 534 else 535 pktnum = size/pktsize; 536 537 reg_val = readl(&info->reg->pkt_reg); 538 reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK | 539 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK); 540 reg_val |= (pktnum << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | pktsize; 541 writel(reg_val, &info->reg->pkt_reg); 542 543 if (!nand->on_die_ecc_enabled) { 544 arasan_nand_enable_ecc(mtd); 545 column_addr_cycles = (chip->onfi_params.addr_cycles & 546 ARASAN_NAND_COL_ADDR_CYCL_MASK) >> 547 ARASAN_NAND_COL_ADDR_CYCL_SHIFT; 548 writel((NAND_CMD_RNDIN | (column_addr_cycles << 28)), 549 &info->reg->ecc_sprcmd_reg); 550 } 551 writel(curr_cmd->pgm, &info->reg->pgm_reg); 552 553 while (rdcount < pktnum) { 554 timeout = ARASAN_NAND_POLL_TIMEOUT; 555 while (!(readl(&info->reg->intsts_reg) & 556 ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK) && timeout) { 557 udelay(1); 558 timeout--; 559 } 560 561 if (!timeout) { 562 puts("arasan_write_page: timedout:Buff RDY\n"); 563 return -ETIMEDOUT; 564 } 565 566 rdcount++; 567 568 if (pktnum == rdcount) { 569 reg_val = readl(&info->reg->intsts_enr); 570 reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK; 571 writel(reg_val, &info->reg->intsts_enr); 572 } else { 573 reg_val = readl(&info->reg->intsts_enr); 574 writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, 575 &info->reg->intsts_enr); 576 } 577 578 reg_val = readl(&info->reg->intsts_reg); 579 writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, 580 &info->reg->intsts_reg); 581 582 for (i = 0; i < pktsize/4; i++) 583 writel(bufptr[i], &info->reg->buf_dataport); 584 585 bufptr += pktsize/4; 586 587 if (rdcount >= pktnum) 588 break; 589 590 writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, 591 &info->reg->intsts_enr); 592 } 593 594 timeout = ARASAN_NAND_POLL_TIMEOUT; 595 596 while (!(readl(&info->reg->intsts_reg) & 597 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { 598 udelay(1); 599 timeout--; 600 } 601 if (!timeout) { 602 puts("arasan write_page timedout:Xfer CMPLT\n"); 603 return -ETIMEDOUT; 604 } 605 606 reg_val = readl(&info->reg->intsts_enr); 607 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 608 &info->reg->intsts_enr); 609 reg_val = readl(&info->reg->intsts_reg); 610 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 611 &info->reg->intsts_reg); 612 613 if (oob_required) 614 chip->ecc.write_oob(mtd, chip, nand->page); 615 616 return 0; 617} 618 619static int arasan_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, 620 int page) 621{ 622 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); 623 chip->read_buf(mtd, chip->oob_poi, (mtd->oobsize)); 624 625 return 0; 626} 627 628static int arasan_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, 629 int page) 630{ 631 int status = 0; 632 const u8 *buf = chip->oob_poi; 633 634 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); 635 chip->write_buf(mtd, buf, mtd->oobsize); 636 637 return status; 638} 639 640static int arasan_nand_reset(struct mtd_info *mtd, 641 struct arasan_nand_command_format *curr_cmd) 642{ 643 struct nand_chip *chip = mtd_to_nand(mtd); 644 struct nand_drv *info = nand_get_controller_data(chip); 645 u32 timeout = ARASAN_NAND_POLL_TIMEOUT; 646 u32 cmd_reg = 0; 647 648 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 649 &info->reg->intsts_enr); 650 cmd_reg = readl(&info->reg->cmd_reg); 651 cmd_reg &= ~ARASAN_NAND_CMD_CMD12_MASK; 652 653 cmd_reg |= curr_cmd->cmd1 | 654 (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT); 655 writel(cmd_reg, &info->reg->cmd_reg); 656 writel(curr_cmd->pgm, &info->reg->pgm_reg); 657 658 while (!(readl(&info->reg->intsts_reg) & 659 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { 660 udelay(1); 661 timeout--; 662 } 663 if (!timeout) { 664 printf("ERROR:%s timedout\n", __func__); 665 return -ETIMEDOUT; 666 } 667 668 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 669 &info->reg->intsts_enr); 670 671 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 672 &info->reg->intsts_reg); 673 674 return 0; 675} 676 677static u8 arasan_nand_page(struct mtd_info *mtd) 678{ 679 u8 page_val = 0; 680 681 switch (mtd->writesize) { 682 case 512: 683 page_val = 0; 684 break; 685 case 2048: 686 page_val = 1; 687 break; 688 case 4096: 689 page_val = 2; 690 break; 691 case 8192: 692 page_val = 3; 693 break; 694 case 16384: 695 page_val = 4; 696 break; 697 case 1024: 698 page_val = 5; 699 break; 700 default: 701 printf("%s:Pagesize>16K\n", __func__); 702 break; 703 } 704 705 return page_val; 706} 707 708static int arasan_nand_send_wrcmd(struct arasan_nand_command_format *curr_cmd, 709 int column, int page_addr, struct mtd_info *mtd) 710{ 711 struct nand_chip *chip = mtd_to_nand(mtd); 712 struct nand_drv *info = nand_get_controller_data(chip); 713 u32 reg_val, page; 714 u8 page_val, addr_cycles; 715 716 writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, 717 &info->reg->intsts_enr); 718 reg_val = readl(&info->reg->cmd_reg); 719 reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK; 720 reg_val |= curr_cmd->cmd1 | 721 (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT); 722 if (curr_cmd->cmd1 == NAND_CMD_SEQIN) { 723 reg_val &= ~ARASAN_NAND_CMD_PG_SIZE_MASK; 724 page_val = arasan_nand_page(mtd); 725 reg_val |= (page_val << ARASAN_NAND_CMD_PG_SIZE_SHIFT); 726 } 727 728 reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK; 729 addr_cycles = arasan_nand_get_addrcycle(mtd); 730 731 if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL) 732 return ERR_ADDR_CYCLE; 733 734 reg_val |= (addr_cycles << 735 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT); 736 writel(reg_val, &info->reg->cmd_reg); 737 738 if (page_addr == -1) 739 page_addr = 0; 740 741 page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) & 742 ARASAN_NAND_MEM_ADDR1_PAGE_MASK; 743 column &= ARASAN_NAND_MEM_ADDR1_COL_MASK; 744 writel(page | column, &info->reg->memadr_reg1); 745 746 reg_val = readl(&info->reg->memadr_reg2); 747 reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK; 748 reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT); 749 writel(reg_val, &info->reg->memadr_reg2); 750 751 return 0; 752} 753 754static void arasan_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) 755{ 756 struct nand_chip *chip = mtd_to_nand(mtd); 757 struct nand_drv *info = nand_get_controller_data(chip); 758 u32 reg_val; 759 u32 timeout = ARASAN_NAND_POLL_TIMEOUT; 760 761 reg_val = readl(&info->reg->pkt_reg); 762 reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK | 763 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK); 764 765 reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | len; 766 writel(reg_val, &info->reg->pkt_reg); 767 writel(curr_cmd->pgm, &info->reg->pgm_reg); 768 769 while (!(readl(&info->reg->intsts_reg) & 770 ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK) && timeout) { 771 udelay(1); 772 timeout--; 773 } 774 775 if (!timeout) 776 puts("ERROR:arasan_nand_write_buf timedout:Buff RDY\n"); 777 778 reg_val = readl(&info->reg->intsts_enr); 779 reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK; 780 writel(reg_val, &info->reg->intsts_enr); 781 writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, 782 &info->reg->intsts_enr); 783 reg_val = readl(&info->reg->intsts_reg); 784 writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK, 785 &info->reg->intsts_reg); 786 787 arasan_nand_fill_tx(mtd, buf, len); 788 789 timeout = ARASAN_NAND_POLL_TIMEOUT; 790 while (!(readl(&info->reg->intsts_reg) & 791 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { 792 udelay(1); 793 timeout--; 794 } 795 if (!timeout) 796 puts("ERROR:arasan_nand_write_buf timedout:Xfer CMPLT\n"); 797 798 writel(readl(&info->reg->intsts_enr) | 799 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 800 &info->reg->intsts_enr); 801 writel(readl(&info->reg->intsts_reg) | 802 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 803 &info->reg->intsts_reg); 804} 805 806static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd, 807 int column, int page_addr, struct mtd_info *mtd) 808{ 809 struct nand_chip *chip = mtd_to_nand(mtd); 810 struct nand_drv *info = nand_get_controller_data(chip); 811 u32 reg_val, page; 812 u32 timeout = ARASAN_NAND_POLL_TIMEOUT; 813 u8 row_addr_cycles; 814 815 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 816 &info->reg->intsts_enr); 817 reg_val = readl(&info->reg->cmd_reg); 818 reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK; 819 reg_val |= curr_cmd->cmd1 | 820 (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT); 821 row_addr_cycles = arasan_nand_get_addrcycle(mtd); 822 823 if (row_addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL) 824 return ERR_ADDR_CYCLE; 825 826 reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK; 827 reg_val |= (row_addr_cycles << 828 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT); 829 830 writel(reg_val, &info->reg->cmd_reg); 831 832 page = (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) & 833 ARASAN_NAND_MEM_ADDR1_COL_MASK; 834 column = page_addr & ARASAN_NAND_MEM_ADDR1_COL_MASK; 835 writel(column | (page << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT), 836 &info->reg->memadr_reg1); 837 838 reg_val = readl(&info->reg->memadr_reg2); 839 reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK; 840 reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT); 841 writel(reg_val, &info->reg->memadr_reg2); 842 writel(curr_cmd->pgm, &info->reg->pgm_reg); 843 844 while (!(readl(&info->reg->intsts_reg) & 845 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { 846 udelay(1); 847 timeout--; 848 } 849 if (!timeout) { 850 printf("ERROR:%s timedout:Xfer CMPLT\n", __func__); 851 return -ETIMEDOUT; 852 } 853 854 reg_val = readl(&info->reg->intsts_enr); 855 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 856 &info->reg->intsts_enr); 857 reg_val = readl(&info->reg->intsts_reg); 858 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 859 &info->reg->intsts_reg); 860 861 return 0; 862} 863 864static int arasan_nand_read_status(struct arasan_nand_command_format *curr_cmd, 865 int column, int page_addr, struct mtd_info *mtd) 866{ 867 struct nand_chip *chip = mtd_to_nand(mtd); 868 struct nand_drv *info = nand_get_controller_data(chip); 869 u32 reg_val; 870 u32 timeout = ARASAN_NAND_POLL_TIMEOUT; 871 u8 addr_cycles; 872 873 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 874 &info->reg->intsts_enr); 875 reg_val = readl(&info->reg->cmd_reg); 876 reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK; 877 reg_val |= curr_cmd->cmd1 | 878 (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT); 879 addr_cycles = arasan_nand_get_addrcycle(mtd); 880 881 if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL) 882 return ERR_ADDR_CYCLE; 883 884 reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK; 885 reg_val |= (addr_cycles << 886 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT); 887 888 writel(reg_val, &info->reg->cmd_reg); 889 890 reg_val = readl(&info->reg->pkt_reg); 891 reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK | 892 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK); 893 reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | 1; 894 writel(reg_val, &info->reg->pkt_reg); 895 896 writel(curr_cmd->pgm, &info->reg->pgm_reg); 897 while (!(readl(&info->reg->intsts_reg) & 898 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { 899 udelay(1); 900 timeout--; 901 } 902 903 if (!timeout) { 904 printf("ERROR:%s: timedout:Xfer CMPLT\n", __func__); 905 return -ETIMEDOUT; 906 } 907 908 reg_val = readl(&info->reg->intsts_enr); 909 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 910 &info->reg->intsts_enr); 911 reg_val = readl(&info->reg->intsts_reg); 912 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 913 &info->reg->intsts_reg); 914 915 return 0; 916} 917 918static int arasan_nand_send_rdcmd(struct arasan_nand_command_format *curr_cmd, 919 int column, int page_addr, struct mtd_info *mtd) 920{ 921 struct nand_chip *chip = mtd_to_nand(mtd); 922 struct nand_drv *info = nand_get_controller_data(chip); 923 u32 reg_val, addr_cycles, page; 924 u8 page_val; 925 926 reg_val = readl(&info->reg->intsts_enr); 927 writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, 928 &info->reg->intsts_enr); 929 930 reg_val = readl(&info->reg->cmd_reg); 931 reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK; 932 reg_val |= curr_cmd->cmd1 | 933 (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT); 934 935 if (curr_cmd->cmd1 == NAND_CMD_RNDOUT || 936 curr_cmd->cmd1 == NAND_CMD_READ0) { 937 reg_val &= ~ARASAN_NAND_CMD_PG_SIZE_MASK; 938 page_val = arasan_nand_page(mtd); 939 reg_val |= (page_val << ARASAN_NAND_CMD_PG_SIZE_SHIFT); 940 } 941 942 reg_val &= ~ARASAN_NAND_CMD_ECC_ON_MASK; 943 944 reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK; 945 946 addr_cycles = arasan_nand_get_addrcycle(mtd); 947 948 if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL) 949 return ERR_ADDR_CYCLE; 950 951 reg_val |= (addr_cycles << 28); 952 writel(reg_val, &info->reg->cmd_reg); 953 954 if (page_addr == -1) 955 page_addr = 0; 956 957 page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) & 958 ARASAN_NAND_MEM_ADDR1_PAGE_MASK; 959 column &= ARASAN_NAND_MEM_ADDR1_COL_MASK; 960 writel(page | column, &info->reg->memadr_reg1); 961 962 reg_val = readl(&info->reg->memadr_reg2); 963 reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK; 964 reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT); 965 writel(reg_val, &info->reg->memadr_reg2); 966 967 buf_index = 0; 968 969 return 0; 970} 971 972static void arasan_nand_read_buf(struct mtd_info *mtd, u8 *buf, int size) 973{ 974 struct nand_chip *chip = mtd_to_nand(mtd); 975 struct nand_drv *info = nand_get_controller_data(chip); 976 u32 reg_val, i; 977 u32 *bufptr = (u32 *)buf; 978 u32 timeout = ARASAN_NAND_POLL_TIMEOUT; 979 980 reg_val = readl(&info->reg->pkt_reg); 981 reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK | 982 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK); 983 reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | size; 984 writel(reg_val, &info->reg->pkt_reg); 985 986 writel(curr_cmd->pgm, &info->reg->pgm_reg); 987 988 while (!(readl(&info->reg->intsts_reg) & 989 ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK) && timeout) { 990 udelay(1); 991 timeout--; 992 } 993 994 if (!timeout) 995 puts("ERROR:arasan_nand_read_buf timedout:Buff RDY\n"); 996 997 reg_val = readl(&info->reg->intsts_enr); 998 reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK; 999 writel(reg_val, &info->reg->intsts_enr); 1000 1001 writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, 1002 &info->reg->intsts_enr); 1003 reg_val = readl(&info->reg->intsts_reg); 1004 writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK, 1005 &info->reg->intsts_reg); 1006 1007 buf_index = 0; 1008 for (i = 0; i < size / 4; i++) 1009 bufptr[i] = readl(&info->reg->buf_dataport); 1010 1011 if (size & 0x03) 1012 bufptr[i] = readl(&info->reg->buf_dataport); 1013 1014 timeout = ARASAN_NAND_POLL_TIMEOUT; 1015 1016 while (!(readl(&info->reg->intsts_reg) & 1017 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) { 1018 udelay(1); 1019 timeout--; 1020 } 1021 1022 if (!timeout) 1023 puts("ERROR:arasan_nand_read_buf timedout:Xfer CMPLT\n"); 1024 1025 reg_val = readl(&info->reg->intsts_enr); 1026 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 1027 &info->reg->intsts_enr); 1028 reg_val = readl(&info->reg->intsts_reg); 1029 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 1030 &info->reg->intsts_reg); 1031} 1032 1033static u8 arasan_nand_read_byte(struct mtd_info *mtd) 1034{ 1035 struct nand_chip *chip = mtd_to_nand(mtd); 1036 struct nand_drv *info = nand_get_controller_data(chip); 1037 u32 size; 1038 u8 val; 1039 struct nand_onfi_params *p; 1040 1041 if (buf_index == 0) { 1042 p = &chip->onfi_params; 1043 if (curr_cmd->cmd1 == NAND_CMD_READID) 1044 size = 4; 1045 else if (curr_cmd->cmd1 == NAND_CMD_PARAM) 1046 size = sizeof(struct nand_onfi_params); 1047 else if (curr_cmd->cmd1 == NAND_CMD_RNDOUT) 1048 size = le16_to_cpu(p->ext_param_page_length) * 16; 1049 else if (curr_cmd->cmd1 == NAND_CMD_GET_FEATURES) 1050 size = 4; 1051 else if (curr_cmd->cmd1 == NAND_CMD_STATUS) 1052 return readb(&info->reg->flash_sts_reg); 1053 else 1054 size = 8; 1055 chip->read_buf(mtd, &buf_data[0], size); 1056 } 1057 1058 val = *(&buf_data[0] + buf_index); 1059 buf_index++; 1060 1061 return val; 1062} 1063 1064static void arasan_nand_cmd_function(struct mtd_info *mtd, unsigned int command, 1065 int column, int page_addr) 1066{ 1067 struct nand_chip *chip = mtd_to_nand(mtd); 1068 struct nand_drv *info = nand_get_controller_data(chip); 1069 struct nand_config *nand = &info->config; 1070 u32 i, ret = 0; 1071 1072 curr_cmd = NULL; 1073 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK, 1074 &info->reg->intsts_enr); 1075 1076 if ((command == NAND_CMD_READOOB) && 1077 (mtd->writesize > 512)) { 1078 column += mtd->writesize; 1079 command = NAND_CMD_READ0; 1080 } 1081 1082 /* Get the command format */ 1083 for (i = 0; (arasan_nand_commands[i].cmd1 != NAND_CMD_NONE || 1084 arasan_nand_commands[i].cmd2 != NAND_CMD_NONE); i++) { 1085 if (command == arasan_nand_commands[i].cmd1) { 1086 curr_cmd = &arasan_nand_commands[i]; 1087 break; 1088 } 1089 } 1090 1091 if (curr_cmd == NULL) { 1092 printf("Unsupported Command; 0x%x\n", command); 1093 return; 1094 } 1095 1096 if (curr_cmd->cmd1 == NAND_CMD_RESET) 1097 ret = arasan_nand_reset(mtd, curr_cmd); 1098 1099 if ((curr_cmd->cmd1 == NAND_CMD_READID) || 1100 (curr_cmd->cmd1 == NAND_CMD_PARAM) || 1101 (curr_cmd->cmd1 == NAND_CMD_RNDOUT) || 1102 (curr_cmd->cmd1 == NAND_CMD_GET_FEATURES) || 1103 (curr_cmd->cmd1 == NAND_CMD_READ0)) 1104 ret = arasan_nand_send_rdcmd(curr_cmd, column, page_addr, mtd); 1105 1106 if ((curr_cmd->cmd1 == NAND_CMD_SET_FEATURES) || 1107 (curr_cmd->cmd1 == NAND_CMD_SEQIN)) { 1108 nand->page = page_addr; 1109 ret = arasan_nand_send_wrcmd(curr_cmd, column, page_addr, mtd); 1110 } 1111 1112 if (curr_cmd->cmd1 == NAND_CMD_ERASE1) 1113 ret = arasan_nand_erase(curr_cmd, column, page_addr, mtd); 1114 1115 if (curr_cmd->cmd1 == NAND_CMD_STATUS) 1116 ret = arasan_nand_read_status(curr_cmd, column, page_addr, mtd); 1117 1118 if (ret != 0) 1119 printf("ERROR:%s:command:0x%x\n", __func__, curr_cmd->cmd1); 1120} 1121 1122static void arasan_check_ondie(struct mtd_info *mtd) 1123{ 1124 struct nand_chip *nand_chip = mtd_to_nand(mtd); 1125 struct nand_drv *info = nand_get_controller_data(nand_chip); 1126 struct nand_config *nand = &info->config; 1127 u8 maf_id, dev_id; 1128 u8 get_feature[4]; 1129 u8 set_feature[4] = {ENABLE_ONDIE_ECC, 0x00, 0x00, 0x00}; 1130 u32 i; 1131 1132 nand_chip->select_chip(mtd, 0); 1133 1134 /* Send the command for reading device ID */ 1135 nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); 1136 nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0, -1); 1137 1138 /* Read manufacturer and device IDs */ 1139 maf_id = nand_chip->read_byte(mtd); 1140 dev_id = nand_chip->read_byte(mtd); 1141 1142 if ((maf_id == NAND_MFR_MICRON) && 1143 ((dev_id == 0xf1) || (dev_id == 0xa1) || (dev_id == 0xb1) || 1144 (dev_id == 0xaa) || (dev_id == 0xba) || (dev_id == 0xda) || 1145 (dev_id == 0xca) || (dev_id == 0xac) || (dev_id == 0xbc) || 1146 (dev_id == 0xdc) || (dev_id == 0xcc) || (dev_id == 0xa3) || 1147 (dev_id == 0xb3) || (dev_id == 0xd3) || (dev_id == 0xc3))) { 1148 nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, 1149 ONDIE_ECC_FEATURE_ADDR, -1); 1150 1151 nand_chip->write_buf(mtd, &set_feature[0], 4); 1152 nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, 1153 ONDIE_ECC_FEATURE_ADDR, -1); 1154 1155 for (i = 0; i < 4; i++) 1156 get_feature[i] = nand_chip->read_byte(mtd); 1157 1158 if (get_feature[0] & ENABLE_ONDIE_ECC) { 1159 nand->on_die_ecc_enabled = true; 1160 printf("On-DIE ECC Enabled\n"); 1161 } else { 1162 printf("%s: Unable to enable OnDie ECC\n", __func__); 1163 } 1164 1165 /* Use the BBT pattern descriptors */ 1166 nand_chip->bbt_td = &bbt_main_descr; 1167 nand_chip->bbt_md = &bbt_mirror_descr; 1168 } 1169} 1170 1171static int arasan_nand_ecc_init(struct mtd_info *mtd) 1172{ 1173 struct nand_chip *nand_chip = mtd_to_nand(mtd); 1174 struct nand_drv *info = nand_get_controller_data(nand_chip); 1175 int found = -1; 1176 u32 regval, eccpos_start, i, eccaddr; 1177 1178 for (i = 0; i < ARRAY_SIZE(ecc_matrix); i++) { 1179 if ((ecc_matrix[i].pagesize == mtd->writesize) && 1180 (ecc_matrix[i].ecc_codeword_size >= 1181 nand_chip->ecc_step_ds)) { 1182 if (ecc_matrix[i].eccbits >= 1183 nand_chip->ecc_strength_ds) { 1184 found = i; 1185 break; 1186 } 1187 found = i; 1188 } 1189 } 1190 1191 if (found < 0) 1192 return 1; 1193 1194 eccaddr = mtd->writesize + mtd->oobsize - 1195 ecc_matrix[found].eccsize; 1196 1197 regval = eccaddr | 1198 (ecc_matrix[found].eccsize << ARASAN_NAND_ECC_SIZE_SHIFT) | 1199 (ecc_matrix[found].bch << ARASAN_NAND_ECC_BCH_SHIFT); 1200 writel(regval, &info->reg->ecc_reg); 1201 1202 if (ecc_matrix[found].bch) { 1203 regval = readl(&info->reg->memadr_reg2); 1204 regval &= ~ARASAN_NAND_MEM_ADDR2_BCH_MASK; 1205 regval |= (ecc_matrix[found].bchval << 1206 ARASAN_NAND_MEM_ADDR2_BCH_SHIFT); 1207 writel(regval, &info->reg->memadr_reg2); 1208 } 1209 1210 nand_oob.eccbytes = ecc_matrix[found].eccsize; 1211 eccpos_start = mtd->oobsize - nand_oob.eccbytes; 1212 1213 for (i = 0; i < nand_oob.eccbytes; i++) 1214 nand_oob.eccpos[i] = eccpos_start + i; 1215 1216 nand_oob.oobfree[0].offset = 2; 1217 nand_oob.oobfree[0].length = eccpos_start - 2; 1218 1219 nand_chip->ecc.size = ecc_matrix[found].ecc_codeword_size; 1220 nand_chip->ecc.strength = ecc_matrix[found].eccbits; 1221 nand_chip->ecc.bytes = ecc_matrix[found].eccsize; 1222 nand_chip->ecc.layout = &nand_oob; 1223 1224 return 0; 1225} 1226 1227static int arasan_probe(struct udevice *dev) 1228{ 1229 struct arasan_nand_info *arasan = dev_get_priv(dev); 1230 struct nand_chip *nand_chip = &arasan->nand_chip; 1231 struct nand_drv *info = &arasan->nand_ctrl; 1232 struct nand_config *nand = &info->config; 1233 struct mtd_info *mtd; 1234 ofnode child; 1235 int ret; 1236 const char *str; 1237 1238 info->reg = dev_read_addr_ptr(dev); 1239 mtd = nand_to_mtd(nand_chip); 1240 nand_set_controller_data(nand_chip, &arasan->nand_ctrl); 1241 1242 ofnode_for_each_subnode(child, dev_ofnode(dev)) 1243 nand_set_flash_node(nand_chip, child); 1244 1245#ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE 1246 nand_chip->options |= NAND_NO_SUBPAGE_WRITE; 1247#endif 1248 1249 /* Set the driver entry points for MTD */ 1250 nand_chip->cmdfunc = arasan_nand_cmd_function; 1251 nand_chip->select_chip = arasan_nand_select_chip; 1252 nand_chip->read_byte = arasan_nand_read_byte; 1253 1254 /* Buffer read/write routines */ 1255 nand_chip->read_buf = arasan_nand_read_buf; 1256 nand_chip->write_buf = arasan_nand_write_buf; 1257 1258 writel(0x0, &info->reg->cmd_reg); 1259 writel(0x0, &info->reg->pgm_reg); 1260 1261 /* first scan to find the device and get the page size */ 1262 ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL); 1263 if (ret) { 1264 printf("%s: nand_scan_ident failed\n", __func__); 1265 return ret; 1266 } 1267 1268 str = ofnode_read_string(nand_chip->flash_node, "nand-ecc-mode"); 1269 if (!str || strcmp(str, "hw") != 0) { 1270 printf("%s ecc mode is not supported\n", str); 1271 return -EINVAL; 1272 } 1273 1274 nand_chip->ecc.mode = NAND_ECC_HW; 1275 nand_chip->ecc.hwctl = NULL; 1276 nand_chip->ecc.read_page = arasan_nand_read_page_hwecc; 1277 nand_chip->ecc.write_page = arasan_nand_write_page_hwecc; 1278 nand_chip->ecc.read_oob = arasan_nand_read_oob; 1279 nand_chip->ecc.write_oob = arasan_nand_write_oob; 1280 1281 arasan_check_ondie(mtd); 1282 1283 /* 1284 * If on die supported, then give priority to on-die ecc and use 1285 * it instead of controller ecc. 1286 */ 1287 if (nand->on_die_ecc_enabled) { 1288 nand_chip->ecc.strength = 1; 1289 nand_chip->ecc.size = mtd->writesize; 1290 nand_chip->ecc.bytes = 0; 1291 nand_chip->ecc.layout = &ondie_nand_oob_64; 1292 } else { 1293 ret = arasan_nand_ecc_init(mtd); 1294 if (ret) { 1295 printf("%s: nand_ecc_init failed\n", __func__); 1296 return ret; 1297 } 1298 } 1299 1300 ret = nand_scan_tail(mtd); 1301 if (ret) { 1302 printf("%s: nand_scan_tail failed\n", __func__); 1303 return ret; 1304 } 1305 1306 ret = nand_register(0, mtd); 1307 if (ret) { 1308 printf("Nand Register Fail\n"); 1309 return ret; 1310 } 1311 1312 return ret; 1313} 1314 1315static const struct udevice_id arasan_nand_dt_ids[] = { 1316 {.compatible = "arasan,nfc-v3p10",}, 1317 { /* sentinel */ } 1318}; 1319 1320U_BOOT_DRIVER(arasan_nand) = { 1321 .name = "arasan_nand", 1322 .id = UCLASS_MTD, 1323 .of_match = arasan_nand_dt_ids, 1324 .probe = arasan_probe, 1325 .priv_auto = sizeof(struct arasan_nand_info), 1326}; 1327 1328void board_nand_init(void) 1329{ 1330 struct udevice *dev; 1331 int ret; 1332 1333 ret = uclass_get_device_by_driver(UCLASS_MTD, 1334 DM_DRIVER_GET(arasan_nand), &dev); 1335 if (ret && ret != -ENODEV) 1336 pr_err("Failed to initialize %s. (error %d)\n", dev->name, ret); 1337} 1338