1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2009 SAMSUNG Electronics 4 * Minkyu Kang <mk7.kang@samsung.com> 5 * Jaehoon Chung <jh80.chung@samsung.com> 6 * Portions Copyright 2011-2019 NVIDIA Corporation 7 */ 8 9#include <bouncebuf.h> 10#include <dm.h> 11#include <errno.h> 12#include <log.h> 13#include <mmc.h> 14#include <asm/gpio.h> 15#include <asm/io.h> 16#include <asm/arch-tegra/tegra_mmc.h> 17#include <linux/bitops.h> 18#include <linux/delay.h> 19#include <linux/err.h> 20#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210) 21#include <asm/arch/clock.h> 22#endif 23 24struct tegra_mmc_plat { 25 struct mmc_config cfg; 26 struct mmc mmc; 27}; 28 29struct tegra_mmc_priv { 30 struct tegra_mmc *reg; 31 struct reset_ctl reset_ctl; 32 struct clk clk; 33 struct gpio_desc cd_gpio; /* Change Detect GPIO */ 34 struct gpio_desc pwr_gpio; /* Power GPIO */ 35 struct gpio_desc wp_gpio; /* Write Protect GPIO */ 36 unsigned int version; /* SDHCI spec. version */ 37 unsigned int clock; /* Current clock (MHz) */ 38 int mmc_id; /* peripheral id */ 39 40 int tap_value; 41 int trim_value; 42}; 43 44static void tegra_mmc_set_power(struct tegra_mmc_priv *priv, 45 unsigned short power) 46{ 47 u8 pwr = 0; 48 debug("%s: power = %x\n", __func__, power); 49 50 if (power != (unsigned short)-1) { 51 switch (1 << power) { 52 case MMC_VDD_165_195: 53 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8; 54 break; 55 case MMC_VDD_29_30: 56 case MMC_VDD_30_31: 57 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0; 58 break; 59 case MMC_VDD_32_33: 60 case MMC_VDD_33_34: 61 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3; 62 break; 63 } 64 } 65 debug("%s: pwr = %X\n", __func__, pwr); 66 67 /* Set the bus voltage first (if any) */ 68 writeb(pwr, &priv->reg->pwrcon); 69 if (pwr == 0) 70 return; 71 72 /* Now enable bus power */ 73 pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER; 74 writeb(pwr, &priv->reg->pwrcon); 75} 76 77static void tegra_mmc_prepare_data(struct tegra_mmc_priv *priv, 78 struct mmc_data *data, 79 struct bounce_buffer *bbstate) 80{ 81 unsigned char ctrl; 82 83 84 debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n", 85 bbstate->bounce_buffer, bbstate->user_buffer, data->blocks, 86 data->blocksize); 87 88 writel((u32)(unsigned long)bbstate->bounce_buffer, &priv->reg->sysad); 89 /* 90 * DMASEL[4:3] 91 * 00 = Selects SDMA 92 * 01 = Reserved 93 * 10 = Selects 32-bit Address ADMA2 94 * 11 = Selects 64-bit Address ADMA2 95 */ 96 ctrl = readb(&priv->reg->hostctl); 97 ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK; 98 ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA; 99 writeb(ctrl, &priv->reg->hostctl); 100 101 /* We do not handle DMA boundaries, so set it to max (512 KiB) */ 102 writew((7 << 12) | (data->blocksize & 0xFFF), &priv->reg->blksize); 103 writew(data->blocks, &priv->reg->blkcnt); 104} 105 106static void tegra_mmc_set_transfer_mode(struct tegra_mmc_priv *priv, 107 struct mmc_data *data) 108{ 109 unsigned short mode; 110 debug(" mmc_set_transfer_mode called\n"); 111 /* 112 * TRNMOD 113 * MUL1SIN0[5] : Multi/Single Block Select 114 * RD1WT0[4] : Data Transfer Direction Select 115 * 1 = read 116 * 0 = write 117 * ENACMD12[2] : Auto CMD12 Enable 118 * ENBLKCNT[1] : Block Count Enable 119 * ENDMA[0] : DMA Enable 120 */ 121 mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE | 122 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE); 123 124 if (data->blocks > 1) 125 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT; 126 127 if (data->flags & MMC_DATA_READ) 128 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ; 129 130 writew(mode, &priv->reg->trnmod); 131} 132 133static int tegra_mmc_wait_inhibit(struct tegra_mmc_priv *priv, 134 struct mmc_cmd *cmd, 135 struct mmc_data *data, 136 unsigned int timeout) 137{ 138 /* 139 * PRNSTS 140 * CMDINHDAT[1] : Command Inhibit (DAT) 141 * CMDINHCMD[0] : Command Inhibit (CMD) 142 */ 143 unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD; 144 145 /* 146 * We shouldn't wait for data inhibit for stop commands, even 147 * though they might use busy signaling 148 */ 149 if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY)) 150 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT; 151 152 while (readl(&priv->reg->prnsts) & mask) { 153 if (timeout == 0) { 154 printf("%s: timeout error\n", __func__); 155 return -1; 156 } 157 timeout--; 158 udelay(1000); 159 } 160 161 return 0; 162} 163 164static int tegra_mmc_send_cmd_bounced(struct udevice *dev, struct mmc_cmd *cmd, 165 struct mmc_data *data, 166 struct bounce_buffer *bbstate) 167{ 168 struct tegra_mmc_priv *priv = dev_get_priv(dev); 169 int flags, i; 170 int result; 171 unsigned int mask = 0; 172 unsigned int retry = 0x100000; 173 debug(" mmc_send_cmd called\n"); 174 175 result = tegra_mmc_wait_inhibit(priv, cmd, data, 10 /* ms */); 176 177 if (result < 0) 178 return result; 179 180 if (data) 181 tegra_mmc_prepare_data(priv, data, bbstate); 182 183 debug("cmd->arg: %08x\n", cmd->cmdarg); 184 writel(cmd->cmdarg, &priv->reg->argument); 185 186 if (data) 187 tegra_mmc_set_transfer_mode(priv, data); 188 189 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) 190 return -1; 191 192 /* 193 * CMDREG 194 * CMDIDX[13:8] : Command index 195 * DATAPRNT[5] : Data Present Select 196 * ENCMDIDX[4] : Command Index Check Enable 197 * ENCMDCRC[3] : Command CRC Check Enable 198 * RSPTYP[1:0] 199 * 00 = No Response 200 * 01 = Length 136 201 * 10 = Length 48 202 * 11 = Length 48 Check busy after response 203 */ 204 if (!(cmd->resp_type & MMC_RSP_PRESENT)) 205 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE; 206 else if (cmd->resp_type & MMC_RSP_136) 207 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136; 208 else if (cmd->resp_type & MMC_RSP_BUSY) 209 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY; 210 else 211 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48; 212 213 if (cmd->resp_type & MMC_RSP_CRC) 214 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK; 215 if (cmd->resp_type & MMC_RSP_OPCODE) 216 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK; 217 if (data) 218 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER; 219 220 debug("cmd: %d\n", cmd->cmdidx); 221 222 writew((cmd->cmdidx << 8) | flags, &priv->reg->cmdreg); 223 224 for (i = 0; i < retry; i++) { 225 mask = readl(&priv->reg->norintsts); 226 /* Command Complete */ 227 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) { 228 if (!data) 229 writel(mask, &priv->reg->norintsts); 230 break; 231 } 232 } 233 234 if (i == retry) { 235 printf("%s: waiting for status update\n", __func__); 236 writel(mask, &priv->reg->norintsts); 237 return -ETIMEDOUT; 238 } 239 240 if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) { 241 /* Timeout Error */ 242 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx); 243 writel(mask, &priv->reg->norintsts); 244 return -ETIMEDOUT; 245 } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { 246 /* Error Interrupt */ 247 debug("error: %08x cmd %d\n", mask, cmd->cmdidx); 248 writel(mask, &priv->reg->norintsts); 249 return -1; 250 } 251 252 if (cmd->resp_type & MMC_RSP_PRESENT) { 253 if (cmd->resp_type & MMC_RSP_136) { 254 /* CRC is stripped so we need to do some shifting. */ 255 for (i = 0; i < 4; i++) { 256 unsigned long offset = (unsigned long) 257 (&priv->reg->rspreg3 - i); 258 cmd->response[i] = readl(offset) << 8; 259 260 if (i != 3) { 261 cmd->response[i] |= 262 readb(offset - 1); 263 } 264 debug("cmd->resp[%d]: %08x\n", 265 i, cmd->response[i]); 266 } 267 } else if (cmd->resp_type & MMC_RSP_BUSY) { 268 for (i = 0; i < retry; i++) { 269 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */ 270 if (readl(&priv->reg->prnsts) 271 & (1 << 20)) /* DAT[0] */ 272 break; 273 } 274 275 if (i == retry) { 276 printf("%s: card is still busy\n", __func__); 277 writel(mask, &priv->reg->norintsts); 278 return -ETIMEDOUT; 279 } 280 281 cmd->response[0] = readl(&priv->reg->rspreg0); 282 debug("cmd->resp[0]: %08x\n", cmd->response[0]); 283 } else { 284 cmd->response[0] = readl(&priv->reg->rspreg0); 285 debug("cmd->resp[0]: %08x\n", cmd->response[0]); 286 } 287 } 288 289 if (data) { 290 unsigned long start = get_timer(0); 291 292 while (1) { 293 mask = readl(&priv->reg->norintsts); 294 295 if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { 296 /* Error Interrupt */ 297 writel(mask, &priv->reg->norintsts); 298 printf("%s: error during transfer: 0x%08x\n", 299 __func__, mask); 300 return -1; 301 } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) { 302 /* 303 * DMA Interrupt, restart the transfer where 304 * it was interrupted. 305 */ 306 unsigned int address = readl(&priv->reg->sysad); 307 308 debug("DMA end\n"); 309 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT, 310 &priv->reg->norintsts); 311 writel(address, &priv->reg->sysad); 312 } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) { 313 /* Transfer Complete */ 314 debug("r/w is done\n"); 315 break; 316 } else if (get_timer(start) > 8000UL) { 317 writel(mask, &priv->reg->norintsts); 318 printf("%s: MMC Timeout\n" 319 " Interrupt status 0x%08x\n" 320 " Interrupt status enable 0x%08x\n" 321 " Interrupt signal enable 0x%08x\n" 322 " Present status 0x%08x\n", 323 __func__, mask, 324 readl(&priv->reg->norintstsen), 325 readl(&priv->reg->norintsigen), 326 readl(&priv->reg->prnsts)); 327 return -1; 328 } 329 } 330 writel(mask, &priv->reg->norintsts); 331 } 332 333 udelay(1000); 334 return 0; 335} 336 337static int tegra_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 338 struct mmc_data *data) 339{ 340 void *buf; 341 unsigned int bbflags; 342 size_t len; 343 struct bounce_buffer bbstate; 344 int ret; 345 346 if (data) { 347 if (data->flags & MMC_DATA_READ) { 348 buf = data->dest; 349 bbflags = GEN_BB_WRITE; 350 } else { 351 buf = (void *)data->src; 352 bbflags = GEN_BB_READ; 353 } 354 len = data->blocks * data->blocksize; 355 356 bounce_buffer_start(&bbstate, buf, len, bbflags); 357 } 358 359 ret = tegra_mmc_send_cmd_bounced(dev, cmd, data, &bbstate); 360 361 if (data) 362 bounce_buffer_stop(&bbstate); 363 364 return ret; 365} 366 367static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock) 368{ 369 ulong rate; 370 int div; 371 unsigned short clk; 372 unsigned long timeout; 373 374 debug(" mmc_change_clock called\n"); 375 376 /* 377 * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0 378 */ 379 if (clock == 0) 380 goto out; 381 382 rate = clk_set_rate(&priv->clk, clock); 383 div = (rate + clock - 1) / clock; 384 385#if defined(CONFIG_TEGRA210) 386 if (priv->mmc_id == PERIPH_ID_SDMMC1 && clock <= 400000) { 387 /* clock_adjust_periph_pll_div() chooses a 'bad' clock 388 * on SDMMC1 T210, so skip it here and force a clock 389 * that's been spec'd in the table in the TRM for 390 * card-detect (400KHz). 391 */ 392 uint effective_rate = clock_adjust_periph_pll_div(priv->mmc_id, 393 CLOCK_ID_PERIPH, 24727273, NULL); 394 div = 62; 395 396 debug("%s: WAR: Using SDMMC1 clock of %u, div %d to achieve %dHz card clock ...\n", 397 __func__, effective_rate, div, clock); 398 } else { 399 clock_adjust_periph_pll_div(priv->mmc_id, CLOCK_ID_PERIPH, 400 clock, &div); 401 } 402#endif 403 debug("div = %d\n", div); 404 405 writew(0, &priv->reg->clkcon); 406 407 /* 408 * CLKCON 409 * SELFREQ[15:8] : base clock divided by value 410 * ENSDCLK[2] : SD Clock Enable 411 * STBLINTCLK[1] : Internal Clock Stable 412 * ENINTCLK[0] : Internal Clock Enable 413 */ 414 div >>= 1; 415 clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) | 416 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE); 417 writew(clk, &priv->reg->clkcon); 418 419 /* Wait max 10 ms */ 420 timeout = 10; 421 while (!(readw(&priv->reg->clkcon) & 422 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) { 423 if (timeout == 0) { 424 printf("%s: timeout error\n", __func__); 425 return; 426 } 427 timeout--; 428 udelay(1000); 429 } 430 431 clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; 432 writew(clk, &priv->reg->clkcon); 433 434 debug("mmc_change_clock: clkcon = %08X\n", clk); 435 436out: 437 priv->clock = clock; 438} 439 440static int tegra_mmc_set_ios(struct udevice *dev) 441{ 442 struct tegra_mmc_priv *priv = dev_get_priv(dev); 443 struct mmc *mmc = mmc_get_mmc_dev(dev); 444 unsigned char ctrl; 445 debug(" mmc_set_ios called\n"); 446 447 debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock); 448 449 /* Change clock first */ 450 tegra_mmc_change_clock(priv, mmc->clock); 451 452 ctrl = readb(&priv->reg->hostctl); 453 454 /* 455 * WIDE8[5] 456 * 0 = Depend on WIDE4 457 * 1 = 8-bit mode 458 * WIDE4[1] 459 * 1 = 4-bit mode 460 * 0 = 1-bit mode 461 */ 462 if (mmc->bus_width == 8) 463 ctrl |= (1 << 5); 464 else if (mmc->bus_width == 4) 465 ctrl |= (1 << 1); 466 else 467 ctrl &= ~(1 << 1 | 1 << 5); 468 469 writeb(ctrl, &priv->reg->hostctl); 470 debug("mmc_set_ios: hostctl = %08X\n", ctrl); 471 472 return 0; 473} 474 475static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv) 476{ 477#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210) 478 u32 val; 479 u16 clk_con; 480 int timeout; 481 int id = priv->mmc_id; 482 483 debug("%s: sdmmc address = %p, id = %d\n", __func__, 484 priv->reg, id); 485 486 /* Set the pad drive strength for SDMMC1 or 3 only */ 487 if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) { 488 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", 489 __func__); 490 return; 491 } 492 493 val = readl(&priv->reg->sdmemcmppadctl); 494 val &= 0xFFFFFFF0; 495 val |= MEMCOMP_PADCTRL_VREF; 496 writel(val, &priv->reg->sdmemcmppadctl); 497 498 /* Disable SD Clock Enable before running auto-cal as per TRM */ 499 clk_con = readw(&priv->reg->clkcon); 500 debug("%s: CLOCK_CONTROL = 0x%04X\n", __func__, clk_con); 501 clk_con &= ~TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; 502 writew(clk_con, &priv->reg->clkcon); 503 504 val = readl(&priv->reg->autocalcfg); 505 val &= 0xFFFF0000; 506 val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET; 507 writel(val, &priv->reg->autocalcfg); 508 val |= AUTO_CAL_START | AUTO_CAL_ENABLE; 509 writel(val, &priv->reg->autocalcfg); 510 debug("%s: AUTO_CAL_CFG = 0x%08X\n", __func__, val); 511 udelay(1); 512 timeout = 100; /* 10 mSec max (100*100uS) */ 513 do { 514 val = readl(&priv->reg->autocalsts); 515 udelay(100); 516 } while ((val & AUTO_CAL_ACTIVE) && --timeout); 517 val = readl(&priv->reg->autocalsts); 518 debug("%s: Final AUTO_CAL_STATUS = 0x%08X, timeout = %d\n", 519 __func__, val, timeout); 520 521 /* Re-enable SD Clock Enable when auto-cal is done */ 522 clk_con |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; 523 writew(clk_con, &priv->reg->clkcon); 524 clk_con = readw(&priv->reg->clkcon); 525 debug("%s: final CLOCK_CONTROL = 0x%04X\n", __func__, clk_con); 526 527 if (timeout == 0) { 528 printf("%s: Warning: Autocal timed out!\n", __func__); 529 /* TBD: Set CFG2TMC_SDMMC1_PAD_CAL_DRV* regs here */ 530 } 531#endif /* T30/T210 */ 532} 533 534static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc) 535{ 536 unsigned int timeout; 537 debug(" mmc_reset called\n"); 538 539 /* 540 * RSTALL[0] : Software reset for all 541 * 1 = reset 542 * 0 = work 543 */ 544 writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &priv->reg->swrst); 545 546 priv->clock = 0; 547 548 /* Wait max 100 ms */ 549 timeout = 100; 550 551 /* hw clears the bit when it's done */ 552 while (readb(&priv->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) { 553 if (timeout == 0) { 554 printf("%s: timeout error\n", __func__); 555 return; 556 } 557 timeout--; 558 udelay(1000); 559 } 560 561 /* Set SD bus voltage & enable bus power */ 562 tegra_mmc_set_power(priv, fls(mmc->cfg->voltages) - 1); 563 debug("%s: power control = %02X, host control = %02X\n", __func__, 564 readb(&priv->reg->pwrcon), readb(&priv->reg->hostctl)); 565 566 /* Make sure SDIO pads are set up */ 567 tegra_mmc_pad_init(priv); 568 569 if (!IS_ERR_VALUE(priv->tap_value) || 570 !IS_ERR_VALUE(priv->trim_value)) { 571 u32 val; 572 573 val = readl(&priv->reg->venclkctl); 574 575 val &= ~TRIM_VAL_MASK; 576 val |= (priv->trim_value << TRIM_VAL_SHIFT); 577 578 val &= ~TAP_VAL_MASK; 579 val |= (priv->tap_value << TAP_VAL_SHIFT); 580 581 writel(val, &priv->reg->venclkctl); 582 debug("%s: VENDOR_CLOCK_CNTRL = 0x%08X\n", __func__, val); 583 } 584} 585 586static int tegra_mmc_init(struct udevice *dev) 587{ 588 struct tegra_mmc_priv *priv = dev_get_priv(dev); 589 struct mmc *mmc = mmc_get_mmc_dev(dev); 590 unsigned int mask; 591 debug(" tegra_mmc_init called\n"); 592 593#if defined(CONFIG_TEGRA210) 594 priv->mmc_id = clock_decode_periph_id(dev); 595 if (priv->mmc_id == PERIPH_ID_NONE) { 596 printf("%s: Missing/invalid peripheral ID\n", __func__); 597 return -EINVAL; 598 } 599#endif 600 tegra_mmc_reset(priv, mmc); 601 602#if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK) 603 /* 604 * Disable the external clock loopback and use the internal one on 605 * SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 606 * bits being set to 0xfffd according to the TRM. 607 * 608 * TODO(marcel.ziswiler@toradex.com): Move to device tree controlled 609 * approach once proper kernel integration made it mainline. 610 */ 611 if (priv->reg == (void *)0x700b0400) { 612 mask = readl(&priv->reg->venmiscctl); 613 mask &= ~TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK; 614 writel(mask, &priv->reg->venmiscctl); 615 } 616#endif 617 618 priv->version = readw(&priv->reg->hcver); 619 debug("host version = %x\n", priv->version); 620 621 /* mask all */ 622 writel(0xffffffff, &priv->reg->norintstsen); 623 writel(0xffffffff, &priv->reg->norintsigen); 624 625 writeb(0xe, &priv->reg->timeoutcon); /* TMCLK * 2^27 */ 626 /* 627 * NORMAL Interrupt Status Enable Register init 628 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable 629 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable 630 * [3] ENSTADMAINT : DMA boundary interrupt 631 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable 632 * [0] ENSTACMDCMPLT : Command Complete Status Enable 633 */ 634 mask = readl(&priv->reg->norintstsen); 635 mask &= ~(0xffff); 636 mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE | 637 TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE | 638 TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT | 639 TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY | 640 TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY); 641 writel(mask, &priv->reg->norintstsen); 642 643 /* 644 * NORMAL Interrupt Signal Enable Register init 645 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable 646 */ 647 mask = readl(&priv->reg->norintsigen); 648 mask &= ~(0xffff); 649 mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE; 650 writel(mask, &priv->reg->norintsigen); 651 652 return 0; 653} 654 655static int tegra_mmc_getcd(struct udevice *dev) 656{ 657 struct tegra_mmc_priv *priv = dev_get_priv(dev); 658 659 debug("tegra_mmc_getcd called\n"); 660 661 if (dm_gpio_is_valid(&priv->cd_gpio)) 662 return dm_gpio_get_value(&priv->cd_gpio); 663 664 return 1; 665} 666 667static const struct dm_mmc_ops tegra_mmc_ops = { 668 .send_cmd = tegra_mmc_send_cmd, 669 .set_ios = tegra_mmc_set_ios, 670 .get_cd = tegra_mmc_getcd, 671}; 672 673static int tegra_mmc_probe(struct udevice *dev) 674{ 675 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 676 struct tegra_mmc_plat *plat = dev_get_plat(dev); 677 struct tegra_mmc_priv *priv = dev_get_priv(dev); 678 struct mmc_config *cfg = &plat->cfg; 679 int bus_width, ret; 680 681 cfg->name = dev->name; 682 683 bus_width = dev_read_u32_default(dev, "bus-width", 1); 684 685 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 686 cfg->host_caps = 0; 687 if (bus_width == 8) 688 cfg->host_caps |= MMC_MODE_8BIT; 689 if (bus_width >= 4) 690 cfg->host_caps |= MMC_MODE_4BIT; 691 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 692 693 /* 694 * min freq is for card identification, and is the highest 695 * low-speed SDIO card frequency (actually 400KHz) 696 * max freq is highest HS eMMC clock as per the SD/MMC spec 697 * (actually 52MHz) 698 */ 699 cfg->f_min = 375000; 700 cfg->f_max = dev_read_u32_default(dev, "max-frequency", 48000000); 701 702 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; 703 704 priv->reg = dev_read_addr_ptr(dev); 705 706 ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl); 707 if (ret) { 708 debug("reset_get_by_name() failed: %d\n", ret); 709 return ret; 710 } 711 ret = clk_get_by_index(dev, 0, &priv->clk); 712 if (ret) { 713 debug("clk_get_by_index() failed: %d\n", ret); 714 return ret; 715 } 716 717 ret = reset_assert(&priv->reset_ctl); 718 if (ret) 719 return ret; 720 ret = clk_enable(&priv->clk); 721 if (ret) 722 return ret; 723 ret = clk_set_rate(&priv->clk, 20000000); 724 if (IS_ERR_VALUE(ret)) 725 return ret; 726 ret = reset_deassert(&priv->reset_ctl); 727 if (ret) 728 return ret; 729 730 /* These GPIOs are optional */ 731 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN); 732 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN); 733 gpio_request_by_name(dev, "power-gpios", 0, &priv->pwr_gpio, 734 GPIOD_IS_OUT); 735 if (dm_gpio_is_valid(&priv->pwr_gpio)) 736 dm_gpio_set_value(&priv->pwr_gpio, 1); 737 738 ret = dev_read_u32(dev, "nvidia,default-tap", &priv->tap_value); 739 if (ret) 740 priv->tap_value = ret; 741 742 ret = dev_read_u32(dev, "nvidia,default-trim", &priv->trim_value); 743 if (ret) 744 priv->trim_value = ret; 745 746 upriv->mmc = &plat->mmc; 747 748 return tegra_mmc_init(dev); 749} 750 751static int tegra_mmc_bind(struct udevice *dev) 752{ 753 struct tegra_mmc_plat *plat = dev_get_plat(dev); 754 755 return mmc_bind(dev, &plat->mmc, &plat->cfg); 756} 757 758static const struct udevice_id tegra_mmc_ids[] = { 759 { .compatible = "nvidia,tegra20-sdhci" }, 760 { .compatible = "nvidia,tegra30-sdhci" }, 761 { .compatible = "nvidia,tegra114-sdhci" }, 762 { .compatible = "nvidia,tegra124-sdhci" }, 763 { .compatible = "nvidia,tegra210-sdhci" }, 764 { .compatible = "nvidia,tegra186-sdhci" }, 765 { } 766}; 767 768U_BOOT_DRIVER(tegra_mmc_drv) = { 769 .name = "tegra_mmc", 770 .id = UCLASS_MMC, 771 .of_match = tegra_mmc_ids, 772 .bind = tegra_mmc_bind, 773 .probe = tegra_mmc_probe, 774 .ops = &tegra_mmc_ops, 775 .plat_auto = sizeof(struct tegra_mmc_plat), 776 .priv_auto = sizeof(struct tegra_mmc_priv), 777}; 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