1menu "Mailbox Controller Support" 2 3config DM_MAILBOX 4 bool "Enable mailbox controllers using Driver Model" 5 depends on DM && OF_CONTROL 6 help 7 Enable support for the mailbox driver class. Mailboxes provide the 8 ability to transfer small messages and/or notifications from one 9 CPU to another CPU, or sometimes to dedicated HW modules. They form 10 the basis of a variety of inter-process/inter-CPU communication 11 protocols. 12 13config APPLE_MBOX 14 bool "Enable Apple IOP controller support" 15 depends on DM_MAILBOX && ARCH_APPLE 16 default y 17 help 18 Enable support for the mailboxes that provide a comminucation 19 channel with Apple IOP controllers integrated on Apple SoCs. 20 These IOP controllers are used to implement various functions 21 such as the System Management Controller (SMC) and NVMe and this 22 driver is required to get that functionality up and running. 23 24config SANDBOX_MBOX 25 bool "Enable the sandbox mailbox test driver" 26 depends on DM_MAILBOX && SANDBOX 27 help 28 Enable support for a test mailbox implementation, which simply echos 29 back a modified version of any message that is sent. 30 31config TEGRA_HSP 32 bool "Enable Tegra HSP controller support" 33 depends on DM_MAILBOX && ARCH_TEGRA 34 help 35 This enables support for the NVIDIA Tegra HSP Hw module, which 36 implements doorbells, mailboxes, semaphores, and shared interrupts. 37 38config STM32_IPCC 39 bool "Enable STM32 IPCC controller support" 40 depends on DM_MAILBOX && ARCH_STM32MP 41 help 42 This enables support for the STM32MP IPCC Hw module, which 43 implements doorbells between 2 processors. 44 45config K3_SEC_PROXY 46 bool "Texas Instruments K3 Secure Proxy Driver" 47 depends on DM_MAILBOX && ARCH_K3 48 help 49 An implementation of Secure proxy slave driver for K3 SoCs from 50 Texas Instruments. Secure proxy is a communication entity mainly 51 used for communication between multiple processors with the SoC. 52 Select this driver if your platform has support for this hardware 53 block. 54 55config ZYNQMP_IPI 56 bool "Xilinx ZynqMP IPI controller support" 57 depends on DM_MAILBOX && (ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET) 58 help 59 This enables support for the Xilinx ZynqMP Inter Processor Interrupt 60 communication controller. 61endmenu 62