1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2012 Samsung Electronics
4 */
5
6#ifndef _S3C24X0_I2C_H
7#define _S3C24X0_I2C_H
8
9struct s3c24x0_i2c {
10	u32	iiccon;
11	u32	iicstat;
12	u32	iicadd;
13	u32	iicds;
14	u32	iiclc;
15};
16
17struct exynos5_hsi2c {
18	u32	usi_ctl;
19	u32	usi_fifo_ctl;
20	u32	usi_trailing_ctl;
21	u32	usi_clk_ctl;
22	u32	usi_clk_slot;
23	u32	spi_ctl;
24	u32	uart_ctl;
25	u32	res1;
26	u32	usi_int_en;
27	u32	usi_int_stat;
28	u32	usi_modem_stat;
29	u32	usi_error_stat;
30	u32	usi_fifo_stat;
31	u32	usi_txdata;
32	u32	usi_rxdata;
33	u32	res2;
34	u32	usi_conf;
35	u32	usi_auto_conf;
36	u32	usi_timeout;
37	u32	usi_manual_cmd;
38	u32	usi_trans_status;
39	u32	usi_timing_hs1;
40	u32	usi_timing_hs2;
41	u32	usi_timing_hs3;
42	u32	usi_timing_fs1;
43	u32	usi_timing_fs2;
44	u32	usi_timing_fs3;
45	u32	usi_timing_sla;
46	u32	i2c_addr;
47};
48
49struct s3c24x0_i2c_bus {
50	bool active;	/* port is active and available */
51	int node;	/* device tree node */
52	int bus_num;	/* i2c bus number */
53	struct s3c24x0_i2c *regs;
54	struct exynos5_hsi2c *hsregs;
55	int is_highspeed;	/* High speed type, rather than I2C */
56	unsigned clock_frequency;
57	int id;
58	unsigned clk_cycle;
59	unsigned clk_div;
60};
61
62#define	I2C_WRITE	0
63#define I2C_READ	1
64
65#define I2C_OK		0
66#define I2C_NOK		1
67#define I2C_NACK	2
68#define I2C_NOK_LA	3	/* Lost arbitration */
69#define I2C_NOK_TOUT	4	/* time out */
70
71/* S3C I2C Controller bits */
72#define I2CSTAT_BSY	0x20	/* Busy bit */
73#define I2CSTAT_NACK	0x01	/* Nack bit */
74#define I2CCON_ACKGEN	0x80	/* Acknowledge generation */
75#define I2CCON_IRPND	0x10	/* Interrupt pending bit */
76#define I2C_MODE_MT	0xC0	/* Master Transmit Mode */
77#define I2C_MODE_MR	0x80	/* Master Receive Mode */
78#define I2C_START_STOP	0x20	/* START / STOP */
79#define I2C_TXRX_ENA	0x10	/* I2C Tx/Rx enable */
80
81#define I2C_TIMEOUT_MS 10		/* 10 ms */
82
83#endif /* _S3C24X0_I2C_H */
84