1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (c) 2016, Google Inc 4 * 5 * (C) Copyright 2002 6 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch 7 */ 8 9#include <common.h> 10#include <dm.h> 11#include <i2c.h> 12#include <log.h> 13#include <asm/arch/clk.h> 14#include <asm/arch/cpu.h> 15#include <asm/arch/pinmux.h> 16#include <asm/global_data.h> 17#include <linux/delay.h> 18#include "s3c24x0_i2c.h" 19 20DECLARE_GLOBAL_DATA_PTR; 21 22/* HSI2C-specific register description */ 23 24/* I2C_CTL Register bits */ 25#define HSI2C_FUNC_MODE_I2C (1u << 0) 26#define HSI2C_MASTER (1u << 3) 27#define HSI2C_RXCHON (1u << 6) /* Write/Send */ 28#define HSI2C_TXCHON (1u << 7) /* Read/Receive */ 29#define HSI2C_SW_RST (1u << 31) 30 31/* I2C_FIFO_CTL Register bits */ 32#define HSI2C_RXFIFO_EN (1u << 0) 33#define HSI2C_TXFIFO_EN (1u << 1) 34#define HSI2C_TXFIFO_TRIGGER_LEVEL (0x20 << 16) 35#define HSI2C_RXFIFO_TRIGGER_LEVEL (0x20 << 4) 36 37/* I2C_TRAILING_CTL Register bits */ 38#define HSI2C_TRAILING_COUNT (0xff) 39 40/* I2C_INT_EN Register bits */ 41#define HSI2C_TX_UNDERRUN_EN (1u << 2) 42#define HSI2C_TX_OVERRUN_EN (1u << 3) 43#define HSI2C_RX_UNDERRUN_EN (1u << 4) 44#define HSI2C_RX_OVERRUN_EN (1u << 5) 45#define HSI2C_INT_TRAILING_EN (1u << 6) 46#define HSI2C_INT_I2C_EN (1u << 9) 47 48#define HSI2C_INT_ERROR_MASK (HSI2C_TX_UNDERRUN_EN |\ 49 HSI2C_TX_OVERRUN_EN |\ 50 HSI2C_RX_UNDERRUN_EN |\ 51 HSI2C_RX_OVERRUN_EN |\ 52 HSI2C_INT_TRAILING_EN) 53 54/* I2C_CONF Register bits */ 55#define HSI2C_AUTO_MODE (1u << 31) 56#define HSI2C_10BIT_ADDR_MODE (1u << 30) 57#define HSI2C_HS_MODE (1u << 29) 58 59/* I2C_AUTO_CONF Register bits */ 60#define HSI2C_READ_WRITE (1u << 16) 61#define HSI2C_STOP_AFTER_TRANS (1u << 17) 62#define HSI2C_MASTER_RUN (1u << 31) 63 64/* I2C_TIMEOUT Register bits */ 65#define HSI2C_TIMEOUT_EN (1u << 31) 66 67/* I2C_TRANS_STATUS register bits */ 68#define HSI2C_MASTER_BUSY (1u << 17) 69#define HSI2C_SLAVE_BUSY (1u << 16) 70#define HSI2C_TIMEOUT_AUTO (1u << 4) 71#define HSI2C_NO_DEV (1u << 3) 72#define HSI2C_NO_DEV_ACK (1u << 2) 73#define HSI2C_TRANS_ABORT (1u << 1) 74#define HSI2C_TRANS_SUCCESS (1u << 0) 75#define HSI2C_TRANS_ERROR_MASK (HSI2C_TIMEOUT_AUTO |\ 76 HSI2C_NO_DEV | HSI2C_NO_DEV_ACK |\ 77 HSI2C_TRANS_ABORT) 78#define HSI2C_TRANS_FINISHED_MASK (HSI2C_TRANS_ERROR_MASK | HSI2C_TRANS_SUCCESS) 79 80 81/* I2C_FIFO_STAT Register bits */ 82#define HSI2C_RX_FIFO_EMPTY (1u << 24) 83#define HSI2C_RX_FIFO_FULL (1u << 23) 84#define HSI2C_TX_FIFO_EMPTY (1u << 8) 85#define HSI2C_TX_FIFO_FULL (1u << 7) 86#define HSI2C_RX_FIFO_LEVEL(x) (((x) >> 16) & 0x7f) 87#define HSI2C_TX_FIFO_LEVEL(x) ((x) & 0x7f) 88 89#define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10) 90 91#define HSI2C_TIMEOUT_US 10000 /* 10 ms, finer granularity */ 92 93/* 94 * Wait for transfer completion. 95 * 96 * This function reads the interrupt status register waiting for the INT_I2C 97 * bit to be set, which indicates copletion of a transaction. 98 * 99 * @param i2c: pointer to the appropriate register bank 100 * 101 * @return: I2C_OK in case of successful completion, I2C_NOK_TIMEOUT in case 102 * the status bits do not get set in time, or an approrpiate error 103 * value in case of transfer errors. 104 */ 105static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c) 106{ 107 int i = HSI2C_TIMEOUT_US; 108 109 while (i-- > 0) { 110 u32 int_status = readl(&i2c->usi_int_stat); 111 112 if (int_status & HSI2C_INT_I2C_EN) { 113 u32 trans_status = readl(&i2c->usi_trans_status); 114 115 /* Deassert pending interrupt. */ 116 writel(int_status, &i2c->usi_int_stat); 117 118 if (trans_status & HSI2C_NO_DEV_ACK) { 119 debug("%s: no ACK from device\n", __func__); 120 return I2C_NACK; 121 } 122 if (trans_status & HSI2C_NO_DEV) { 123 debug("%s: no device\n", __func__); 124 return I2C_NOK; 125 } 126 if (trans_status & HSI2C_TRANS_ABORT) { 127 debug("%s: arbitration lost\n", __func__); 128 return I2C_NOK_LA; 129 } 130 if (trans_status & HSI2C_TIMEOUT_AUTO) { 131 debug("%s: device timed out\n", __func__); 132 return I2C_NOK_TOUT; 133 } 134 return I2C_OK; 135 } 136 udelay(1); 137 } 138 debug("%s: transaction timeout!\n", __func__); 139 return I2C_NOK_TOUT; 140} 141 142static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus) 143{ 144 struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; 145 ulong clkin; 146 unsigned int op_clk = i2c_bus->clock_frequency; 147 unsigned int i = 0, utemp0 = 0, utemp1 = 0; 148 unsigned int t_ftl_cycle; 149 150#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5) 151 clkin = get_i2c_clk(); 152#else 153 clkin = get_PCLK(); 154#endif 155 /* FPCLK / FI2C = 156 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE 157 * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) 158 * uTemp1 = (TSCLK_L + TSCLK_H + 2) 159 * uTemp2 = TSCLK_L + TSCLK_H 160 */ 161 t_ftl_cycle = (readl(&hsregs->usi_conf) >> 16) & 0x7; 162 utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle; 163 164 /* CLK_DIV max is 256 */ 165 for (i = 0; i < 256; i++) { 166 utemp1 = utemp0 / (i + 1); 167 if ((utemp1 < 512) && (utemp1 > 4)) { 168 i2c_bus->clk_cycle = utemp1 - 2; 169 i2c_bus->clk_div = i; 170 return 0; 171 } 172 } 173 return -EINVAL; 174} 175 176static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus) 177{ 178 struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; 179 unsigned int t_sr_release; 180 unsigned int n_clkdiv; 181 unsigned int t_start_su, t_start_hd; 182 unsigned int t_stop_su; 183 unsigned int t_data_su, t_data_hd; 184 unsigned int t_scl_l, t_scl_h; 185 u32 i2c_timing_s1; 186 u32 i2c_timing_s2; 187 u32 i2c_timing_s3; 188 u32 i2c_timing_sla; 189 190 n_clkdiv = i2c_bus->clk_div; 191 t_scl_l = i2c_bus->clk_cycle / 2; 192 t_scl_h = i2c_bus->clk_cycle / 2; 193 t_start_su = t_scl_l; 194 t_start_hd = t_scl_l; 195 t_stop_su = t_scl_l; 196 t_data_su = t_scl_l / 2; 197 t_data_hd = t_scl_l / 2; 198 t_sr_release = i2c_bus->clk_cycle; 199 200 i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8; 201 i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0; 202 i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0; 203 i2c_timing_sla = t_data_hd << 0; 204 205 writel(HSI2C_TRAILING_COUNT, &hsregs->usi_trailing_ctl); 206 207 /* Clear to enable Timeout */ 208 clrsetbits_le32(&hsregs->usi_timeout, HSI2C_TIMEOUT_EN, 0); 209 210 /* set AUTO mode */ 211 writel(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf); 212 213 /* Enable completion conditions' reporting. */ 214 writel(HSI2C_INT_I2C_EN, &hsregs->usi_int_en); 215 216 /* Enable FIFOs */ 217 writel(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl); 218 219 /* Currently operating in Fast speed mode. */ 220 writel(i2c_timing_s1, &hsregs->usi_timing_fs1); 221 writel(i2c_timing_s2, &hsregs->usi_timing_fs2); 222 writel(i2c_timing_s3, &hsregs->usi_timing_fs3); 223 writel(i2c_timing_sla, &hsregs->usi_timing_sla); 224} 225 226/* SW reset for the high speed bus */ 227static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus) 228{ 229 struct exynos5_hsi2c *i2c = i2c_bus->hsregs; 230 u32 i2c_ctl; 231 232 /* Set and clear the bit for reset */ 233 i2c_ctl = readl(&i2c->usi_ctl); 234 i2c_ctl |= HSI2C_SW_RST; 235 writel(i2c_ctl, &i2c->usi_ctl); 236 237 i2c_ctl = readl(&i2c->usi_ctl); 238 i2c_ctl &= ~HSI2C_SW_RST; 239 writel(i2c_ctl, &i2c->usi_ctl); 240 241 /* Initialize the configure registers */ 242 hsi2c_ch_init(i2c_bus); 243} 244 245/* 246 * Poll the appropriate bit of the fifo status register until the interface is 247 * ready to process the next byte or timeout expires. 248 * 249 * In addition to the FIFO status register this function also polls the 250 * interrupt status register to be able to detect unexpected transaction 251 * completion. 252 * 253 * When FIFO is ready to process the next byte, this function returns I2C_OK. 254 * If in course of polling the INT_I2C assertion is detected, the function 255 * returns I2C_NOK. If timeout happens before any of the above conditions is 256 * met - the function returns I2C_NOK_TOUT; 257 258 * @param i2c: pointer to the appropriate i2c register bank. 259 * @param rx_transfer: set to True if the receive transaction is in progress. 260 * @return: as described above. 261 */ 262static unsigned hsi2c_poll_fifo(struct exynos5_hsi2c *i2c, bool rx_transfer) 263{ 264 u32 fifo_bit = rx_transfer ? HSI2C_RX_FIFO_EMPTY : HSI2C_TX_FIFO_FULL; 265 int i = HSI2C_TIMEOUT_US; 266 267 while (readl(&i2c->usi_fifo_stat) & fifo_bit) { 268 if (readl(&i2c->usi_int_stat) & HSI2C_INT_I2C_EN) { 269 /* 270 * There is a chance that assertion of 271 * HSI2C_INT_I2C_EN and deassertion of 272 * HSI2C_RX_FIFO_EMPTY happen simultaneously. Let's 273 * give FIFO status priority and check it one more 274 * time before reporting interrupt. The interrupt will 275 * be reported next time this function is called. 276 */ 277 if (rx_transfer && 278 !(readl(&i2c->usi_fifo_stat) & fifo_bit)) 279 break; 280 return I2C_NOK; 281 } 282 if (!i--) { 283 debug("%s: FIFO polling timeout!\n", __func__); 284 return I2C_NOK_TOUT; 285 } 286 udelay(1); 287 } 288 return I2C_OK; 289} 290 291/* 292 * Preapre hsi2c transaction, either read or write. 293 * 294 * Set up transfer as described in section 27.5.1.2 'I2C Channel Auto Mode' of 295 * the 5420 UM. 296 * 297 * @param i2c: pointer to the appropriate i2c register bank. 298 * @param chip: slave address on the i2c bus (with read/write bit exlcuded) 299 * @param len: number of bytes expected to be sent or received 300 * @param rx_transfer: set to true for receive transactions 301 * @param: issue_stop: set to true if i2c stop condition should be generated 302 * after this transaction. 303 * @return: I2C_NOK_TOUT in case the bus remained busy for HSI2C_TIMEOUT_US, 304 * I2C_OK otherwise. 305 */ 306static int hsi2c_prepare_transaction(struct exynos5_hsi2c *i2c, 307 u8 chip, 308 u16 len, 309 bool rx_transfer, 310 bool issue_stop) 311{ 312 u32 conf; 313 314 conf = len | HSI2C_MASTER_RUN; 315 316 if (issue_stop) 317 conf |= HSI2C_STOP_AFTER_TRANS; 318 319 /* Clear to enable Timeout */ 320 writel(readl(&i2c->usi_timeout) & ~HSI2C_TIMEOUT_EN, &i2c->usi_timeout); 321 322 /* Set slave address */ 323 writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr); 324 325 if (rx_transfer) { 326 /* i2c master, read transaction */ 327 writel((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), 328 &i2c->usi_ctl); 329 330 /* read up to len bytes, stop after transaction is finished */ 331 writel(conf | HSI2C_READ_WRITE, &i2c->usi_auto_conf); 332 } else { 333 /* i2c master, write transaction */ 334 writel((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), 335 &i2c->usi_ctl); 336 337 /* write up to len bytes, stop after transaction is finished */ 338 writel(conf, &i2c->usi_auto_conf); 339 } 340 341 /* Reset all pending interrupt status bits we care about, if any */ 342 writel(HSI2C_INT_I2C_EN, &i2c->usi_int_stat); 343 344 return I2C_OK; 345} 346 347/* 348 * Wait while i2c bus is settling down (mostly stop gets completed). 349 */ 350static int hsi2c_wait_while_busy(struct exynos5_hsi2c *i2c) 351{ 352 int i = HSI2C_TIMEOUT_US; 353 354 while (readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY) { 355 if (!i--) { 356 debug("%s: bus busy\n", __func__); 357 return I2C_NOK_TOUT; 358 } 359 udelay(1); 360 } 361 return I2C_OK; 362} 363 364static int hsi2c_write(struct exynos5_hsi2c *i2c, 365 unsigned char chip, 366 unsigned char addr[], 367 unsigned char alen, 368 unsigned char data[], 369 unsigned short len, 370 bool issue_stop) 371{ 372 int i, rv = 0; 373 374 if (!(len + alen)) { 375 /* Writes of zero length not supported in auto mode. */ 376 debug("%s: zero length writes not supported\n", __func__); 377 return I2C_NOK; 378 } 379 380 rv = hsi2c_prepare_transaction 381 (i2c, chip, len + alen, false, issue_stop); 382 if (rv != I2C_OK) 383 return rv; 384 385 /* Move address, if any, and the data, if any, into the FIFO. */ 386 for (i = 0; i < alen; i++) { 387 rv = hsi2c_poll_fifo(i2c, false); 388 if (rv != I2C_OK) { 389 debug("%s: address write failed\n", __func__); 390 goto write_error; 391 } 392 writel(addr[i], &i2c->usi_txdata); 393 } 394 395 for (i = 0; i < len; i++) { 396 rv = hsi2c_poll_fifo(i2c, false); 397 if (rv != I2C_OK) { 398 debug("%s: data write failed\n", __func__); 399 goto write_error; 400 } 401 writel(data[i], &i2c->usi_txdata); 402 } 403 404 rv = hsi2c_wait_for_trx(i2c); 405 406 write_error: 407 if (issue_stop) { 408 int tmp_ret = hsi2c_wait_while_busy(i2c); 409 if (rv == I2C_OK) 410 rv = tmp_ret; 411 } 412 413 writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */ 414 return rv; 415} 416 417static int hsi2c_read(struct exynos5_hsi2c *i2c, 418 unsigned char chip, 419 unsigned char addr[], 420 unsigned char alen, 421 unsigned char data[], 422 unsigned short len) 423{ 424 int i, rv, tmp_ret; 425 bool drop_data = false; 426 427 if (!len) { 428 /* Reads of zero length not supported in auto mode. */ 429 debug("%s: zero length read adjusted\n", __func__); 430 drop_data = true; 431 len = 1; 432 } 433 434 if (alen) { 435 /* Internal register adress needs to be written first. */ 436 rv = hsi2c_write(i2c, chip, addr, alen, NULL, 0, false); 437 if (rv != I2C_OK) 438 return rv; 439 } 440 441 rv = hsi2c_prepare_transaction(i2c, chip, len, true, true); 442 443 if (rv != I2C_OK) 444 return rv; 445 446 for (i = 0; i < len; i++) { 447 rv = hsi2c_poll_fifo(i2c, true); 448 if (rv != I2C_OK) 449 goto read_err; 450 if (drop_data) 451 continue; 452 data[i] = readl(&i2c->usi_rxdata); 453 } 454 455 rv = hsi2c_wait_for_trx(i2c); 456 457 read_err: 458 tmp_ret = hsi2c_wait_while_busy(i2c); 459 if (rv == I2C_OK) 460 rv = tmp_ret; 461 462 writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */ 463 return rv; 464} 465 466static int exynos_hs_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, 467 int nmsgs) 468{ 469 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); 470 struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; 471 int ret; 472 473 for (; nmsgs > 0; nmsgs--, msg++) { 474 if (msg->flags & I2C_M_RD) { 475 ret = hsi2c_read(hsregs, msg->addr, 0, 0, msg->buf, 476 msg->len); 477 } else { 478 ret = hsi2c_write(hsregs, msg->addr, 0, 0, msg->buf, 479 msg->len, true); 480 } 481 if (ret) { 482 exynos5_i2c_reset(i2c_bus); 483 return -EREMOTEIO; 484 } 485 } 486 487 return 0; 488} 489 490static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) 491{ 492 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); 493 494 i2c_bus->clock_frequency = speed; 495 496 if (hsi2c_get_clk_details(i2c_bus)) 497 return -EFAULT; 498 hsi2c_ch_init(i2c_bus); 499 500 return 0; 501} 502 503static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags) 504{ 505 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); 506 uchar buf[1]; 507 int ret; 508 509 buf[0] = 0; 510 511 /* 512 * What is needed is to send the chip address and verify that the 513 * address was <ACK>ed (i.e. there was a chip at that address which 514 * drove the data line low). 515 */ 516 ret = hsi2c_read(i2c_bus->hsregs, chip, 0, 0, buf, 1); 517 518 return ret != I2C_OK; 519} 520 521static int s3c_i2c_of_to_plat(struct udevice *dev) 522{ 523 const void *blob = gd->fdt_blob; 524 struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); 525 int node; 526 527 node = dev_of_offset(dev); 528 529 i2c_bus->hsregs = dev_read_addr_ptr(dev); 530 531 i2c_bus->id = pinmux_decode_periph_id(blob, node); 532 533 i2c_bus->clock_frequency = 534 dev_read_u32_default(dev, "clock-frequency", 535 I2C_SPEED_STANDARD_RATE); 536 i2c_bus->node = node; 537 i2c_bus->bus_num = dev_seq(dev); 538 539 exynos_pinmux_config(i2c_bus->id, PINMUX_FLAG_HS_MODE); 540 541 i2c_bus->active = true; 542 543 return 0; 544} 545 546static const struct dm_i2c_ops exynos_hs_i2c_ops = { 547 .xfer = exynos_hs_i2c_xfer, 548 .probe_chip = s3c24x0_i2c_probe, 549 .set_bus_speed = s3c24x0_i2c_set_bus_speed, 550}; 551 552static const struct udevice_id exynos_hs_i2c_ids[] = { 553 { .compatible = "samsung,exynos5-hsi2c" }, 554 { } 555}; 556 557U_BOOT_DRIVER(hs_i2c) = { 558 .name = "i2c_s3c_hs", 559 .id = UCLASS_I2C, 560 .of_match = exynos_hs_i2c_ids, 561 .of_to_plat = s3c_i2c_of_to_plat, 562 .priv_auto = sizeof(struct s3c24x0_i2c_bus), 563 .ops = &exynos_hs_i2c_ops, 564}; 565