1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2009
4 * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
5 */
6
7#ifndef __DW_I2C_H_
8#define __DW_I2C_H_
9
10#include <clk.h>
11#include <i2c.h>
12#include <reset.h>
13#include <linux/bitops.h>
14
15struct i2c_regs {
16	u32 ic_con;		/* 0x00 */
17	u32 ic_tar;		/* 0x04 */
18	u32 ic_sar;		/* 0x08 */
19	u32 ic_hs_maddr;	/* 0x0c */
20	u32 ic_cmd_data;	/* 0x10 */
21	u32 ic_ss_scl_hcnt;	/* 0x14 */
22	u32 ic_ss_scl_lcnt;	/* 0x18 */
23	u32 ic_fs_scl_hcnt;	/* 0x1c */
24	u32 ic_fs_scl_lcnt;	/* 0x20 */
25	u32 ic_hs_scl_hcnt;	/* 0x24 */
26	u32 ic_hs_scl_lcnt;	/* 0x28 */
27	u32 ic_intr_stat;	/* 0x2c */
28	u32 ic_intr_mask;	/* 0x30 */
29	u32 ic_raw_intr_stat;	/* 0x34 */
30	u32 ic_rx_tl;		/* 0x38 */
31	u32 ic_tx_tl;		/* 0x3c */
32	u32 ic_clr_intr;	/* 0x40 */
33	u32 ic_clr_rx_under;	/* 0x44 */
34	u32 ic_clr_rx_over;	/* 0x48 */
35	u32 ic_clr_tx_over;	/* 0x4c */
36	u32 ic_clr_rd_req;	/* 0x50 */
37	u32 ic_clr_tx_abrt;	/* 0x54 */
38	u32 ic_clr_rx_done;	/* 0x58 */
39	u32 ic_clr_activity;	/* 0x5c */
40	u32 ic_clr_stop_det;	/* 0x60 */
41	u32 ic_clr_start_det;	/* 0x64 */
42	u32 ic_clr_gen_call;	/* 0x68 */
43	u32 ic_enable;		/* 0x6c */
44	u32 ic_status;		/* 0x70 */
45	u32 ic_txflr;		/* 0x74 */
46	u32 ic_rxflr;		/* 0x78 */
47	u32 ic_sda_hold;	/* 0x7c */
48	u32 ic_tx_abrt_source;	/* 0x80 */
49	u32 slv_data_nak_only;
50	u32 dma_cr;
51	u32 dma_tdlr;
52	u32 dma_rdlr;
53	u32 sda_setup;
54	u32 ack_general_call;
55	u32 ic_enable_status;	/* 0x9c */
56	u32 fs_spklen;
57	u32 hs_spklen;
58	u32 clr_restart_det;
59	u8 reserved[0xf4 - 0xac];
60	u32 comp_param1;	/* 0xf4 */
61	u32 comp_version;
62	u32 comp_type;
63};
64
65#define IC_CLK			166666666
66#define NANO_TO_KILO		1000000
67
68/* High and low times in different speed modes (in ns) */
69#define MIN_SS_SCL_HIGHTIME	4000
70#define MIN_SS_SCL_LOWTIME	4700
71#define MIN_FS_SCL_HIGHTIME	600
72#define MIN_FS_SCL_LOWTIME	1300
73#define MIN_FP_SCL_HIGHTIME	260
74#define MIN_FP_SCL_LOWTIME	500
75#define MIN_HS_SCL_HIGHTIME	60
76#define MIN_HS_SCL_LOWTIME	160
77
78/* Worst case timeout for 1 byte is kept as 2ms */
79#define I2C_BYTE_TO		(CONFIG_SYS_HZ/500)
80#define I2C_STOPDET_TO		(CONFIG_SYS_HZ/500)
81#define I2C_BYTE_TO_BB		(I2C_BYTE_TO * 16)
82
83/* i2c control register definitions */
84#define IC_CON_SD		0x0040
85#define IC_CON_RE		0x0020
86#define IC_CON_10BITADDRMASTER	0x0010
87#define IC_CON_10BITADDR_SLAVE	0x0008
88#define IC_CON_SPD_MSK		0x0006
89#define IC_CON_SPD_SS		0x0002
90#define IC_CON_SPD_FS		0x0004
91#define IC_CON_SPD_HS		0x0006
92#define IC_CON_MM		0x0001
93
94/* i2c target address register definitions */
95#define TAR_ADDR		0x0050
96
97/* i2c slave address register definitions */
98#define IC_SLAVE_ADDR		0x0002
99
100/* i2c data buffer and command register definitions */
101#define IC_CMD			0x0100
102#define IC_STOP			0x0200
103
104/* i2c interrupt status register definitions */
105#define IC_GEN_CALL		0x0800
106#define IC_START_DET		0x0400
107#define IC_STOP_DET		0x0200
108#define IC_ACTIVITY		0x0100
109#define IC_RX_DONE		0x0080
110#define IC_TX_ABRT		0x0040
111#define IC_RD_REQ		0x0020
112#define IC_TX_EMPTY		0x0010
113#define IC_TX_OVER		0x0008
114#define IC_RX_FULL		0x0004
115#define IC_RX_OVER		0x0002
116#define IC_RX_UNDER		0x0001
117
118/* fifo threshold register definitions */
119#define IC_TL0			0x00
120#define IC_TL1			0x01
121#define IC_TL2			0x02
122#define IC_TL3			0x03
123#define IC_TL4			0x04
124#define IC_TL5			0x05
125#define IC_TL6			0x06
126#define IC_TL7			0x07
127#define IC_RX_TL		IC_TL0
128#define IC_TX_TL		IC_TL0
129
130/* i2c enable register definitions */
131#define IC_ENABLE_0B		0x0001
132
133/* i2c status register  definitions */
134#define IC_STATUS_SA		0x0040
135#define IC_STATUS_MA		0x0020
136#define IC_STATUS_RFF		0x0010
137#define IC_STATUS_RFNE		0x0008
138#define IC_STATUS_TFE		0x0004
139#define IC_STATUS_TFNF		0x0002
140#define IC_STATUS_ACT		0x0001
141
142#define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH      (BIT(2) | BIT(3))
143#define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK      (BIT(2) | BIT(3))
144
145/**
146 * struct dw_scl_sda_cfg - I2C timing configuration
147 *
148 * @ss_hcnt: Standard speed high time in ns
149 * @fs_hcnt: Fast speed high time in ns
150 * @hs_hcnt: High speed high time in ns
151 * @ss_lcnt: Standard speed low time in ns
152 * @fs_lcnt: Fast speed low time in ns
153 * @hs_lcnt: High speed low time in ns
154 * @sda_hold: SDA hold time
155 */
156struct dw_scl_sda_cfg {
157	u32 ss_hcnt;
158	u32 fs_hcnt;
159	u32 hs_hcnt;
160	u32 ss_lcnt;
161	u32 fs_lcnt;
162	u32 hs_lcnt;
163	u32 sda_hold;
164};
165
166/**
167 * struct dw_i2c_speed_config - timings to use for a particular speed
168 *
169 * This holds calculated values to be written to the I2C controller. Each value
170 * is represented as a number of IC clock cycles.
171 *
172 * @scl_lcnt: Low count value for SCL
173 * @scl_hcnt: High count value for SCL
174 * @sda_hold: Data hold count
175 * @speed_mode: Speed mode being used
176 */
177struct dw_i2c_speed_config {
178	/* SCL high and low period count */
179	u16 scl_lcnt;
180	u16 scl_hcnt;
181	u32 sda_hold;
182	enum i2c_speed_mode speed_mode;
183};
184
185/**
186 * struct dw_i2c - private information for the bus
187 *
188 * @regs: Registers pointer
189 * @scl_sda_cfg: Deprecated information for x86 (should move to device tree)
190 * @resets: Resets for the I2C controller
191 * @scl_rise_time_ns: Configured SCL rise time in nanoseconds
192 * @scl_fall_time_ns: Configured SCL fall time in nanoseconds
193 * @sda_hold_time_ns: Configured SDA hold time in nanoseconds
194 * @has_spk_cnt: true if the spike-count register is present
195 * @clk: Clock input to the I2C controller
196 */
197struct dw_i2c {
198	struct i2c_regs *regs;
199	struct dw_scl_sda_cfg *scl_sda_cfg;
200	struct reset_ctl_bulk resets;
201	u32 scl_rise_time_ns;
202	u32 scl_fall_time_ns;
203	u32 sda_hold_time_ns;
204	bool has_spk_cnt;
205#if CONFIG_IS_ENABLED(CLK)
206	struct clk clk;
207#endif
208	struct dw_i2c_speed_config config;
209};
210
211extern const struct dm_i2c_ops designware_i2c_ops;
212
213int designware_i2c_probe(struct udevice *bus);
214int designware_i2c_remove(struct udevice *dev);
215int designware_i2c_of_to_plat(struct udevice *bus);
216
217/**
218 * dw_i2c_gen_speed_config() - Calculate config info from requested speed
219 *
220 * Calculate the speed config from the given @speed_hz and return it so that
221 * it can be incorporated in ACPI tables
222 *
223 * @dev: I2C bus to check
224 * @speed_hz: Requested speed in Hz
225 * @config: Returns config to use for that speed
226 * Return: 0 if OK, -ve on error
227 */
228int dw_i2c_gen_speed_config(const struct udevice *dev, int speed_hz,
229			    struct dw_i2c_speed_config *config);
230
231#endif /* __DW_I2C_H_ */
232