1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) Marvell International Ltd. and its affiliates
4 */
5
6#ifndef __DDR3_AXP_CONFIG_H
7#define __DDR3_AXP_CONFIG_H
8
9/*
10 * DDR3_LOG_LEVEL Information
11 *
12 * Level 0: Provides an error code in a case of failure, RL, WL errors
13 *          and other algorithm failure
14 * Level 1: Provides the D-Unit setup (SPD/Static configuration)
15 * Level 2: Provides the windows margin as a results of DQS centeralization
16 * Level 3: Provides the windows margin of each DQ as a results of DQS
17 *          centeralization
18 */
19#define	DDR3_LOG_LEVEL	CONFIG_DDR_LOG_LEVEL
20
21#define DDR3_PBS        1
22
23/* This flag allows the execution of SW WL/RL upon HW failure */
24#define DDR3_RUN_SW_WHEN_HW_FAIL    1
25
26/*
27 * General Configurations
28 *
29 * The following parameters are required for proper setup:
30 *
31 * DDR_TARGET_FABRIC   - Set desired fabric configuration
32 *                       (for sample@Reset fabfreq parameter)
33 * DRAM_ECC            - Set ECC support 1/0
34 * BUS_WIDTH           - 64/32 bit
35 * CONFIG_SPD_EEPROM   - Enables auto detection of DIMMs and their timing values
36 * DQS_CLK_ALIGNED     - Set this if CLK and DQS signals are aligned on board
37 * MIXED_DIMM_STATIC   - Mixed DIMM + On board devices support (ODT registers
38 *                       values are taken statically)
39 * DDR3_TRAINING_DEBUG - Debug prints of internal code
40 */
41#define DDR_TARGET_FABRIC			5
42/* Only enable ECC if the board selects it */
43#ifdef CONFIG_BOARD_ECC_SUPPORT
44#define DRAM_ECC				1
45#else
46#define DRAM_ECC				0
47#endif
48
49#ifdef CONFIG_DDR_32BIT
50#define BUS_WIDTH                               32
51#else
52#define BUS_WIDTH				64
53#endif
54
55#undef DQS_CLK_ALIGNED
56#undef MIXED_DIMM_STATIC
57#define DDR3_TRAINING_DEBUG			0
58#define REG_DIMM_SKIP_WL			0
59
60/* Marvell boards specific configurations */
61#if defined(DB_78X60_PCAC)
62#define STATIC_TRAINING
63#endif
64
65#if defined(DB_78X60_AMC)
66#undef  DRAM_ECC
67#define DRAM_ECC				1
68#endif
69
70#ifdef CONFIG_SPD_EEPROM
71/*
72 * DIMM support parameters:
73 * DRAM_2T - Set Desired 2T Mode - 0 - 1T, 0x1 - 2T, 0x2 - 3T
74 * DIMM_CS_BITMAP - bitmap representing the optional CS in DIMMs
75 * (0xF=CS0+CS1+CS2+CS3, 0xC=CS2+CS3...)
76 */
77#define DRAM_2T					0x0
78#define DIMM_CS_BITMAP				0xF
79#define DUNIT_SPD
80#endif
81
82#ifdef DRAM_ECC
83/*
84 * ECC support parameters:
85 *
86 * U_BOOT_START_ADDR, U_BOOT_SCRUB_SIZE - relevant when using ECC and need
87 * to configure the scrubbing area
88 */
89#define TRAINING_SIZE				0x20000
90#define U_BOOT_START_ADDR			0
91#define U_BOOT_SCRUB_SIZE			0x1000000 /* TRAINING_SIZE */
92#endif
93
94/*
95 * Registered DIMM Support - In case registered DIMM is attached,
96 * please supply the following values:
97 * (see JEDEC - JESD82-29A "Definition of the SSTE32882 Registering Clock
98 * Driver with Parity and Quad Chip
99 * Selects for DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V Applications")
100 * RC0: Global Features Control Word
101 * RC1: Clock Driver Enable Control Word
102 * RC2: Timing Control Word
103 * RC3-RC5 - taken from SPD
104 * RC8: Additional IBT Setting Control Word
105 * RC9: Power Saving Settings Control Word
106 * RC10: Encoding for RDIMM Operating Speed
107 * RC11: Operating Voltage VDD and VREFCA Control Word
108 */
109#define RDIMM_RC0				0
110#define RDIMM_RC1				0
111#define RDIMM_RC2				0
112#define RDIMM_RC8				0
113#define RDIMM_RC9				0
114#define RDIMM_RC10				0x2
115#define RDIMM_RC11				0x0
116
117#if defined(MIXED_DIMM_STATIC) || !defined(CONFIG_SPD_EEPROM)
118#define DUNIT_STATIC
119#endif
120
121#if defined(MIXED_DIMM_STATIC) || defined(CONFIG_SPD_EEPROM)
122/*
123 * This flag allows the user to change the dram refresh cycle in ps,
124 * only in case of SPD or MIX DIMM topology
125 */
126#define TREFI_USER_EN
127
128#ifdef TREFI_USER_EN
129#define TREFI_USER				3900000
130#endif
131#endif
132
133#ifdef CONFIG_SPD_EEPROM
134/*
135 * AUTO_DETECTION_SUPPORT - relevant ONLY for Marvell DB boards.
136 * Enables I2C auto detection different options
137 */
138#if defined(CONFIG_DB_88F78X60) || defined(CONFIG_DB_88F78X60_REV2) || \
139    defined(CONFIG_TARGET_DB_MV784MP_GP)
140#define AUTO_DETECTION_SUPPORT
141#endif
142#endif
143
144#endif /* __DDR3_AXP_CONFIG_H */
145