1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2008-2014 Freescale Semiconductor, Inc. 4 * Copyright 2021 NXP 5 * 6 */ 7 8#ifndef __JR_H 9#define __JR_H 10 11#include <linux/compiler.h> 12#include "fsl_sec.h" 13#include "type.h" 14#include <misc.h> 15 16#define JR_SIZE 4 17/* Timeout currently defined as 10 sec */ 18#define CFG_USEC_DEQ_TIMEOUT 10000000U 19 20#define DEFAULT_JR_ID 0 21#define DEFAULT_JR_LIODN 0 22#define DEFAULT_IRQ 0 /* Interrupts not to be configured */ 23 24#define MCFGR_SWRST ((uint32_t)(1)<<31) /* Software Reset */ 25#define MCFGR_DMA_RST ((uint32_t)(1)<<28) /* DMA Reset */ 26#define MCFGR_PS_SHIFT 16 27#define MCFGR_AWCACHE_SHIFT 8 28#define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT) 29#define MCFGR_ARCACHE_SHIFT 12 30#define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT) 31 32#define JR_INTMASK 0x00000001 33#define JRCR_RESET 0x01 34#define JRINT_ERR_HALT_INPROGRESS 0x4 35#define JRINT_ERR_HALT_MASK 0xc 36#define JRNSLIODN_SHIFT 16 37#define JRNSLIODN_MASK 0x0fff0000 38#define JRSLIODN_SHIFT 0 39#define JRSLIODN_MASK 0x00000fff 40#define JROWN_NS 0x00000008 41#define JRMID_NS 0x00000001 42 43#define JRDID_MS_PRIM_DID BIT(0) 44#define JRDID_MS_PRIM_TZ BIT(4) 45#define JRDID_MS_TZ_OWN BIT(15) 46 47#define JQ_DEQ_ERR (-1) 48#define JQ_DEQ_TO_ERR (-2) 49#define JQ_ENQ_ERR (-3) 50 51#define RNG4_MAX_HANDLES 2 52 53enum { 54 /* Run caam jobring descriptor(in buf) */ 55 CAAM_JR_RUN_DESC, 56}; 57 58struct op_ring { 59 caam_dma_addr_t desc; 60 uint32_t status; 61} __packed; 62 63struct jr_info { 64 void (*callback)(uint32_t status, void *arg); 65 caam_dma_addr_t desc_phys_addr; 66 uint32_t desc_len; 67 uint32_t op_done; 68 void *arg; 69}; 70 71struct jobring { 72 int jq_id; 73 int irq; 74 int liodn; 75 /* Head is the index where software would enq the descriptor in 76 * the i/p ring 77 */ 78 int head; 79 /* Tail index would be used by s/w ehile enqueuing to determine if 80 * there is any space left in the s/w maintained i/p rings 81 */ 82 /* Also in case of deq tail will be incremented only in case of 83 * in-order job completion 84 */ 85 int tail; 86 /* Read index of the output ring. It may not match with tail in case 87 * of out of order completetion 88 */ 89 int read_idx; 90 /* Write index to input ring. Would be always equal to head */ 91 int write_idx; 92 /* Size of the rings. */ 93 int size; 94 /* Op ring size aligned to cache line size */ 95 int op_size; 96 /* The ip and output rings have to be accessed by SEC. So the 97 * pointers will ahve to point to the housekeeping region provided 98 * by SEC 99 */ 100 /*Circular Ring of i/p descriptors */ 101 caam_dma_addr_t *input_ring; 102 /* Circular Ring of o/p descriptors */ 103 /* Circula Ring containing info regarding descriptors in i/p 104 * and o/p ring 105 */ 106 /* This ring can be on the stack */ 107 struct jr_info info[JR_SIZE]; 108 struct op_ring *output_ring; 109 /* Offset in CCSR to the SEC engine to which this JR belongs */ 110 uint32_t sec_offset; 111 112}; 113 114struct result { 115 int done; 116 uint32_t status; 117}; 118 119/* 120 * struct caam_regs - CAAM initialization register interface 121 * 122 * Interface to caam memory map, jobring register, jobring storage. 123 */ 124struct caam_regs { 125 ccsr_sec_t *sec; /*caam initialization registers*/ 126 struct jr_regs *regs; /*jobring configuration registers*/ 127 u8 jrid; /*id to identify a jobring*/ 128 /*Private sub-storage for a single JobR*/ 129 struct jobring jr[CONFIG_SYS_FSL_MAX_NUM_OF_SEC]; 130}; 131 132void caam_jr_strstatus(u32 status); 133int run_descriptor_jr(uint32_t *desc); 134 135#endif 136