1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <clk-uclass.h>
8#include <dm.h>
9#include <errno.h>
10#include <clk/sunxi.h>
11#include <dt-bindings/clock/sun8i-r40-ccu.h>
12#include <dt-bindings/reset/sun8i-r40-ccu.h>
13#include <linux/bitops.h>
14
15static struct ccu_clk_gate r40_gates[] = {
16	[CLK_BUS_MIPI_DSI]	= GATE(0x060, BIT(1)),
17	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
18	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
19	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
20	[CLK_BUS_MMC3]		= GATE(0x060, BIT(11)),
21	[CLK_BUS_NAND]		= GATE(0x060, BIT(13)),
22	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
23	[CLK_BUS_SPI1]		= GATE(0x060, BIT(21)),
24	[CLK_BUS_SPI2]		= GATE(0x060, BIT(22)),
25	[CLK_BUS_SPI3]		= GATE(0x060, BIT(23)),
26	[CLK_BUS_OTG]		= GATE(0x060, BIT(25)),
27	[CLK_BUS_EHCI0]		= GATE(0x060, BIT(26)),
28	[CLK_BUS_EHCI1]		= GATE(0x060, BIT(27)),
29	[CLK_BUS_EHCI2]		= GATE(0x060, BIT(28)),
30	[CLK_BUS_OHCI0]		= GATE(0x060, BIT(29)),
31	[CLK_BUS_OHCI1]		= GATE(0x060, BIT(30)),
32	[CLK_BUS_OHCI2]		= GATE(0x060, BIT(31)),
33
34	[CLK_BUS_HDMI0]		= GATE(0x064, BIT(10)),
35	[CLK_BUS_HDMI1]		= GATE(0x064, BIT(11)),
36	[CLK_BUS_DE]		= GATE(0x064, BIT(12)),
37	[CLK_BUS_GMAC]		= GATE(0x064, BIT(17)),
38	[CLK_BUS_TCON_LCD0]	= GATE(0x064, BIT(26)),
39	[CLK_BUS_TCON_LCD1]	= GATE(0x064, BIT(27)),
40	[CLK_BUS_TCON_TV0]	= GATE(0x064, BIT(28)),
41	[CLK_BUS_TCON_TV1]	= GATE(0x064, BIT(29)),
42	[CLK_BUS_TCON_TOP]	= GATE(0x064, BIT(30)),
43
44	[CLK_BUS_PIO]		= GATE(0x068, BIT(5)),
45
46	[CLK_BUS_I2C0]		= GATE(0x06c, BIT(0)),
47	[CLK_BUS_I2C1]		= GATE(0x06c, BIT(1)),
48	[CLK_BUS_I2C2]		= GATE(0x06c, BIT(2)),
49	[CLK_BUS_I2C3]		= GATE(0x06c, BIT(3)),
50	[CLK_BUS_I2C4]		= GATE(0x06c, BIT(15)),
51	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
52	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
53	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
54	[CLK_BUS_UART3]		= GATE(0x06c, BIT(19)),
55	[CLK_BUS_UART4]		= GATE(0x06c, BIT(20)),
56	[CLK_BUS_UART5]		= GATE(0x06c, BIT(21)),
57	[CLK_BUS_UART6]		= GATE(0x06c, BIT(22)),
58	[CLK_BUS_UART7]		= GATE(0x06c, BIT(23)),
59
60	[CLK_NAND]		= GATE(0x080, BIT(31)),
61	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
62	[CLK_SPI1]		= GATE(0x0a4, BIT(31)),
63	[CLK_SPI2]		= GATE(0x0a8, BIT(31)),
64	[CLK_SPI3]		= GATE(0x0ac, BIT(31)),
65
66	[CLK_USB_PHY0]		= GATE(0x0cc, BIT(8)),
67	[CLK_USB_PHY1]		= GATE(0x0cc, BIT(9)),
68	[CLK_USB_PHY2]		= GATE(0x0cc, BIT(10)),
69	[CLK_USB_OHCI0]		= GATE(0x0cc, BIT(16)),
70	[CLK_USB_OHCI1]		= GATE(0x0cc, BIT(17)),
71	[CLK_USB_OHCI2]		= GATE(0x0cc, BIT(18)),
72
73	[CLK_DE]		= GATE(0x104, BIT(31)),
74	[CLK_TCON_LCD0]		= GATE(0x110, BIT(31)),
75	[CLK_TCON_LCD1]		= GATE(0x114, BIT(31)),
76	[CLK_TCON_TV0]		= GATE(0x118, BIT(31)),
77	[CLK_TCON_TV1]		= GATE(0x11c, BIT(31)),
78
79	[CLK_HDMI]		= GATE(0x150, BIT(31)),
80	[CLK_HDMI_SLOW]		= GATE(0x154, BIT(31)),
81
82	[CLK_DSI_DPHY]		= GATE(0x168, BIT(15)),
83};
84
85static struct ccu_reset r40_resets[] = {
86	[RST_USB_PHY0]		= RESET(0x0cc, BIT(0)),
87	[RST_USB_PHY1]		= RESET(0x0cc, BIT(1)),
88	[RST_USB_PHY2]		= RESET(0x0cc, BIT(2)),
89
90	[RST_BUS_MIPI_DSI]	= RESET(0x2c0, BIT(1)),
91	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
92	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
93	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
94	[RST_BUS_MMC3]		= RESET(0x2c0, BIT(11)),
95	[RST_BUS_NAND]		= RESET(0x2c0, BIT(13)),
96	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
97	[RST_BUS_SPI1]		= RESET(0x2c0, BIT(21)),
98	[RST_BUS_SPI2]		= RESET(0x2c0, BIT(22)),
99	[RST_BUS_SPI3]		= RESET(0x2c0, BIT(23)),
100	[RST_BUS_OTG]		= RESET(0x2c0, BIT(25)),
101	[RST_BUS_EHCI0]		= RESET(0x2c0, BIT(26)),
102	[RST_BUS_EHCI1]		= RESET(0x2c0, BIT(27)),
103	[RST_BUS_EHCI2]		= RESET(0x2c0, BIT(28)),
104	[RST_BUS_OHCI0]		= RESET(0x2c0, BIT(29)),
105	[RST_BUS_OHCI1]		= RESET(0x2c0, BIT(30)),
106	[RST_BUS_OHCI2]		= RESET(0x2c0, BIT(31)),
107
108	[RST_BUS_HDMI0]		= RESET(0x2c4, BIT(10)),
109	[RST_BUS_HDMI1]		= RESET(0x2c4, BIT(11)),
110	[RST_BUS_DE]		= RESET(0x2c4, BIT(12)),
111	[RST_BUS_GMAC]		= RESET(0x2c4, BIT(17)),
112	[RST_BUS_TCON_LCD0]	= RESET(0x2c4, BIT(26)),
113	[RST_BUS_TCON_LCD1]	= RESET(0x2c4, BIT(27)),
114	[RST_BUS_TCON_TV0]	= RESET(0x2c4, BIT(28)),
115	[RST_BUS_TCON_TV1]	= RESET(0x2c4, BIT(29)),
116	[RST_BUS_TCON_TOP]	= RESET(0x2c4, BIT(30)),
117
118	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
119	[RST_BUS_I2C1]		= RESET(0x2d8, BIT(1)),
120	[RST_BUS_I2C2]		= RESET(0x2d8, BIT(2)),
121	[RST_BUS_I2C3]		= RESET(0x2d8, BIT(3)),
122	[RST_BUS_I2C4]		= RESET(0x2d8, BIT(15)),
123	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
124	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
125	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
126	[RST_BUS_UART3]		= RESET(0x2d8, BIT(19)),
127	[RST_BUS_UART4]		= RESET(0x2d8, BIT(20)),
128	[RST_BUS_UART5]		= RESET(0x2d8, BIT(21)),
129	[RST_BUS_UART6]		= RESET(0x2d8, BIT(22)),
130	[RST_BUS_UART7]		= RESET(0x2d8, BIT(23)),
131};
132
133const struct ccu_desc r40_ccu_desc = {
134	.gates = r40_gates,
135	.resets = r40_resets,
136	.num_gates = ARRAY_SIZE(r40_gates),
137	.num_resets = ARRAY_SIZE(r40_resets),
138};
139