1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * R-Car Gen2 Clock Pulse Generator 4 * 5 * Copyright (C) 2016 Cogent Embedded Inc. 6 */ 7 8#ifndef __CLK_RENESAS_RCAR_GEN2_CPG_H__ 9#define __CLK_RENESAS_RCAR_GEN2_CPG_H__ 10 11enum rcar_gen2_clk_types { 12 CLK_TYPE_GEN2_MAIN = CLK_TYPE_CUSTOM, 13 CLK_TYPE_GEN2_PLL0, 14 CLK_TYPE_GEN2_PLL1, 15 CLK_TYPE_GEN2_PLL3, 16 CLK_TYPE_GEN2_Z, 17 CLK_TYPE_GEN2_LB, 18 CLK_TYPE_GEN2_ADSP, 19 CLK_TYPE_GEN2_SDH, 20 CLK_TYPE_GEN2_SD0, 21 CLK_TYPE_GEN2_SD1, 22 CLK_TYPE_GEN2_QSPI, 23 CLK_TYPE_GEN2_RCAN, 24}; 25 26struct rcar_gen2_cpg_pll_config { 27 unsigned int extal_div; 28 unsigned int pll1_mult; 29 unsigned int pll3_mult; 30 unsigned int pll0_mult; /* leave as zero if PLL0CR exists */ 31}; 32 33#define CPG_RST_MODEMR 0x060 34 35struct gen2_clk_priv { 36 void __iomem *base; 37 struct cpg_mssr_info *info; 38 struct clk clk_extal; 39 struct clk clk_extal_usb; 40 const struct rcar_gen2_cpg_pll_config *cpg_pll_config; 41}; 42 43int gen2_clk_probe(struct udevice *dev); 44int gen2_clk_remove(struct udevice *dev); 45 46extern const struct clk_ops gen2_clk_ops; 47 48#endif 49