1// SPDX-License-Identifier: GPL-2.0 2/* 3 * r8a774b1 Clock Pulse Generator / Module Standby and Software Reset 4 * 5 * Copyright (C) 2019 Renesas Electronics Corp. 6 * 7 * Based on r8a7796-cpg-mssr.c 8 * 9 * Copyright (C) 2016 Glider bvba 10 */ 11 12#include <clk-uclass.h> 13#include <dm.h> 14 15#include <dt-bindings/clock/r8a774b1-cpg-mssr.h> 16 17#include "renesas-cpg-mssr.h" 18#include "rcar-gen3-cpg.h" 19 20enum clk_ids { 21 /* Core Clock Outputs exported to DT */ 22 LAST_DT_CORE_CLK = R8A774B1_CLK_CANFD, 23 24 /* External Input Clocks */ 25 CLK_EXTAL, 26 CLK_EXTALR, 27 28 /* Internal Core Clocks */ 29 CLK_MAIN, 30 CLK_PLL0, 31 CLK_PLL1, 32 CLK_PLL3, 33 CLK_PLL4, 34 CLK_PLL1_DIV2, 35 CLK_PLL1_DIV4, 36 CLK_S0, 37 CLK_S1, 38 CLK_S2, 39 CLK_S3, 40 CLK_SDSRC, 41 CLK_RPCSRC, 42 CLK_RINT, 43 44 /* Module Clocks */ 45 MOD_CLK_BASE 46}; 47 48static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = { 49 /* External Clock Inputs */ 50 DEF_INPUT("extal", CLK_EXTAL), 51 DEF_INPUT("extalr", CLK_EXTALR), 52 53 /* Internal Core Clocks */ 54 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 55 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN), 56 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN), 57 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN), 58 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN), 59 60 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1), 61 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1), 62 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1), 63 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1), 64 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), 65 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), 66 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), 67 68 DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), 69 70 DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), 71 72 /* Core Clock Outputs */ 73 DEF_GEN3_Z("z", R8A774B1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), 74 DEF_GEN3_Z("zg", R8A774B1_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24), 75 DEF_FIXED("ztr", R8A774B1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), 76 DEF_FIXED("ztrd2", R8A774B1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), 77 DEF_FIXED("zt", R8A774B1_CLK_ZT, CLK_PLL1_DIV2, 4, 1), 78 DEF_FIXED("zx", R8A774B1_CLK_ZX, CLK_PLL1_DIV2, 2, 1), 79 DEF_FIXED("s0d1", R8A774B1_CLK_S0D1, CLK_S0, 1, 1), 80 DEF_FIXED("s0d2", R8A774B1_CLK_S0D2, CLK_S0, 2, 1), 81 DEF_FIXED("s0d3", R8A774B1_CLK_S0D3, CLK_S0, 3, 1), 82 DEF_FIXED("s0d4", R8A774B1_CLK_S0D4, CLK_S0, 4, 1), 83 DEF_FIXED("s0d6", R8A774B1_CLK_S0D6, CLK_S0, 6, 1), 84 DEF_FIXED("s0d8", R8A774B1_CLK_S0D8, CLK_S0, 8, 1), 85 DEF_FIXED("s0d12", R8A774B1_CLK_S0D12, CLK_S0, 12, 1), 86 DEF_FIXED("s1d2", R8A774B1_CLK_S1D2, CLK_S1, 2, 1), 87 DEF_FIXED("s1d4", R8A774B1_CLK_S1D4, CLK_S1, 4, 1), 88 DEF_FIXED("s2d1", R8A774B1_CLK_S2D1, CLK_S2, 1, 1), 89 DEF_FIXED("s2d2", R8A774B1_CLK_S2D2, CLK_S2, 2, 1), 90 DEF_FIXED("s2d4", R8A774B1_CLK_S2D4, CLK_S2, 4, 1), 91 DEF_FIXED("s3d1", R8A774B1_CLK_S3D1, CLK_S3, 1, 1), 92 DEF_FIXED("s3d2", R8A774B1_CLK_S3D2, CLK_S3, 2, 1), 93 DEF_FIXED("s3d4", R8A774B1_CLK_S3D4, CLK_S3, 4, 1), 94 95 DEF_GEN3_SDH("sd0h", R8A774B1_CLK_SD0H, CLK_SDSRC, 0x074), 96 DEF_GEN3_SDH("sd1h", R8A774B1_CLK_SD1H, CLK_SDSRC, 0x078), 97 DEF_GEN3_SDH("sd2h", R8A774B1_CLK_SD2H, CLK_SDSRC, 0x268), 98 DEF_GEN3_SDH("sd3h", R8A774B1_CLK_SD3H, CLK_SDSRC, 0x26c), 99 DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, R8A774B1_CLK_SD0H, 0x074), 100 DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, R8A774B1_CLK_SD1H, 0x078), 101 DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, R8A774B1_CLK_SD2H, 0x268), 102 DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, R8A774B1_CLK_SD3H, 0x26c), 103 104 DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), 105 DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774B1_CLK_RPC), 106 107 DEF_FIXED("cl", R8A774B1_CLK_CL, CLK_PLL1_DIV2, 48, 1), 108 DEF_FIXED("cp", R8A774B1_CLK_CP, CLK_EXTAL, 2, 1), 109 DEF_FIXED("cpex", R8A774B1_CLK_CPEX, CLK_EXTAL, 2, 1), 110 111 DEF_DIV6P1("canfd", R8A774B1_CLK_CANFD, CLK_PLL1_DIV4, 0x244), 112 DEF_DIV6P1("csi0", R8A774B1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), 113 DEF_DIV6P1("mso", R8A774B1_CLK_MSO, CLK_PLL1_DIV4, 0x014), 114 DEF_DIV6P1("hdmi", R8A774B1_CLK_HDMI, CLK_PLL1_DIV4, 0x250), 115 116 DEF_GEN3_OSC("osc", R8A774B1_CLK_OSC, CLK_EXTAL, 8), 117 118 DEF_BASE("r", R8A774B1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), 119}; 120 121static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = { 122 DEF_MOD("3dge", 112, R8A774B1_CLK_ZG), 123 DEF_MOD("tmu4", 121, R8A774B1_CLK_S0D6), 124 DEF_MOD("tmu3", 122, R8A774B1_CLK_S3D2), 125 DEF_MOD("tmu2", 123, R8A774B1_CLK_S3D2), 126 DEF_MOD("tmu1", 124, R8A774B1_CLK_S3D2), 127 DEF_MOD("tmu0", 125, R8A774B1_CLK_CP), 128 DEF_MOD("fdp1-0", 119, R8A774B1_CLK_S0D1), 129 DEF_MOD("scif5", 202, R8A774B1_CLK_S3D4), 130 DEF_MOD("scif4", 203, R8A774B1_CLK_S3D4), 131 DEF_MOD("scif3", 204, R8A774B1_CLK_S3D4), 132 DEF_MOD("scif1", 206, R8A774B1_CLK_S3D4), 133 DEF_MOD("scif0", 207, R8A774B1_CLK_S3D4), 134 DEF_MOD("msiof3", 208, R8A774B1_CLK_MSO), 135 DEF_MOD("msiof2", 209, R8A774B1_CLK_MSO), 136 DEF_MOD("msiof1", 210, R8A774B1_CLK_MSO), 137 DEF_MOD("msiof0", 211, R8A774B1_CLK_MSO), 138 DEF_MOD("sys-dmac2", 217, R8A774B1_CLK_S3D1), 139 DEF_MOD("sys-dmac1", 218, R8A774B1_CLK_S3D1), 140 DEF_MOD("sys-dmac0", 219, R8A774B1_CLK_S0D3), 141 DEF_MOD("cmt3", 300, R8A774B1_CLK_R), 142 DEF_MOD("cmt2", 301, R8A774B1_CLK_R), 143 DEF_MOD("cmt1", 302, R8A774B1_CLK_R), 144 DEF_MOD("cmt0", 303, R8A774B1_CLK_R), 145 DEF_MOD("tpu0", 304, R8A774B1_CLK_S3D4), 146 DEF_MOD("scif2", 310, R8A774B1_CLK_S3D4), 147 DEF_MOD("sdif3", 311, R8A774B1_CLK_SD3), 148 DEF_MOD("sdif2", 312, R8A774B1_CLK_SD2), 149 DEF_MOD("sdif1", 313, R8A774B1_CLK_SD1), 150 DEF_MOD("sdif0", 314, R8A774B1_CLK_SD0), 151 DEF_MOD("pcie1", 318, R8A774B1_CLK_S3D1), 152 DEF_MOD("pcie0", 319, R8A774B1_CLK_S3D1), 153 DEF_MOD("usb3-if0", 328, R8A774B1_CLK_S3D1), 154 DEF_MOD("usb-dmac0", 330, R8A774B1_CLK_S3D1), 155 DEF_MOD("usb-dmac1", 331, R8A774B1_CLK_S3D1), 156 DEF_MOD("rwdt", 402, R8A774B1_CLK_R), 157 DEF_MOD("intc-ex", 407, R8A774B1_CLK_CP), 158 DEF_MOD("intc-ap", 408, R8A774B1_CLK_S0D3), 159 DEF_MOD("audmac1", 501, R8A774B1_CLK_S1D2), 160 DEF_MOD("audmac0", 502, R8A774B1_CLK_S1D2), 161 DEF_MOD("hscif4", 516, R8A774B1_CLK_S3D1), 162 DEF_MOD("hscif3", 517, R8A774B1_CLK_S3D1), 163 DEF_MOD("hscif2", 518, R8A774B1_CLK_S3D1), 164 DEF_MOD("hscif1", 519, R8A774B1_CLK_S3D1), 165 DEF_MOD("hscif0", 520, R8A774B1_CLK_S3D1), 166 DEF_MOD("thermal", 522, R8A774B1_CLK_CP), 167 DEF_MOD("pwm", 523, R8A774B1_CLK_S0D12), 168 DEF_MOD("fcpvd1", 602, R8A774B1_CLK_S0D2), 169 DEF_MOD("fcpvd0", 603, R8A774B1_CLK_S0D2), 170 DEF_MOD("fcpvb0", 607, R8A774B1_CLK_S0D1), 171 DEF_MOD("fcpvi0", 611, R8A774B1_CLK_S0D1), 172 DEF_MOD("fcpf0", 615, R8A774B1_CLK_S0D1), 173 DEF_MOD("fcpcs", 619, R8A774B1_CLK_S0D2), 174 DEF_MOD("vspd1", 622, R8A774B1_CLK_S0D2), 175 DEF_MOD("vspd0", 623, R8A774B1_CLK_S0D2), 176 DEF_MOD("vspb", 626, R8A774B1_CLK_S0D1), 177 DEF_MOD("vspi0", 631, R8A774B1_CLK_S0D1), 178 DEF_MOD("ehci1", 702, R8A774B1_CLK_S3D2), 179 DEF_MOD("ehci0", 703, R8A774B1_CLK_S3D2), 180 DEF_MOD("hsusb", 704, R8A774B1_CLK_S3D2), 181 DEF_MOD("csi20", 714, R8A774B1_CLK_CSI0), 182 DEF_MOD("csi40", 716, R8A774B1_CLK_CSI0), 183 DEF_MOD("du3", 721, R8A774B1_CLK_S2D1), 184 DEF_MOD("du1", 723, R8A774B1_CLK_S2D1), 185 DEF_MOD("du0", 724, R8A774B1_CLK_S2D1), 186 DEF_MOD("lvds", 727, R8A774B1_CLK_S2D1), 187 DEF_MOD("hdmi0", 729, R8A774B1_CLK_HDMI), 188 DEF_MOD("vin7", 804, R8A774B1_CLK_S0D2), 189 DEF_MOD("vin6", 805, R8A774B1_CLK_S0D2), 190 DEF_MOD("vin5", 806, R8A774B1_CLK_S0D2), 191 DEF_MOD("vin4", 807, R8A774B1_CLK_S0D2), 192 DEF_MOD("vin3", 808, R8A774B1_CLK_S0D2), 193 DEF_MOD("vin2", 809, R8A774B1_CLK_S0D2), 194 DEF_MOD("vin1", 810, R8A774B1_CLK_S0D2), 195 DEF_MOD("vin0", 811, R8A774B1_CLK_S0D2), 196 DEF_MOD("etheravb", 812, R8A774B1_CLK_S0D6), 197 DEF_MOD("sata0", 815, R8A774B1_CLK_S3D2), 198 DEF_MOD("gpio7", 905, R8A774B1_CLK_S3D4), 199 DEF_MOD("gpio6", 906, R8A774B1_CLK_S3D4), 200 DEF_MOD("gpio5", 907, R8A774B1_CLK_S3D4), 201 DEF_MOD("gpio4", 908, R8A774B1_CLK_S3D4), 202 DEF_MOD("gpio3", 909, R8A774B1_CLK_S3D4), 203 DEF_MOD("gpio2", 910, R8A774B1_CLK_S3D4), 204 DEF_MOD("gpio1", 911, R8A774B1_CLK_S3D4), 205 DEF_MOD("gpio0", 912, R8A774B1_CLK_S3D4), 206 DEF_MOD("can-fd", 914, R8A774B1_CLK_S3D2), 207 DEF_MOD("can-if1", 915, R8A774B1_CLK_S3D4), 208 DEF_MOD("can-if0", 916, R8A774B1_CLK_S3D4), 209 DEF_MOD("rpc-if", 917, R8A774B1_CLK_RPCD2), 210 DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6), 211 DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6), 212 DEF_MOD("adg", 922, R8A774B1_CLK_S0D4), 213 DEF_MOD("iic-pmic", 926, R8A774B1_CLK_CP), 214 DEF_MOD("i2c4", 927, R8A774B1_CLK_S0D6), 215 DEF_MOD("i2c3", 928, R8A774B1_CLK_S0D6), 216 DEF_MOD("i2c2", 929, R8A774B1_CLK_S3D2), 217 DEF_MOD("i2c1", 930, R8A774B1_CLK_S3D2), 218 DEF_MOD("i2c0", 931, R8A774B1_CLK_S3D2), 219 DEF_MOD("ssi-all", 1005, R8A774B1_CLK_S3D4), 220 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)), 221 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)), 222 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)), 223 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)), 224 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)), 225 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)), 226 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)), 227 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), 228 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), 229 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), 230 DEF_MOD("scu-all", 1017, R8A774B1_CLK_S3D4), 231 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), 232 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), 233 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)), 234 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)), 235 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)), 236 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)), 237 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)), 238 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)), 239 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)), 240 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)), 241 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)), 242 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)), 243 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)), 244 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), 245}; 246 247/* 248 * CPG Clock Data 249 */ 250 251/* 252 * MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC 253 * 14 13 19 17 (MHz) 254 *----------------------------------------------------------------- 255 * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16 256 * 0 0 0 1 16.66 x 1 x180 x192 x128 x144 /16 257 * 0 0 1 0 Prohibited setting 258 * 0 0 1 1 16.66 x 1 x180 x192 x192 x144 /16 259 * 0 1 0 0 20 x 1 x150 x160 x160 x120 /19 260 * 0 1 0 1 20 x 1 x150 x160 x106 x120 /19 261 * 0 1 1 0 Prohibited setting 262 * 0 1 1 1 20 x 1 x150 x160 x160 x120 /19 263 * 1 0 0 0 25 x 1 x120 x128 x128 x96 /24 264 * 1 0 0 1 25 x 1 x120 x128 x84 x96 /24 265 * 1 0 1 0 Prohibited setting 266 * 1 0 1 1 25 x 1 x120 x128 x128 x96 /24 267 * 1 1 0 0 33.33 / 2 x180 x192 x192 x144 /32 268 * 1 1 0 1 33.33 / 2 x180 x192 x128 x144 /32 269 * 1 1 1 0 Prohibited setting 270 * 1 1 1 1 33.33 / 2 x180 x192 x192 x144 /32 271 */ 272#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ 273 (((md) & BIT(13)) >> 11) | \ 274 (((md) & BIT(19)) >> 18) | \ 275 (((md) & BIT(17)) >> 17)) 276 277static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { 278 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */ 279 { 1, 192, 1, 192, 1, 16, }, 280 { 1, 192, 1, 128, 1, 16, }, 281 { 0, /* Prohibited setting */ }, 282 { 1, 192, 1, 192, 1, 16, }, 283 { 1, 160, 1, 160, 1, 19, }, 284 { 1, 160, 1, 106, 1, 19, }, 285 { 0, /* Prohibited setting */ }, 286 { 1, 160, 1, 160, 1, 19, }, 287 { 1, 128, 1, 128, 1, 24, }, 288 { 1, 128, 1, 84, 1, 24, }, 289 { 0, /* Prohibited setting */ }, 290 { 1, 128, 1, 128, 1, 24, }, 291 { 2, 192, 1, 192, 1, 32, }, 292 { 2, 192, 1, 128, 1, 32, }, 293 { 0, /* Prohibited setting */ }, 294 { 2, 192, 1, 192, 1, 32, }, 295}; 296 297/* RMSTPCR[0-11] is not present on RZ/G2N */ 298static const struct mstp_stop_table r8a774b1_mstp_table[] = { 299 { 0x00200000, 0x0, 0x0, 0 }, 300 { 0xFFFFFFFF, 0x0, 0x0, 0 }, 301 { 0x340E2FDC, 0x2040, 0x0, 0 }, 302 { 0xFFFFFFDF, 0x400, 0x0, 0 }, 303 { 0x80000184, 0x180, 0x0, 0 }, 304 { 0xC3FFFFFF, 0x0, 0x0, 0 }, 305 { 0xFFFFFFFF, 0x0, 0x0, 0 }, 306 { 0xFFFFFFFF, 0x0, 0x0, 0 }, 307 { 0x01F1FFF7, 0x0, 0x0, 0 }, 308 { 0xFFFFFFFE, 0x0, 0x0, 0 }, 309 { 0xFFFEFFE0, 0x0, 0x0, 0 }, 310 { 0x000000B7, 0x0, 0x0, 0 }, 311}; 312 313static const void *r8a774b1_get_pll_config(const u32 cpg_mode) 314{ 315 return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; 316} 317 318static const struct cpg_mssr_info r8a774b1_cpg_mssr_info = { 319 .core_clk = r8a774b1_core_clks, 320 .core_clk_size = ARRAY_SIZE(r8a774b1_core_clks), 321 .mod_clk = r8a774b1_mod_clks, 322 .mod_clk_size = ARRAY_SIZE(r8a774b1_mod_clks), 323 .mstp_table = r8a774b1_mstp_table, 324 .mstp_table_size = ARRAY_SIZE(r8a774b1_mstp_table), 325 .reset_node = "renesas,r8a774b1-rst", 326 .reset_modemr_offset = CPG_RST_MODEMR, 327 .extalr_node = "extalr", 328 .mod_clk_base = MOD_CLK_BASE, 329 .clk_extal_id = CLK_EXTAL, 330 .clk_extalr_id = CLK_EXTALR, 331 .get_pll_config = r8a774b1_get_pll_config, 332}; 333 334static const struct udevice_id r8a774b1_cpg_ids[] = { 335 { 336 .compatible = "renesas,r8a774b1-cpg-mssr", 337 .data = (ulong)&r8a774b1_cpg_mssr_info, 338 }, 339 { } 340}; 341 342U_BOOT_DRIVER(cpg_r8a774b1) = { 343 .name = "cpg_r8a774b1", 344 .id = UCLASS_NOP, 345 .of_match = r8a774b1_cpg_ids, 346 .bind = gen3_cpg_bind, 347}; 348