1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Clock drivers for Qualcomm sm8550 4 * 5 * (C) Copyright 2024 Linaro Ltd. 6 */ 7 8#include <clk-uclass.h> 9#include <dm.h> 10#include <linux/delay.h> 11#include <errno.h> 12#include <asm/io.h> 13#include <linux/bug.h> 14#include <linux/bitops.h> 15#include <dt-bindings/clock/qcom,sm8550-gcc.h> 16#include <dt-bindings/clock/qcom,sm8550-tcsr.h> 17 18#include "clock-qcom.h" 19 20/* On-board TCXO, TOFIX get from DT */ 21#define TCXO_RATE 38400000 22 23/* bi_tcxo_div2 divided after RPMh output */ 24#define TCXO_DIV2_RATE (TCXO_RATE / 2) 25 26static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s2_clk_src[] = { 27 F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625), 28 F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625), 29 F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), 30 F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625), 31 F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75), 32 F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25), 33 F(51200000, CFG_CLK_SRC_GPLL0_EVEN, 1, 64, 375), 34 F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75), 35 F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), 36 F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15), 37 F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25), 38 F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0), 39 { } 40}; 41 42static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 43 F(400000, CFG_CLK_SRC_CXO, 12, 1, 4), 44 F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0), 45 F(37500000, CFG_CLK_SRC_GPLL0_EVEN, 8, 0, 0), 46 F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0), 47 F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), 48 /* TOFIX F(202000000, CFG_CLK_SRC_GPLL9, 4, 0, 0), */ 49 { } 50}; 51 52static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 53 F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0), 54 F(133333333, CFG_CLK_SRC_GPLL0, 4.5, 0, 0), 55 F(200000000, CFG_CLK_SRC_GPLL0, 3, 0, 0), 56 F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0), 57 { } 58}; 59 60static ulong sm8550_set_rate(struct clk *clk, ulong rate) 61{ 62 struct msm_clk_priv *priv = dev_get_priv(clk->dev); 63 const struct freq_tbl *freq; 64 65 switch (clk->id) { 66 case GCC_QUPV3_WRAP1_S7_CLK: /* UART7 */ 67 freq = qcom_find_freq(ftbl_gcc_qupv3_wrap1_s2_clk_src, rate); 68 clk_rcg_set_rate_mnd(priv->base, 0x18898, 69 freq->pre_div, freq->m, freq->n, freq->src, 16); 70 return freq->freq; 71 case GCC_SDCC2_APPS_CLK: 72 freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate); 73 clk_rcg_set_rate_mnd(priv->base, 0x14018, 74 freq->pre_div, freq->m, freq->n, freq->src, 8); 75 return freq->freq; 76 case GCC_USB30_PRIM_MASTER_CLK: 77 freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate); 78 clk_rcg_set_rate_mnd(priv->base, 0x3902c, 79 freq->pre_div, freq->m, freq->n, freq->src, 8); 80 return freq->freq; 81 case GCC_USB30_PRIM_MOCK_UTMI_CLK: 82 clk_rcg_set_rate(priv->base, 0x39044, 0, 0); 83 return TCXO_DIV2_RATE; 84 case GCC_USB3_PRIM_PHY_AUX_CLK_SRC: 85 clk_rcg_set_rate(priv->base, 0x39070, 0, 0); 86 return TCXO_DIV2_RATE; 87 default: 88 return 0; 89 } 90} 91 92static const struct gate_clk sm8550_clks[] = { 93 GATE_CLK(GCC_AGGRE_NOC_PCIE_AXI_CLK, 0x52000, BIT(12)), 94 GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770e4, BIT(0)), 95 GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK, 0x770e4, BIT(1)), 96 GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0x3908c, BIT(0)), 97 GATE_CLK(GCC_CNOC_PCIE_SF_AXI_CLK, 0x52008, BIT(6)), 98 GATE_CLK(GCC_DDRSS_GPU_AXI_CLK, 0x71154, BIT(0)), 99 GATE_CLK(GCC_DDRSS_PCIE_SF_QTB_CLK, 0x52000, BIT(19)), 100 GATE_CLK(GCC_PCIE_0_AUX_CLK, 0x52008, BIT(3)), 101 GATE_CLK(GCC_PCIE_0_CFG_AHB_CLK, 0x52008, BIT(2)), 102 GATE_CLK(GCC_PCIE_0_MSTR_AXI_CLK, 0x52008, BIT(1)), 103 GATE_CLK(GCC_PCIE_0_PHY_RCHNG_CLK, 0x52000, BIT(22)), 104 GATE_CLK(GCC_PCIE_0_PIPE_CLK, 0x52008, BIT(4)), 105 GATE_CLK(GCC_PCIE_0_SLV_AXI_CLK, 0x52008, BIT(0)), 106 GATE_CLK(GCC_PCIE_0_SLV_Q2A_AXI_CLK, 0x52008, BIT(5)), 107 GATE_CLK(GCC_PCIE_1_AUX_CLK, 0x52000, BIT(29)), 108 GATE_CLK(GCC_PCIE_1_CFG_AHB_CLK, 0x52000, BIT(28)), 109 GATE_CLK(GCC_PCIE_1_MSTR_AXI_CLK, 0x52000, BIT(27)), 110 GATE_CLK(GCC_PCIE_1_PHY_AUX_CLK, 0x52000, BIT(24)), 111 GATE_CLK(GCC_PCIE_1_PHY_RCHNG_CLK, 0x52000, BIT(23)), 112 GATE_CLK(GCC_PCIE_1_PIPE_CLK, 0x52000, BIT(30)), 113 GATE_CLK(GCC_PCIE_1_SLV_AXI_CLK, 0x52000, BIT(26)), 114 GATE_CLK(GCC_PCIE_1_SLV_Q2A_AXI_CLK, 0x52000, BIT(25)), 115 GATE_CLK(GCC_QUPV3_I2C_CORE_CLK, 0x52008, BIT(8)), 116 GATE_CLK(GCC_QUPV3_I2C_S0_CLK, 0x52008, BIT(10)), 117 GATE_CLK(GCC_QUPV3_I2C_S1_CLK, 0x52008, BIT(11)), 118 GATE_CLK(GCC_QUPV3_I2C_S2_CLK, 0x52008, BIT(12)), 119 GATE_CLK(GCC_QUPV3_I2C_S3_CLK, 0x52008, BIT(13)), 120 GATE_CLK(GCC_QUPV3_I2C_S4_CLK, 0x52008, BIT(14)), 121 GATE_CLK(GCC_QUPV3_I2C_S5_CLK, 0x52008, BIT(15)), 122 GATE_CLK(GCC_QUPV3_I2C_S6_CLK, 0x52008, BIT(16)), 123 GATE_CLK(GCC_QUPV3_I2C_S7_CLK, 0x52008, BIT(17)), 124 GATE_CLK(GCC_QUPV3_I2C_S8_CLK, 0x52010, BIT(14)), 125 GATE_CLK(GCC_QUPV3_I2C_S9_CLK, 0x52010, BIT(15)), 126 GATE_CLK(GCC_QUPV3_I2C_S_AHB_CLK, 0x52008, BIT(7)), 127 GATE_CLK(GCC_QUPV3_WRAP1_CORE_2X_CLK, 0x52008, BIT(18)), 128 GATE_CLK(GCC_QUPV3_WRAP1_CORE_CLK, 0x52008, BIT(19)), 129 GATE_CLK(GCC_QUPV3_WRAP1_S0_CLK, 0x52008, BIT(22)), 130 GATE_CLK(GCC_QUPV3_WRAP1_S1_CLK, 0x52008, BIT(23)), 131 GATE_CLK(GCC_QUPV3_WRAP1_S2_CLK, 0x52008, BIT(24)), 132 GATE_CLK(GCC_QUPV3_WRAP1_S3_CLK, 0x52008, BIT(25)), 133 GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x52008, BIT(26)), 134 GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x52008, BIT(27)), 135 GATE_CLK(GCC_QUPV3_WRAP1_S6_CLK, 0x52008, BIT(28)), 136 GATE_CLK(GCC_QUPV3_WRAP1_S7_CLK, 0x52010, BIT(16)), 137 GATE_CLK(GCC_QUPV3_WRAP2_CORE_2X_CLK, 0x52010, BIT(3)), 138 GATE_CLK(GCC_QUPV3_WRAP2_CORE_CLK, 0x52010, BIT(0)), 139 GATE_CLK(GCC_QUPV3_WRAP2_S0_CLK, 0x52010, BIT(4)), 140 GATE_CLK(GCC_QUPV3_WRAP2_S1_CLK, 0x52010, BIT(5)), 141 GATE_CLK(GCC_QUPV3_WRAP2_S2_CLK, 0x52010, BIT(6)), 142 GATE_CLK(GCC_QUPV3_WRAP2_S3_CLK, 0x52010, BIT(7)), 143 GATE_CLK(GCC_QUPV3_WRAP2_S4_CLK, 0x52010, BIT(8)), 144 GATE_CLK(GCC_QUPV3_WRAP2_S5_CLK, 0x52010, BIT(9)), 145 GATE_CLK(GCC_QUPV3_WRAP2_S6_CLK, 0x52010, BIT(10)), 146 GATE_CLK(GCC_QUPV3_WRAP2_S7_CLK, 0x52010, BIT(17)), 147 GATE_CLK(GCC_QUPV3_WRAP_1_M_AHB_CLK, 0x52008, BIT(20)), 148 GATE_CLK(GCC_QUPV3_WRAP_1_S_AHB_CLK, 0x52008, BIT(21)), 149 GATE_CLK(GCC_QUPV3_WRAP_2_M_AHB_CLK, 0x52010, BIT(2)), 150 GATE_CLK(GCC_QUPV3_WRAP_2_S_AHB_CLK, 0x52010, BIT(1)), 151 GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14010, BIT(0)), 152 GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, BIT(0)), 153 GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77024, BIT(0)), 154 GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77018, BIT(0)), 155 GATE_CLK(GCC_UFS_PHY_AXI_HW_CTL_CLK, 0x77018, BIT(1)), 156 GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77074, BIT(0)), 157 GATE_CLK(GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK, 0x77074, BIT(1)), 158 GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x770b0, BIT(0)), 159 GATE_CLK(GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK, 0x770b0, BIT(1)), 160 GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x7702c, BIT(0)), 161 GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x770cc, BIT(0)), 162 GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x77028, BIT(0)), 163 GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x77068, BIT(0)), 164 GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK, 0x77068, BIT(1)), 165 GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x39018, BIT(0)), 166 GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x39028, BIT(0)), 167 GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x39024, BIT(0)), 168 GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x39060, BIT(0)), 169 GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x39064, BIT(0)), 170 GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x39068, BIT(0)), 171}; 172 173static int sm8550_enable(struct clk *clk) 174{ 175 struct msm_clk_priv *priv = dev_get_priv(clk->dev); 176 177 switch (clk->id) { 178 case GCC_AGGRE_USB3_PRIM_AXI_CLK: 179 qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK); 180 fallthrough; 181 case GCC_USB30_PRIM_MASTER_CLK: 182 qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK); 183 qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); 184 break; 185 } 186 187 qcom_gate_clk_en(priv, clk->id); 188 189 return 0; 190} 191 192static const struct qcom_reset_map sm8550_gcc_resets[] = { 193 [GCC_CAMERA_BCR] = { 0x26000 }, 194 [GCC_DISPLAY_BCR] = { 0x27000 }, 195 [GCC_GPU_BCR] = { 0x71000 }, 196 [GCC_PCIE_0_BCR] = { 0x6b000 }, 197 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, 198 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, 199 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 200 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 }, 201 [GCC_PCIE_1_BCR] = { 0x8d000 }, 202 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 }, 203 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 }, 204 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, 205 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 }, 206 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 207 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c }, 208 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 }, 209 [GCC_PDM_BCR] = { 0x33000 }, 210 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, 211 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, 212 [GCC_QUPV3_WRAPPER_I2C_BCR] = { 0x17000 }, 213 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 214 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 215 [GCC_SDCC2_BCR] = { 0x14000 }, 216 [GCC_SDCC4_BCR] = { 0x16000 }, 217 [GCC_UFS_PHY_BCR] = { 0x77000 }, 218 [GCC_USB30_PRIM_BCR] = { 0x39000 }, 219 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, 220 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, 221 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 222 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, 223 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 224 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 225 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 226 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 }, 227 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x32024, 2 }, 228 [GCC_VIDEO_BCR] = { 0x32000 }, 229}; 230 231static const struct qcom_power_map sm8550_gdscs[] = { 232 [PCIE_0_GDSC] = { 0x6b004 }, 233 [PCIE_0_PHY_GDSC] = { 0x6c000 }, 234 [PCIE_1_GDSC] = { 0x8d004 }, 235 [PCIE_1_PHY_GDSC] = { 0x8e000 }, 236 [UFS_PHY_GDSC] = { 0x77004 }, 237 [UFS_MEM_PHY_GDSC] = { 0x9e000 }, 238 [USB30_PRIM_GDSC] = { 0x39004 }, 239 [USB3_PHY_GDSC] = { 0x50018 }, 240}; 241 242static struct msm_clk_data sm8550_gcc_data = { 243 .resets = sm8550_gcc_resets, 244 .num_resets = ARRAY_SIZE(sm8550_gcc_resets), 245 .clks = sm8550_clks, 246 .num_clks = ARRAY_SIZE(sm8550_clks), 247 .power_domains = sm8550_gdscs, 248 .num_power_domains = ARRAY_SIZE(sm8550_gdscs), 249 250 .enable = sm8550_enable, 251 .set_rate = sm8550_set_rate, 252}; 253 254static const struct udevice_id gcc_sm8550_of_match[] = { 255 { 256 .compatible = "qcom,sm8550-gcc", 257 .data = (ulong)&sm8550_gcc_data, 258 }, 259 { } 260}; 261 262U_BOOT_DRIVER(gcc_sm8550) = { 263 .name = "gcc_sm8550", 264 .id = UCLASS_NOP, 265 .of_match = gcc_sm8550_of_match, 266 .bind = qcom_cc_bind, 267 .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, 268}; 269 270/* TCSRCC */ 271 272static const struct gate_clk sm8550_tcsr_clks[] = { 273 GATE_CLK(TCSR_PCIE_0_CLKREF_EN, 0x15100, BIT(0)), 274 GATE_CLK(TCSR_PCIE_1_CLKREF_EN, 0x15114, BIT(0)), 275 GATE_CLK(TCSR_UFS_CLKREF_EN, 0x15110, BIT(0)), 276 GATE_CLK(TCSR_UFS_PAD_CLKREF_EN, 0x15104, BIT(0)), 277 GATE_CLK(TCSR_USB2_CLKREF_EN, 0x15118, BIT(0)), 278 GATE_CLK(TCSR_USB3_CLKREF_EN, 0x15108, BIT(0)), 279}; 280 281static struct msm_clk_data sm8550_tcsrcc_data = { 282 .clks = sm8550_tcsr_clks, 283 .num_clks = ARRAY_SIZE(sm8550_tcsr_clks), 284}; 285 286static int tcsrcc_sm8550_clk_enable(struct clk *clk) 287{ 288 struct msm_clk_priv *priv = dev_get_priv(clk->dev); 289 290 qcom_gate_clk_en(priv, clk->id); 291 292 return 0; 293} 294 295static ulong tcsrcc_sm8550_clk_get_rate(struct clk *clk) 296{ 297 return TCXO_RATE; 298} 299 300static int tcsrcc_sm8550_clk_probe(struct udevice *dev) 301{ 302 struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(dev); 303 struct msm_clk_priv *priv = dev_get_priv(dev); 304 305 priv->base = dev_read_addr(dev); 306 if (priv->base == FDT_ADDR_T_NONE) 307 return -EINVAL; 308 309 priv->data = data; 310 311 return 0; 312} 313 314static struct clk_ops tcsrcc_sm8550_clk_ops = { 315 .enable = tcsrcc_sm8550_clk_enable, 316 .get_rate = tcsrcc_sm8550_clk_get_rate, 317}; 318 319static const struct udevice_id tcsrcc_sm8550_of_match[] = { 320 { 321 .compatible = "qcom,sm8550-tcsr", 322 .data = (ulong)&sm8550_tcsrcc_data, 323 }, 324 { } 325}; 326 327U_BOOT_DRIVER(tcsrcc_sm8550) = { 328 .name = "tcsrcc_sm8550", 329 .id = UCLASS_CLK, 330 .of_match = tcsrcc_sm8550_of_match, 331 .ops = &tcsrcc_sm8550_clk_ops, 332 .priv_auto = sizeof(struct msm_clk_priv), 333 .probe = tcsrcc_sm8550_clk_probe, 334 .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, 335}; 336