1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Clock drivers for Qualcomm SDM845 4 * 5 * (C) Copyright 2017 Jorge Ramirez Ortiz <jorge.ramirez-ortiz@linaro.org> 6 * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com> 7 * 8 * Based on Little Kernel driver, simplified 9 */ 10 11#include <common.h> 12#include <clk-uclass.h> 13#include <dm.h> 14#include <linux/delay.h> 15#include <errno.h> 16#include <asm/io.h> 17#include <linux/bitops.h> 18#include <dt-bindings/clock/qcom,gcc-sdm845.h> 19 20#include "clock-qcom.h" 21 22#define SE9_UART_APPS_CMD_RCGR 0x18148 23 24#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf018 25#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf030 26#define USB3_PRIM_PHY_AUX_CMD_RCGR 0xf05c 27#define SDCC2_APPS_CLK_CMD_RCGR 0x1400c 28 29static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { 30 F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625), 31 F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625), 32 F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), 33 F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625), 34 F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75), 35 F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25), 36 F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75), 37 F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15), 38 F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25), 39 F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), 40 F(102400000, CFG_CLK_SRC_GPLL0_EVEN, 1, 128, 375), 41 F(112000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 28, 75), 42 F(117964800, CFG_CLK_SRC_GPLL0_EVEN, 1, 6144, 15625), 43 F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0), 44 F(128000000, CFG_CLK_SRC_GPLL0, 1, 16, 75), 45 { } 46}; 47 48static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 49 F(400000, CFG_CLK_SRC_CXO, 12, 1, 4), 50 F(9600000, CFG_CLK_SRC_CXO, 2, 0, 0), 51 F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), 52 F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0), 53 F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0), 54 F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0), 55 F(201500000, CFG_CLK_SRC_GPLL4, 4, 0, 0), 56 { } 57}; 58 59static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate) 60{ 61 struct msm_clk_priv *priv = dev_get_priv(clk->dev); 62 const struct freq_tbl *freq; 63 64 switch (clk->id) { 65 case GCC_QUPV3_WRAP1_S1_CLK: /* UART9 */ 66 freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate); 67 clk_rcg_set_rate_mnd(priv->base, SE9_UART_APPS_CMD_RCGR, 68 freq->pre_div, freq->m, freq->n, freq->src, 16); 69 return freq->freq; 70 case GCC_SDCC2_APPS_CLK: 71 freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate); 72 clk_rcg_set_rate_mnd(priv->base, SDCC2_APPS_CLK_CMD_RCGR, 73 freq->pre_div, freq->m, freq->n, freq->src, 8); 74 return freq->freq; 75 default: 76 return 0; 77 } 78} 79 80static const struct gate_clk sdm845_clks[] = { 81 GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK, 0x82020, 0x00000001), 82 GATE_CLK(GCC_CFG_NOC_USB3_SEC_AXI_CLK, 0x05030, 0x00000001), 83 GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, 0x00000400), 84 GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, 0x00000800), 85 GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, 0x00001000), 86 GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x5200c, 0x00002000), 87 GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK, 0x5200c, 0x00004000), 88 GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x5200c, 0x00008000), 89 GATE_CLK(GCC_QUPV3_WRAP0_S6_CLK, 0x5200c, 0x00010000), 90 GATE_CLK(GCC_QUPV3_WRAP0_S7_CLK, 0x5200c, 0x00020000), 91 GATE_CLK(GCC_QUPV3_WRAP1_S0_CLK, 0x5200c, 0x00400000), 92 GATE_CLK(GCC_QUPV3_WRAP1_S1_CLK, 0x5200c, 0x00800000), 93 GATE_CLK(GCC_QUPV3_WRAP1_S3_CLK, 0x5200c, 0x02000000), 94 GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x5200c, 0x04000000), 95 GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x5200c, 0x08000000), 96 GATE_CLK(GCC_QUPV3_WRAP1_S6_CLK, 0x5200c, 0x10000000), 97 GATE_CLK(GCC_QUPV3_WRAP1_S7_CLK, 0x5200c, 0x20000000), 98 GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x5200c, 0x00000040), 99 GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x5200c, 0x00000080), 100 GATE_CLK(GCC_QUPV3_WRAP_1_M_AHB_CLK, 0x5200c, 0x00100000), 101 GATE_CLK(GCC_QUPV3_WRAP_1_S_AHB_CLK, 0x5200c, 0x00200000), 102 GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14008, 0x00000001), 103 GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, 0x00000001), 104 GATE_CLK(GCC_SDCC4_AHB_CLK, 0x16008, 0x00000001), 105 GATE_CLK(GCC_SDCC4_APPS_CLK, 0x16004, 0x00000001), 106 GATE_CLK(GCC_UFS_CARD_AHB_CLK, 0x75010, 0x00000001), 107 GATE_CLK(GCC_UFS_CARD_AXI_CLK, 0x7500c, 0x00000001), 108 GATE_CLK(GCC_UFS_CARD_CLKREF_CLK, 0x8c004, 0x00000001), 109 GATE_CLK(GCC_UFS_CARD_ICE_CORE_CLK, 0x75058, 0x00000001), 110 GATE_CLK(GCC_UFS_CARD_PHY_AUX_CLK, 0x7508c, 0x00000001), 111 GATE_CLK(GCC_UFS_CARD_RX_SYMBOL_0_CLK, 0x75018, 0x00000001), 112 GATE_CLK(GCC_UFS_CARD_RX_SYMBOL_1_CLK, 0x750a8, 0x00000001), 113 GATE_CLK(GCC_UFS_CARD_TX_SYMBOL_0_CLK, 0x75014, 0x00000001), 114 GATE_CLK(GCC_UFS_CARD_UNIPRO_CORE_CLK, 0x75054, 0x00000001), 115 GATE_CLK(GCC_UFS_MEM_CLKREF_CLK, 0x8c000, 0x00000001), 116 GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77010, 0x00000001), 117 GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x7700c, 0x00000001), 118 GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77058, 0x00000001), 119 GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x7708c, 0x00000001), 120 GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x77018, 0x00000001), 121 GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x770a8, 0x00000001), 122 GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x77014, 0x00000001), 123 GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x77054, 0x00000001), 124 GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x0f00c, 0x00000001), 125 GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x0f014, 0x00000001), 126 GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x0f010, 0x00000001), 127 GATE_CLK(GCC_USB30_SEC_MASTER_CLK, 0x1000c, 0x00000001), 128 GATE_CLK(GCC_USB30_SEC_MOCK_UTMI_CLK, 0x10014, 0x00000001), 129 GATE_CLK(GCC_USB30_SEC_SLEEP_CLK, 0x10010, 0x00000001), 130 GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x8c008, 0x00000001), 131 GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x0f04c, 0x00000001), 132 GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x0f050, 0x00000001), 133 GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x0f054, 0x00000001), 134 GATE_CLK(GCC_USB3_SEC_CLKREF_CLK, 0x8c028, 0x00000001), 135 GATE_CLK(GCC_USB3_SEC_PHY_AUX_CLK, 0x1004c, 0x00000001), 136 GATE_CLK(GCC_USB3_SEC_PHY_PIPE_CLK, 0x10054, 0x00000001), 137 GATE_CLK(GCC_USB3_SEC_PHY_COM_AUX_CLK, 0x10050, 0x00000001), 138 GATE_CLK(GCC_USB_PHY_CFG_AHB2PHY_CLK, 0x6a004, 0x00000001), 139}; 140 141static int sdm845_clk_enable(struct clk *clk) 142{ 143 struct msm_clk_priv *priv = dev_get_priv(clk->dev); 144 145 debug("%s: clk %s\n", __func__, sdm845_clks[clk->id].name); 146 147 switch (clk->id) { 148 case GCC_USB30_PRIM_MASTER_CLK: 149 qcom_gate_clk_en(priv, GCC_USB_PHY_CFG_AHB2PHY_CLK); 150 /* These numbers are just pulled from the frequency tables in the Linux driver */ 151 clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR, 152 (4.5 * 2) - 1, 0, 0, 1 << 8, 8); 153 clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 154 1, 0, 0, 0, 8); 155 clk_rcg_set_rate_mnd(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 156 1, 0, 0, 0, 8); 157 break; 158 case GCC_USB30_SEC_MASTER_CLK: 159 qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_AUX_CLK); 160 161 qcom_gate_clk_en(priv, GCC_USB3_SEC_CLKREF_CLK); 162 qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK); 163 break; 164 } 165 166 qcom_gate_clk_en(priv, clk->id); 167 168 return 0; 169} 170 171static const struct qcom_reset_map sdm845_gcc_resets[] = { 172 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 }, 173 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, 174 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 175 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 176 [GCC_SDCC2_BCR] = { 0x14000 }, 177 [GCC_SDCC4_BCR] = { 0x16000 }, 178 [GCC_UFS_CARD_BCR] = { 0x75000 }, 179 [GCC_UFS_PHY_BCR] = { 0x77000 }, 180 [GCC_USB30_PRIM_BCR] = { 0xf000 }, 181 [GCC_USB30_SEC_BCR] = { 0x10000 }, 182 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 183 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 184 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, 185 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, 186 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 187 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, 188 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, 189}; 190 191static const struct qcom_power_map sdm845_gdscs[] = { 192 [PCIE_0_GDSC] = { 0x6b004 }, 193 [PCIE_1_GDSC] = { 0x8d004 }, 194 [UFS_CARD_GDSC] = { 0x75004 }, 195 [UFS_PHY_GDSC] = { 0x77004 }, 196 [USB30_PRIM_GDSC] = { 0xf004 }, 197 [USB30_SEC_GDSC] = { 0x10004 }, 198 [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = { 0x7d030 }, 199 [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] = { 0x7d03c }, 200 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = { 0x7d034 }, 201 [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = { 0x7d038 }, 202 [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = { 0x7d040 }, 203 [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = { 0x7d048 }, 204 [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = { 0x7d044 }, 205}; 206 207static struct msm_clk_data sdm845_clk_data = { 208 .resets = sdm845_gcc_resets, 209 .num_resets = ARRAY_SIZE(sdm845_gcc_resets), 210 .clks = sdm845_clks, 211 .num_clks = ARRAY_SIZE(sdm845_clks), 212 .power_domains = sdm845_gdscs, 213 .num_power_domains = ARRAY_SIZE(sdm845_gdscs), 214 215 .enable = sdm845_clk_enable, 216 .set_rate = sdm845_clk_set_rate, 217}; 218 219static const struct udevice_id gcc_sdm845_of_match[] = { 220 { 221 .compatible = "qcom,gcc-sdm845", 222 .data = (ulong)&sdm845_clk_data, 223 }, 224 { } 225}; 226 227U_BOOT_DRIVER(gcc_sdm845) = { 228 .name = "gcc_sdm845", 229 .id = UCLASS_NOP, 230 .of_match = gcc_sdm845_of_match, 231 .bind = qcom_cc_bind, 232 .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, 233}; 234