1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2016 4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc 5 * 6 * (C) Copyright 2017, 2018 7 * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc 8 */ 9 10#include <axi.h> 11#include <dm.h> 12#include <log.h> 13#include <regmap.h> 14#include <linux/bitops.h> 15#include <linux/delay.h> 16 17/** 18 * struct ihs_axi_regs - Structure for the register map of a IHS AXI device 19 * @interrupt_status: Status register to indicate certain events (e.g. 20 * error during transfer, transfer complete, etc.) 21 * @interrupt_enable_control: Register to both control which statuses will be 22 * indicated in the interrupt_status register, and 23 * to change bus settings 24 * @address_lsb: Least significant 16-bit word of the address of a 25 * device to transfer data from/to 26 * @address_msb: Most significant 16-bit word of the address of a 27 * device to transfer data from/to 28 * @write_data_lsb: Least significant 16-bit word of the data to be 29 * written to a device 30 * @write_data_msb: Most significant 16-bit word of the data to be 31 * written to a device 32 * @read_data_lsb: Least significant 16-bit word of the data read 33 * from a device 34 * @read_data_msb: Most significant 16-bit word of the data read 35 * from a device 36 */ 37struct ihs_axi_regs { 38 u16 interrupt_status; 39 u16 interrupt_enable_control; 40 u16 address_lsb; 41 u16 address_msb; 42 u16 write_data_lsb; 43 u16 write_data_msb; 44 u16 read_data_lsb; 45 u16 read_data_msb; 46}; 47 48/** 49 * ihs_axi_set() - Convenience macro to set values in register map 50 * @map: The register map to write to 51 * @member: The member of the ihs_axi_regs structure to write 52 * @val: The value to write to the register map 53 */ 54#define ihs_axi_set(map, member, val) \ 55 regmap_set(map, struct ihs_axi_regs, member, val) 56 57/** 58 * ihs_axi_get() - Convenience macro to read values from register map 59 * @map: The register map to read from 60 * @member: The member of the ihs_axi_regs structure to read 61 * @valp: Pointer to a buffer to receive the value read 62 */ 63#define ihs_axi_get(map, member, valp) \ 64 regmap_get(map, struct ihs_axi_regs, member, valp) 65 66/** 67 * struct ihs_axi_priv - Private data structure of IHS AXI devices 68 * @map: Register map for the IHS AXI device 69 */ 70struct ihs_axi_priv { 71 struct regmap *map; 72}; 73 74/** 75 * enum status_reg - Description of bits in the interrupt_status register 76 * @STATUS_READ_COMPLETE_EVENT: A read transfer was completed 77 * @STATUS_WRITE_COMPLETE_EVENT: A write transfer was completed 78 * @STATUS_TIMEOUT_EVENT: A timeout has occurred during the transfer 79 * @STATUS_ERROR_EVENT: A error has occurred during the transfer 80 * @STATUS_AXI_INT: A AXI interrupt has occurred 81 * @STATUS_READ_DATA_AVAILABLE: Data is available to be read 82 * @STATUS_BUSY: The bus is busy 83 * @STATUS_INIT_DONE: The bus has finished initializing 84 */ 85enum status_reg { 86 STATUS_READ_COMPLETE_EVENT = BIT(15), 87 STATUS_WRITE_COMPLETE_EVENT = BIT(14), 88 STATUS_TIMEOUT_EVENT = BIT(13), 89 STATUS_ERROR_EVENT = BIT(12), 90 STATUS_AXI_INT = BIT(11), 91 STATUS_READ_DATA_AVAILABLE = BIT(7), 92 STATUS_BUSY = BIT(6), 93 STATUS_INIT_DONE = BIT(5), 94}; 95 96/** 97 * enum control_reg - Description of bit fields in the interrupt_enable_control 98 * register 99 * @CONTROL_READ_COMPLETE_EVENT_ENABLE: STATUS_READ_COMPLETE_EVENT will be 100 * raised in the interrupt_status register 101 * @CONTROL_WRITE_COMPLETE_EVENT_ENABLE: STATUS_WRITE_COMPLETE_EVENT will be 102 * raised in the interrupt_status register 103 * @CONTROL_TIMEOUT_EVENT_ENABLE: STATUS_TIMEOUT_EVENT will be raised in 104 * the interrupt_status register 105 * @CONTROL_ERROR_EVENT_ENABLE: STATUS_ERROR_EVENT will be raised in 106 * the interrupt_status register 107 * @CONTROL_AXI_INT_ENABLE: STATUS_AXI_INT will be raised in the 108 * interrupt_status register 109 * @CONTROL_CMD_NOP: Configure bus to send a NOP command 110 * for the next transfer 111 * @CONTROL_CMD_WRITE: Configure bus to do a write transfer 112 * @CONTROL_CMD_WRITE_POST_INC: Auto-increment address after write 113 * transfer 114 * @CONTROL_CMD_READ: Configure bus to do a read transfer 115 * @CONTROL_CMD_READ_POST_INC: Auto-increment address after read 116 * transfer 117 */ 118enum control_reg { 119 CONTROL_READ_COMPLETE_EVENT_ENABLE = BIT(15), 120 CONTROL_WRITE_COMPLETE_EVENT_ENABLE = BIT(14), 121 CONTROL_TIMEOUT_EVENT_ENABLE = BIT(13), 122 CONTROL_ERROR_EVENT_ENABLE = BIT(12), 123 CONTROL_AXI_INT_ENABLE = BIT(11), 124 125 CONTROL_CMD_NOP = 0x0, 126 CONTROL_CMD_WRITE = 0x8, 127 CONTROL_CMD_WRITE_POST_INC = 0x9, 128 CONTROL_CMD_READ = 0xa, 129 CONTROL_CMD_READ_POST_INC = 0xb, 130}; 131 132/** 133 * enum axi_cmd - Determine if transfer is read or write transfer 134 * @AXI_CMD_READ: The transfer should be a read transfer 135 * @AXI_CMD_WRITE: The transfer should be a write transfer 136 */ 137enum axi_cmd { 138 AXI_CMD_READ, 139 AXI_CMD_WRITE, 140}; 141 142/** 143 * ihs_axi_transfer() - Run transfer on the AXI bus 144 * @bus: The AXI bus device on which to run the transfer on 145 * @address: The address to use in the transfer (i.e. which address to 146 * read/write from/to) 147 * @cmd: Should the transfer be a read or write transfer? 148 * 149 * Return: 0 if OK, -ve on error 150 */ 151static int ihs_axi_transfer(struct udevice *bus, ulong address, 152 enum axi_cmd cmd) 153{ 154 struct ihs_axi_priv *priv = dev_get_priv(bus); 155 /* Try waiting for events up to 10 times */ 156 const uint WAIT_TRIES = 10; 157 u16 wait_mask = STATUS_TIMEOUT_EVENT | 158 STATUS_ERROR_EVENT; 159 u16 complete_flag; 160 u16 status; 161 uint k; 162 163 if (cmd == AXI_CMD_READ) { 164 complete_flag = STATUS_READ_COMPLETE_EVENT; 165 cmd = CONTROL_CMD_READ; 166 } else { 167 complete_flag = STATUS_WRITE_COMPLETE_EVENT; 168 cmd = CONTROL_CMD_WRITE; 169 } 170 171 wait_mask |= complete_flag; 172 173 /* Lower 16 bit */ 174 ihs_axi_set(priv->map, address_lsb, address & 0xffff); 175 /* Upper 16 bit */ 176 ihs_axi_set(priv->map, address_msb, (address >> 16) & 0xffff); 177 178 ihs_axi_set(priv->map, interrupt_status, wait_mask); 179 ihs_axi_set(priv->map, interrupt_enable_control, cmd); 180 181 for (k = WAIT_TRIES; k > 0; --k) { 182 ihs_axi_get(priv->map, interrupt_status, &status); 183 if (status & wait_mask) 184 break; 185 udelay(1); 186 } 187 188 /* 189 * k == 0 -> Tries ran out with no event we were waiting for actually 190 * occurring. 191 */ 192 if (!k) 193 ihs_axi_get(priv->map, interrupt_status, &status); 194 195 if (status & complete_flag) 196 return 0; 197 198 if (status & STATUS_ERROR_EVENT) { 199 debug("%s: Error occurred during transfer\n", bus->name); 200 return -EIO; 201 } 202 203 debug("%s: Transfer timed out\n", bus->name); 204 return -ETIMEDOUT; 205} 206 207/* 208 * API 209 */ 210 211static int ihs_axi_read(struct udevice *dev, ulong address, void *data, 212 enum axi_size_t size) 213{ 214 struct ihs_axi_priv *priv = dev_get_priv(dev); 215 int ret; 216 u16 data_lsb, data_msb; 217 u32 *p = data; 218 219 if (size != AXI_SIZE_32) { 220 debug("%s: transfer size '%d' not supported\n", 221 dev->name, size); 222 return -ENOSYS; 223 } 224 225 ret = ihs_axi_transfer(dev, address, AXI_CMD_READ); 226 if (ret < 0) { 227 debug("%s: Error during AXI transfer (err = %d)\n", 228 dev->name, ret); 229 return ret; 230 } 231 232 ihs_axi_get(priv->map, read_data_lsb, &data_lsb); 233 ihs_axi_get(priv->map, read_data_msb, &data_msb); 234 235 /* Assemble data from two 16-bit words */ 236 *p = (data_msb << 16) | data_lsb; 237 238 return 0; 239} 240 241static int ihs_axi_write(struct udevice *dev, ulong address, void *data, 242 enum axi_size_t size) 243{ 244 struct ihs_axi_priv *priv = dev_get_priv(dev); 245 int ret; 246 u32 *p = data; 247 248 if (size != AXI_SIZE_32) { 249 debug("%s: transfer size '%d' not supported\n", 250 dev->name, size); 251 return -ENOSYS; 252 } 253 254 /* Lower 16 bit */ 255 ihs_axi_set(priv->map, write_data_lsb, *p & 0xffff); 256 /* Upper 16 bit */ 257 ihs_axi_set(priv->map, write_data_msb, (*p >> 16) & 0xffff); 258 259 ret = ihs_axi_transfer(dev, address, AXI_CMD_WRITE); 260 if (ret < 0) { 261 debug("%s: Error during AXI transfer (err = %d)\n", 262 dev->name, ret); 263 return ret; 264 } 265 266 return 0; 267} 268 269static const struct udevice_id ihs_axi_ids[] = { 270 { .compatible = "gdsys,ihs_axi" }, 271 { /* sentinel */ } 272}; 273 274static const struct axi_ops ihs_axi_ops = { 275 .read = ihs_axi_read, 276 .write = ihs_axi_write, 277}; 278 279static int ihs_axi_probe(struct udevice *dev) 280{ 281 struct ihs_axi_priv *priv = dev_get_priv(dev); 282 283 regmap_init_mem(dev_ofnode(dev), &priv->map); 284 285 return 0; 286} 287 288U_BOOT_DRIVER(ihs_axi_bus) = { 289 .name = "ihs_axi_bus", 290 .id = UCLASS_AXI, 291 .of_match = ihs_axi_ids, 292 .ops = &ihs_axi_ops, 293 .priv_auto = sizeof(struct ihs_axi_priv), 294 .probe = ihs_axi_probe, 295}; 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