1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2014-2023 Tony Dinh <mibodhi@gmail.com>
4 *
5 * Based on
6 * Copyright (C) 2014  Jason Plum <jplum@archlinuxarm.org>
7 *
8 * Based on nsa320.c originall written by
9 * Copyright (C) 2012  Peter Schildmann <linux@schildmann.info>
10 *
11 * Based on guruplug.c originally written by
12 * Siddarth Gore <gores@marvell.com>
13 * (C) Copyright 2009
14 * Marvell Semiconductor <www.marvell.com>
15 */
16
17#include <common.h>
18#include <asm/arch/soc.h>
19#include <asm/arch/mpp.h>
20#include <netdev.h>
21#include <asm/arch/cpu.h>
22#include <asm/gpio.h>
23#include <asm/io.h>
24#include <asm/arch/gpio.h>
25#include <asm/mach-types.h>
26#include <bootstage.h>
27#include <command.h>
28#include <init.h>
29#include <linux/bitops.h>
30
31DECLARE_GLOBAL_DATA_PTR;
32
33/* low GPIO's */
34#define HDD2_GREEN_LED		BIT(12)
35#define HDD2_RED_LED		BIT(13)
36#define USB_GREEN_LED		BIT(15)
37#define USB_POWER		BIT(21)
38#define SYS_GREEN_LED		BIT(28)
39#define SYS_ORANGE_LED		BIT(29)
40
41#define PIN_USB_GREEN_LED	15
42#define PIN_USB_POWER		21
43
44#define NSA325_OE_LOW		(~(HDD2_GREEN_LED | HDD2_RED_LED |	\
45				   USB_GREEN_LED | USB_POWER |		\
46				   SYS_GREEN_LED | SYS_ORANGE_LED))
47#define NSA325_VAL_LOW		(SYS_GREEN_LED | USB_POWER)
48
49/* high GPIO's */
50#define COPY_GREEN_LED		BIT(7)
51#define COPY_RED_LED		BIT(8)
52#define HDD1_GREEN_LED		BIT(9)
53#define HDD1_RED_LED		BIT(10)
54#define HDD2_POWER		BIT(15)
55#define WATCHDOG_SIGNAL		BIT(14)
56
57#define NSA325_OE_HIGH		(~(COPY_GREEN_LED | COPY_RED_LED | \
58				   HDD1_GREEN_LED | HDD1_RED_LED | HDD2_POWER | WATCHDOG_SIGNAL))
59#define NSA325_VAL_HIGH		(WATCHDOG_SIGNAL | HDD2_POWER)
60
61#define BTN_POWER				46
62#define BTN_RESET				36
63#define BTN_COPY				37
64
65int board_early_init_f(void)
66{
67	/*
68	 * default gpio configuration
69	 * There are maximum 64 gpios controlled through 2 sets of registers
70	 * the below configuration configures mainly initial LED status
71	 */
72	mvebu_config_gpio(NSA325_VAL_LOW, NSA325_VAL_HIGH,
73			  NSA325_OE_LOW, NSA325_OE_HIGH);
74
75	/* Multi-Purpose Pins Functionality configuration */
76	/* (all LEDs & power off active high) */
77	u32 kwmpp_config[] = {
78		MPP0_NF_IO2,
79		MPP1_NF_IO3,
80		MPP2_NF_IO4,
81		MPP3_NF_IO5,
82		MPP4_NF_IO6,
83		MPP5_NF_IO7,
84		MPP6_SYSRST_OUTn,
85		MPP7_GPO,
86		MPP8_TW_SDA,		/* PCF8563 RTC chip   */
87		MPP9_TW_SCK,		/* connected to TWSI  */
88		MPP10_UART0_TXD,
89		MPP11_UART0_RXD,
90		MPP12_GPO,		/* HDD2 LED (green)   */
91		MPP13_GPIO,		/* HDD2 LED (red)     */
92		MPP14_GPIO,		/* MCU DATA pin (in)  */
93		MPP15_GPIO,		/* USB LED (green)    */
94		MPP16_GPIO,		/* MCU CLK pin (out)  */
95		MPP17_GPIO,		/* MCU ACT pin (out)  */
96		MPP18_NF_IO0,
97		MPP19_NF_IO1,
98		MPP20_GPIO,
99		MPP21_GPIO,		/* USB power          */
100		MPP22_GPIO,
101		MPP23_GPIO,
102		MPP24_GPIO,
103		MPP25_GPIO,
104		MPP26_GPIO,
105		MPP27_GPIO,
106		MPP28_GPIO,		/* SYS LED (green)    */
107		MPP29_GPIO,		/* SYS LED (orange)   */
108		MPP30_GPIO,
109		MPP31_GPIO,
110		MPP32_GPIO,
111		MPP33_GPIO,
112		MPP34_GPIO,
113		MPP35_GPIO,
114		MPP36_GPIO,		/* reset button       */
115		MPP37_GPIO,		/* copy button        */
116		MPP38_GPIO,		/* VID B0             */
117		MPP39_GPIO,		/* COPY LED (green)   */
118		MPP40_GPIO,		/* COPY LED (red)     */
119		MPP41_GPIO,		/* HDD1 LED (green)   */
120		MPP42_GPIO,		/* HDD1 LED (red)     */
121		MPP43_GPIO,		/* HTP pin            */
122		MPP44_GPIO,		/* buzzer             */
123		MPP45_GPIO,		/* VID B1             */
124		MPP46_GPIO,		/* power button       */
125		MPP47_GPIO,		/* HDD2 power         */
126		MPP48_GPIO,		/* power off          */
127		0
128	};
129	kirkwood_mpp_conf(kwmpp_config, NULL);
130	return 0;
131}
132
133int board_eth_init(struct bd_info *bis)
134{
135	return cpu_eth_init(bis);
136}
137
138int board_init(void)
139{
140	/* address of boot parameters */
141	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
142
143	return 0;
144}
145
146int board_late_init(void)
147{
148	/* Do late init to ensure successful enumeration of XHCI devices */
149	pci_init();
150	return 0;
151}
152
153#if defined(CONFIG_SHOW_BOOT_PROGRESS)
154void show_boot_progress(int val)
155{
156	struct kwgpio_registers *gpio0 = (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
157	u32 dout0 = readl(&gpio0->dout);
158	u32 blen0 = readl(&gpio0->blink_en);
159
160	struct kwgpio_registers *gpio1 = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
161	u32 dout1 = readl(&gpio1->dout);
162	u32 blen1 = readl(&gpio1->blink_en);
163
164	switch (val) {
165	case BOOTSTAGE_ID_DECOMP_IMAGE:
166		writel(blen0 & ~(SYS_GREEN_LED | SYS_ORANGE_LED), &gpio0->blink_en);
167		writel((dout0 & ~SYS_GREEN_LED) | SYS_ORANGE_LED, &gpio0->dout);
168		break;
169	case BOOTSTAGE_ID_RUN_OS:
170		writel(dout0 & ~SYS_ORANGE_LED, &gpio0->dout);
171		writel(blen0 | SYS_GREEN_LED, &gpio0->blink_en);
172		break;
173	case BOOTSTAGE_ID_NET_START:
174		writel(dout1 & ~COPY_RED_LED, &gpio1->dout);
175		writel((blen1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->blink_en);
176		break;
177	case BOOTSTAGE_ID_NET_LOADED:
178		writel(blen1 & ~(COPY_RED_LED | COPY_GREEN_LED), &gpio1->blink_en);
179		writel((dout1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->dout);
180		break;
181	case -BOOTSTAGE_ID_NET_NETLOOP_OK:
182	case -BOOTSTAGE_ID_NET_LOADED:
183		writel(dout1 & ~COPY_GREEN_LED, &gpio1->dout);
184		writel((blen1 & ~COPY_GREEN_LED) | COPY_RED_LED, &gpio1->blink_en);
185		break;
186	default:
187		if (val < 0) {
188			/* error */
189			printf("Error occurred, error code = %d\n", -val);
190			writel(dout0 & ~SYS_GREEN_LED, &gpio0->dout);
191			writel(blen0 | SYS_ORANGE_LED, &gpio0->blink_en);
192		}
193		break;
194	}
195}
196#endif /* CONFIG_SHOW_BOOT_PROGRESS */
197