1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2022 NXP
4 * Copyright 2023 Variscite Ltd.
5 */
6
7#include <env.h>
8#include <init.h>
9#include <miiphy.h>
10#include <netdev.h>
11#include <asm/global_data.h>
12#include <asm/arch-imx9/ccm_regs.h>
13#include <asm/arch/sys_proto.h>
14#include <asm/arch-imx9/imx93_pins.h>
15#include <asm/arch/clock.h>
16#include <power/pmic.h>
17#include <dm/device.h>
18#include <dm/uclass.h>
19
20#include "../common/imx9_eeprom.h"
21#include "../common/eth.h"
22
23DECLARE_GLOBAL_DATA_PTR;
24
25#define CARRIER_EEPROM_ADDR 0x54
26
27#define UART_PAD_CTRL	(PAD_CTL_DSE(6) | PAD_CTL_FSEL2)
28#define WDOG_PAD_CTRL	(PAD_CTL_DSE(6) | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
29
30static const iomux_v3_cfg_t uart_pads[] = {
31	MX93_PAD_UART1_RXD__LPUART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
32	MX93_PAD_UART1_TXD__LPUART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
33};
34
35int board_early_init_f(void)
36{
37	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
38
39	init_uart_clk(LPUART1_CLK_ROOT);
40
41	return 0;
42}
43
44int board_phys_sdram_size(phys_size_t *size)
45{
46	struct var_eeprom *ep = VAR_EEPROM_DATA;
47
48	var_eeprom_get_dram_size(ep, size);
49	return 0;
50}
51
52int board_phy_config(struct phy_device *phydev)
53{
54	if (phydev->drv->config)
55		phydev->drv->config(phydev);
56
57	return 0;
58}
59
60static int setup_eqos(void)
61{
62	struct blk_ctrl_wakeupmix_regs *bctrl =
63		(struct blk_ctrl_wakeupmix_regs *)BLK_CTRL_WAKEUPMIX_BASE_ADDR;
64
65	/* set INTF as RGMII, enable RGMII TXC clock */
66	clrsetbits_le32(&bctrl->eqos_gpr,
67			BCTRL_GPR_ENET_QOS_INTF_MODE_MASK,
68			BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII | BCTRL_GPR_ENET_QOS_CLK_GEN_EN);
69
70	return set_clk_eqos(ENET_125MHZ);
71}
72
73int board_init(void)
74{
75	set_clk_enet(ENET_125MHZ);
76
77	if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
78		setup_eqos();
79
80	return 0;
81}
82
83#define SDRAM_SIZE_STR_LEN 5
84
85int board_late_init(void)
86{
87	int ret;
88	struct var_eeprom *ep = VAR_EEPROM_DATA;
89	char sdram_size_str[SDRAM_SIZE_STR_LEN];
90	struct var_carrier_eeprom carrier_eeprom;
91	char carrier_rev[CARRIER_REV_LEN] = {0};
92	char som_rev[CARRIER_REV_LEN] = {0};
93
94	var_setup_mac(ep);
95	var_eeprom_print_prod_info(ep);
96
97	/* SDRAM ENV */
98	snprintf(sdram_size_str, SDRAM_SIZE_STR_LEN, "%d",
99		 (int)(gd->ram_size / 1024 / 1024));
100	env_set("sdram_size", sdram_size_str);
101
102	/* Carrier Board ENV */
103	ret = var_carrier_eeprom_read(VAR_CARRIER_EEPROM_I2C_NAME,
104				      CARRIER_EEPROM_ADDR, &carrier_eeprom);
105	if (!ret) {
106		var_carrier_eeprom_get_revision(&carrier_eeprom, carrier_rev,
107						sizeof(carrier_rev));
108		env_set("carrier_rev", carrier_rev);
109	}
110
111	/* SoM Rev ENV */
112	snprintf(som_rev, CARRIER_REV_LEN, "som_rev1%d", ep->somrev);
113	env_set("som_rev", som_rev);
114
115	if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
116		board_late_mmc_env_init();
117
118	env_set("sec_boot", "no");
119	if (IS_ENABLED(CONFIG_AHAB_BOOT))
120		env_set("sec_boot", "yes");
121
122	if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
123		env_set("board_name", "VAR-SOM-MX93");
124
125	return 0;
126}
127