1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2012-2016 Toradex, Inc.
4 */
5
6#include <common.h>
7#include <log.h>
8#include <asm/io.h>
9#include <asm/arch-tegra/tegra_i2c.h>
10#include <linux/delay.h>
11
12/* AS3722-PMIC-specific early init regs */
13
14#define AS3722_I2C_ADDR		0x80
15
16#define AS3722_SD0VOLTAGE_REG	0x00	/* CPU */
17#define AS3722_SD1VOLTAGE_REG	0x01	/* CORE, already set by OTP */
18#define AS3722_SD6VOLTAGE_REG	0x06	/* GPU */
19#define AS3722_SDCONTROL_REG	0x4D
20
21#define AS3722_LDO1VOLTAGE_REG	0x11	/* VDD_SDMMC1 */
22#define AS3722_LDO2VOLTAGE_REG	0x12	/* VPP_FUSE */
23#define AS3722_LDO6VOLTAGE_REG	0x16	/* VDD_SDMMC3 */
24#define AS3722_LDCONTROL_REG	0x4E
25
26#define AS3722_SD0VOLTAGE_DATA	(0x3C00 | AS3722_SD0VOLTAGE_REG)
27#define AS3722_SD0CONTROL_DATA	(0x0100 | AS3722_SDCONTROL_REG)
28
29#define AS3722_SD1VOLTAGE_DATA	(0x3200 | AS3722_SD1VOLTAGE_REG)
30#define AS3722_SD1CONTROL_DATA	(0x0200 | AS3722_SDCONTROL_REG)
31
32#define AS3722_SD6CONTROL_DATA	(0x4000 | AS3722_SDCONTROL_REG)
33#define AS3722_SD6VOLTAGE_DATA	(0x2800 | AS3722_SD6VOLTAGE_REG)
34
35#define AS3722_LDO1CONTROL_DATA	(0x0200 | AS3722_LDCONTROL_REG)
36#define AS3722_LDO1VOLTAGE_DATA	(0x7F00 | AS3722_LDO1VOLTAGE_REG)
37
38#define AS3722_LDO2CONTROL_DATA	(0x0400 | AS3722_LDCONTROL_REG)
39#define AS3722_LDO2VOLTAGE_DATA	(0x1000 | AS3722_LDO2VOLTAGE_REG)
40
41#define AS3722_LDO6CONTROL_DATA	(0x4000 | AS3722_LDCONTROL_REG)
42#define AS3722_LDO6VOLTAGE_DATA	(0x3F00 | AS3722_LDO6VOLTAGE_REG)
43
44/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
45
46void pmic_enable_cpu_vdd(void)
47{
48	debug("%s entry\n", __func__);
49
50#ifdef AS3722_SD1VOLTAGE_DATA
51	/* Set up VDD_CORE, for boards where OTP is incorrect*/
52	debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
53	/* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
54	tegra_i2c_ll_write(AS3722_I2C_ADDR,
55			   AS3722_SD1VOLTAGE_DATA);
56	/*
57	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
58	 * tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
59	 */
60	udelay(10 * 1000);
61#endif
62
63	/*
64	 * Make sure all non-fused regulators are down.
65	 * That way we're in known state after software reboot from linux
66	 */
67	tegra_i2c_ll_write(AS3722_I2C_ADDR, 0x0003);
68	udelay(10 * 1000);
69	tegra_i2c_ll_write(AS3722_I2C_ADDR, 0x0004);
70	udelay(10 * 1000);
71	tegra_i2c_ll_write(AS3722_I2C_ADDR, 0x001b);
72	udelay(10 * 1000);
73	tegra_i2c_ll_write(AS3722_I2C_ADDR, 0x0014);
74	udelay(10 * 1000);
75	tegra_i2c_ll_write(AS3722_I2C_ADDR, 0x001a);
76	udelay(10 * 1000);
77	tegra_i2c_ll_write(AS3722_I2C_ADDR, 0x0019);
78	udelay(10 * 1000);
79
80	debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
81	/*
82	 * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
83	 * First set VDD to 1.0V, then enable the VDD regulator.
84	 */
85	tegra_i2c_ll_write(AS3722_I2C_ADDR,
86			   AS3722_SD0VOLTAGE_DATA);
87	/*
88	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
89	 * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
90	 */
91	udelay(10 * 1000);
92
93	debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
94	/*
95	 * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
96	 * First set VDD to 1.0V, then enable the VDD regulator.
97	 */
98	tegra_i2c_ll_write(AS3722_I2C_ADDR,
99			   AS3722_SD6VOLTAGE_DATA);
100	/*
101	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
102	 * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
103	 */
104	udelay(10 * 1000);
105
106	debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
107	/*
108	 * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
109	 * First set VDD to 1.2V, then enable the VDD regulator.
110	 */
111	tegra_i2c_ll_write(AS3722_I2C_ADDR,
112			   AS3722_LDO2VOLTAGE_DATA);
113	/*
114	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
115	 * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
116	 */
117	udelay(10 * 1000);
118
119	debug("%s: Set VDD_SDMMC1 to 3.3V via AS3722 reg 0x11/4E\n", __func__);
120	/*
121	 * Bring up VDD_SDMMC1 via the AS3722 PMIC on the PWR I2C bus.
122	 * First set it to value closest to 3.3V, then enable the regulator
123	 *
124	 * NOTE: We do this early because doing it later seems to hose the CPU
125	 * power rail/partition startup. Need to debug.
126	 */
127	tegra_i2c_ll_write(AS3722_I2C_ADDR,
128			   AS3722_LDO1VOLTAGE_DATA);
129	/*
130	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
131	 * tegra_i2c_ll_write_data(AS3722_LDO1CONTROL_DATA, I2C_SEND_2_BYTES);
132	 */
133	udelay(10 * 1000);
134
135	debug("%s: Set VDD_SDMMC3 to 3.3V via AS3722 reg 0x16/4E\n", __func__);
136	/*
137	 * Bring up VDD_SDMMC3 via the AS3722 PMIC on the PWR I2C bus.
138	 * First set it to bypass 3.3V straight thru, then enable the regulator
139	 *
140	 * NOTE: We do this early because doing it later seems to hose the CPU
141	 * power rail/partition startup. Need to debug.
142	 */
143	tegra_i2c_ll_write(AS3722_I2C_ADDR,
144			   AS3722_LDO6VOLTAGE_DATA);
145	/*
146	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
147	 * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
148	 */
149	udelay(10 * 1000);
150}
151