1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright 2008 Freescale Semiconductor, Inc. 4 */ 5 6 7#include <fsl_ddr_sdram.h> 8#include <fsl_ddr_dimm_params.h> 9 10void fsl_ddr_board_options(memctl_options_t *popts, 11 dimm_params_t *pdimm, 12 unsigned int ctrl_num) 13{ 14 /* 15 * Factors to consider for clock adjust: 16 * - number of chips on bus 17 * - position of slot 18 * - DDR1 vs. DDR2? 19 * - ??? 20 * 21 * This needs to be determined on a board-by-board basis. 22 * 0110 3/4 cycle late 23 * 0111 7/8 cycle late 24 */ 25 popts->clk_adjust = 7; 26 27 /* 28 * Factors to consider for CPO: 29 * - frequency 30 * - ddr1 vs. ddr2 31 */ 32 popts->cpo_override = 0; 33 34 /* 35 * Factors to consider for write data delay: 36 * - number of DIMMs 37 * 38 * 1 = 1/4 clock delay 39 * 2 = 1/2 clock delay 40 * 3 = 3/4 clock delay 41 * 4 = 1 clock delay 42 * 5 = 5/4 clock delay 43 * 6 = 3/2 clock delay 44 */ 45 popts->write_data_delay = 3; 46 47 /* 48 * Factors to consider for half-strength driver enable: 49 * - number of DIMMs installed 50 */ 51 popts->half_strength_driver_enable = 0; 52} 53