1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Board functions for TI AM335X based rut board
4 * (C) Copyright 2013 Siemens Schweiz AG
5 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
6 *
7 * Based on:
8 * u-boot:/board/ti/am335x/board.c
9 *
10 * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
11 */
12
13#include <cpsw.h>
14#include <env.h>
15#include <init.h>
16#include <linux/delay.h>
17#include <nand.h>
18#include <asm/arch/clock.h>
19#include <asm/arch/ddr_defs.h>
20#include <asm/arch/sys_proto.h>
21#include <asm/gpio.h>
22#include <asm/io.h>
23#include "../common/board_am335x.h"
24#include "../common/eeprom.h"
25#include "../common/factoryset.h"
26
27#ifdef CONFIG_SPL_BUILD
28/*
29 * Read header information from EEPROM into global structure.
30 */
31int draco_read_eeprom(void)
32{
33	return 0;
34}
35
36void draco_init_ddr(void)
37{
38struct emif_regs rut_ddr3_emif_reg_data = {
39	.sdram_config = 0x61C04AB2,
40	.sdram_tim1 = 0x0888A39B,
41	.sdram_tim2 = 0x26337FDA,
42	.sdram_tim3 = 0x501F830F,
43	.emif_ddr_phy_ctlr_1 = 0x6,
44	.zq_config = 0x50074BE4,
45	.ref_ctrl = 0x93B,
46};
47
48struct ddr_data rut_ddr3_data = {
49	.datardsratio0 = 0x3b,
50	.datawdsratio0 = 0x85,
51	.datafwsratio0 = 0x100,
52	.datawrsratio0 = 0xc1,
53};
54
55struct cmd_control rut_ddr3_cmd_ctrl_data = {
56	.cmd0csratio = 0x40,
57	.cmd0iclkout = 1,
58	.cmd1csratio = 0x40,
59	.cmd1iclkout = 1,
60	.cmd2csratio = 0x40,
61	.cmd2iclkout = 1,
62};
63
64const struct ctrl_ioregs ioregs = {
65	.cm0ioctl		= RUT_IOCTRL_VAL,
66	.cm1ioctl		= RUT_IOCTRL_VAL,
67	.cm2ioctl		= RUT_IOCTRL_VAL,
68	.dt0ioctl		= RUT_IOCTRL_VAL,
69	.dt1ioctl		= RUT_IOCTRL_VAL,
70};
71
72	config_ddr(DDR_PLL_FREQ, &ioregs, &rut_ddr3_data,
73		   &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
74}
75
76static int request_and_pulse_reset(int gpio, const char *name)
77{
78	int ret;
79	const int delay_us = 2000; /* 2ms */
80
81	ret = gpio_request(gpio, name);
82	if (ret < 0) {
83		printf("%s: Unable to request %s\n", __func__, name);
84		goto err;
85	}
86
87	ret = gpio_direction_output(gpio, 0);
88	if (ret < 0) {
89		printf("%s: Unable to set %s  as output\n", __func__, name);
90		goto err_free_gpio;
91	}
92
93	udelay(delay_us);
94
95	gpio_set_value(gpio, 1);
96
97	return 0;
98
99err_free_gpio:
100	gpio_free(gpio);
101err:
102	return ret;
103}
104
105#define GPIO_TO_PIN(bank, gpio)		(32 * (bank) + (gpio))
106#define ETH_PHY_RESET_GPIO		GPIO_TO_PIN(2, 18)
107#define MAXTOUCH_RESET_GPIO		GPIO_TO_PIN(3, 18)
108#define DISPLAY_RESET_GPIO		GPIO_TO_PIN(3, 19)
109
110#define REQUEST_AND_PULSE_RESET(N) \
111		request_and_pulse_reset(N, #N);
112
113void spl_draco_board_init(void)
114{
115	REQUEST_AND_PULSE_RESET(ETH_PHY_RESET_GPIO);
116	REQUEST_AND_PULSE_RESET(MAXTOUCH_RESET_GPIO);
117	REQUEST_AND_PULSE_RESET(DISPLAY_RESET_GPIO);
118}
119#endif /* if def CONFIG_SPL_BUILD */
120
121#if defined(CONFIG_DRIVER_TI_CPSW)
122static void cpsw_control(int enabled)
123{
124	/* VTP can be added here */
125
126	return;
127}
128
129static struct cpsw_slave_data cpsw_slaves[] = {
130	{
131		.slave_reg_ofs	= 0x208,
132		.sliver_reg_ofs	= 0xd80,
133		.phy_addr	= 1,
134		.phy_if		= PHY_INTERFACE_MODE_RMII,
135	},
136	{
137		.slave_reg_ofs	= 0x308,
138		.sliver_reg_ofs	= 0xdc0,
139		.phy_addr	= 0,
140		.phy_if		= PHY_INTERFACE_MODE_RMII,
141	},
142};
143
144static struct cpsw_platform_data cpsw_data = {
145	.mdio_base		= CPSW_MDIO_BASE,
146	.cpsw_base		= CPSW_BASE,
147	.mdio_div		= 0xff,
148	.channels		= 8,
149	.cpdma_reg_ofs		= 0x800,
150	.slaves			= 1,
151	.slave_data		= cpsw_slaves,
152	.ale_reg_ofs		= 0xd00,
153	.ale_entries		= 1024,
154	.host_port_reg_ofs	= 0x108,
155	.hw_stats_reg_ofs	= 0x900,
156	.bd_ram_ofs		= 0x2000,
157	.mac_control		= (1 << 5),
158	.control		= cpsw_control,
159	.host_port_num		= 0,
160	.version		= CPSW_CTRL_VERSION_2,
161};
162
163#if defined(CONFIG_DRIVER_TI_CPSW) || \
164	(defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
165int board_eth_init(struct bd_info *bis)
166{
167	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
168	int n = 0;
169	int rv;
170
171#ifndef CONFIG_SPL_BUILD
172	factoryset_env_set();
173#endif
174
175	/* Set rgmii mode and enable rmii clock to be sourced from chip */
176	writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
177
178	rv = cpsw_register(&cpsw_data);
179	if (rv < 0)
180		printf("Error %d registering CPSW switch\n", rv);
181	else
182		n += rv;
183	return n;
184}
185#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
186#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
187
188#if defined(CONFIG_HW_WATCHDOG)
189static bool hw_watchdog_init_done;
190static int  hw_watchdog_trigger_level;
191
192void hw_watchdog_reset(void)
193{
194	if (!hw_watchdog_init_done)
195		return;
196
197	hw_watchdog_trigger_level = hw_watchdog_trigger_level ? 0 : 1;
198	gpio_set_value(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
199}
200
201void hw_watchdog_init(void)
202{
203	gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger");
204	gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
205
206	hw_watchdog_reset();
207
208	hw_watchdog_init_done = 1;
209}
210#endif /* defined(CONFIG_HW_WATCHDOG) */
211
212#ifdef CONFIG_BOARD_LATE_INIT
213int board_late_init(void)
214{
215	int ret;
216	char tmp[2 * MAX_STRING_LENGTH + 2];
217
218	omap_nand_switch_ecc(1, 8);
219
220	if (factory_dat.asn[0] != 0)
221		sprintf(tmp, "%s_%s", factory_dat.asn,
222			factory_dat.comp_version);
223	else
224		strcpy(tmp, "QMX7.E38_4.0");
225
226	ret = env_set("boardid", tmp);
227	if (ret)
228		printf("error setting board id\n");
229
230	return 0;
231}
232#endif
233