1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2014 Samsung Electronics 4 * Przemyslaw Marczak <p.marczak@samsung.com> 5 */ 6 7#include <common.h> 8#include <log.h> 9#include <asm/arch/pinmux.h> 10#include <asm/arch/power.h> 11#include <asm/arch/clock.h> 12#include <asm/arch/gpio.h> 13#include <asm/global_data.h> 14#include <asm/gpio.h> 15#include <asm/arch/cpu.h> 16#include <dm.h> 17#include <env.h> 18#include <linux/printk.h> 19#include <power/pmic.h> 20#include <power/regulator.h> 21#include <power/max77686_pmic.h> 22#include <errno.h> 23#include <mmc.h> 24#include <usb.h> 25#include <usb/dwc2_udc.h> 26#include <samsung/misc.h> 27#include "setup.h" 28 29DECLARE_GLOBAL_DATA_PTR; 30 31#ifdef CONFIG_BOARD_TYPES 32/* Odroid board types */ 33enum { 34 ODROID_TYPE_U3, 35 ODROID_TYPE_X2, 36 ODROID_TYPES, 37}; 38 39void set_board_type(void) 40{ 41 /* Set GPA1 pin 1 to HI - enable XCL205 output */ 42 writel(XCL205_EN_GPIO_CON_CFG, XCL205_EN_GPIO_CON); 43 writel(XCL205_EN_GPIO_DAT_CFG, XCL205_EN_GPIO_CON + 0x4); 44 writel(XCL205_EN_GPIO_PUD_CFG, XCL205_EN_GPIO_CON + 0x8); 45 writel(XCL205_EN_GPIO_DRV_CFG, XCL205_EN_GPIO_CON + 0xc); 46 47 /* Set GPC1 pin 2 to IN - check XCL205 output state */ 48 writel(XCL205_STATE_GPIO_CON_CFG, XCL205_STATE_GPIO_CON); 49 writel(XCL205_STATE_GPIO_PUD_CFG, XCL205_STATE_GPIO_CON + 0x8); 50 51 /* XCL205 - needs some latch time */ 52 sdelay(200000); 53 54 /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */ 55 if (readl(XCL205_STATE_GPIO_DAT) & (1 << XCL205_STATE_GPIO_PIN)) 56 gd->board_type = ODROID_TYPE_X2; 57 else 58 gd->board_type = ODROID_TYPE_U3; 59} 60 61void set_board_revision(void) 62{ 63 /* 64 * Revision already set by set_board_type() because it can be 65 * executed early. 66 */ 67} 68 69const char *get_board_type(void) 70{ 71 const char *board_type[] = {"u3", "x2"}; 72 73 return board_type[gd->board_type]; 74} 75#endif 76 77#ifdef CONFIG_SET_DFU_ALT_INFO 78char *get_dfu_alt_system(char *interface, char *devstr) 79{ 80 return env_get("dfu_alt_system"); 81} 82 83char *get_dfu_alt_boot(char *interface, char *devstr) 84{ 85 struct mmc *mmc; 86 char *alt_boot; 87 int dev_num; 88 89 dev_num = dectoul(devstr, NULL); 90 91 mmc = find_mmc_device(dev_num); 92 if (!mmc) 93 return NULL; 94 95 if (mmc_init(mmc)) 96 return NULL; 97 98 alt_boot = IS_SD(mmc) ? CFG_DFU_ALT_BOOT_SD : 99 CFG_DFU_ALT_BOOT_EMMC; 100 101 return alt_boot; 102} 103#endif 104 105static void board_clock_init(void) 106{ 107 unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc; 108 struct exynos4x12_clock *clk = (struct exynos4x12_clock *) 109 samsung_get_base_clock(); 110 111 /* 112 * CMU_CPU clocks src to MPLL 113 * Bit values: 0 ; 1 114 * MUX_APLL_SEL: FIN_PLL ; FOUT_APLL 115 * MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL 116 * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C 117 * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL 118 */ 119 clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1) | 120 MUX_HPM_SEL(1) | MUX_MPLL_USER_SEL_C(1); 121 set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) | 122 MUX_MPLL_USER_SEL_C(1); 123 124 clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); 125 126 /* Wait for mux change */ 127 while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING) 128 continue; 129 130 /* Set APLL to 1000MHz */ 131 clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1); 132 set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1); 133 134 clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set); 135 136 /* Wait for PLL to be locked */ 137 while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT)) 138 continue; 139 140 /* Set CMU_CPU clocks src to APLL */ 141 set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) | 142 MUX_MPLL_USER_SEL_C(1); 143 clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); 144 145 /* Wait for mux change */ 146 while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING) 147 continue; 148 149 set = CORE_RATIO(0) | COREM0_RATIO(2) | COREM1_RATIO(5) | 150 PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) | 151 APLL_RATIO(0) | CORE2_RATIO(0); 152 /* 153 * Set dividers for MOUTcore = 1000 MHz 154 * coreout = MOUT / (ratio + 1) = 1000 MHz (0) 155 * corem0 = armclk / (ratio + 1) = 333 MHz (2) 156 * corem1 = armclk / (ratio + 1) = 166 MHz (5) 157 * periph = armclk / (ratio + 1) = 1000 MHz (0) 158 * atbout = MOUT / (ratio + 1) = 200 MHz (4) 159 * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1) 160 * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0) 161 * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk) 162 */ 163 clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) | 164 PERIPH_RATIO(7) | ATB_RATIO(7) | PCLK_DBG_RATIO(7) | 165 APLL_RATIO(7) | CORE2_RATIO(7); 166 167 clrsetbits_le32(&clk->div_cpu0, clr, set); 168 169 /* Wait for divider ready status */ 170 while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING) 171 continue; 172 173 /* 174 * For MOUThpm = 1000 MHz (MOUTapll) 175 * doutcopy = MOUThpm / (ratio + 1) = 200 (4) 176 * sclkhpm = doutcopy / (ratio + 1) = 200 (4) 177 * cores_out = armclk / (ratio + 1) = 200 (4) 178 */ 179 clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7); 180 set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(4); 181 182 clrsetbits_le32(&clk->div_cpu1, clr, set); 183 184 /* Wait for divider ready status */ 185 while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING) 186 continue; 187 188 /* 189 * Set CMU_DMC clocks src to APLL 190 * Bit values: 0 ; 1 191 * MUX_C2C_SEL: SCLKMPLL ; SCLKAPLL 192 * MUX_DMC_BUS_SEL: SCLKMPLL ; SCLKAPLL 193 * MUX_DPHY_SEL: SCLKMPLL ; SCLKAPLL 194 * MUX_MPLL_SEL: FINPLL ; MOUT_MPLL_FOUT 195 * MUX_PWI_SEL: 0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI) 196 * MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL 197 * MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL 198 * MUX_G2D_ACP_SEL: OUT_ACP0 ; OUT_ACP1 199 */ 200 clr_src_dmc = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | 201 MUX_DPHY_SEL(1) | MUX_MPLL_SEL(1) | 202 MUX_PWI_SEL(15) | MUX_G2D_ACP0_SEL(1) | 203 MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1); 204 set = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | MUX_DPHY_SEL(1) | 205 MUX_MPLL_SEL(0) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(1) | 206 MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1); 207 208 clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set); 209 210 /* Wait for mux change */ 211 while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING) 212 continue; 213 214 /* Set MPLL to 800MHz */ 215 set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1); 216 217 clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set); 218 219 /* Wait for PLL to be locked */ 220 while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT)) 221 continue; 222 223 /* Switch back CMU_DMC mux */ 224 set = MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) | 225 MUX_MPLL_SEL(1) | MUX_PWI_SEL(8) | MUX_G2D_ACP0_SEL(0) | 226 MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0); 227 228 clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set); 229 230 /* Wait for mux change */ 231 while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING) 232 continue; 233 234 /* CLK_DIV_DMC0 */ 235 clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) | 236 DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7); 237 /* 238 * For: 239 * MOUTdmc = 800 MHz 240 * MOUTdphy = 800 MHz 241 * 242 * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3) 243 * pclk_acp = aclk_acp / (ratio + 1) = 100 (1) 244 * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1) 245 * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1) 246 * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1) 247 * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1) 248 */ 249 set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) | 250 DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1); 251 252 clrsetbits_le32(&clk->div_dmc0, clr, set); 253 254 /* Wait for divider ready status */ 255 while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING) 256 continue; 257 258 /* CLK_DIV_DMC1 */ 259 clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) | 260 C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127); 261 /* 262 * For: 263 * MOUTg2d = 800 MHz 264 * MOUTc2c = 800 Mhz 265 * MOUTpwi = 108 MHz 266 * 267 * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 200 (3) 268 * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1) 269 * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1) 270 * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5) 271 */ 272 set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(5) | 273 C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1); 274 275 clrsetbits_le32(&clk->div_dmc1, clr, set); 276 277 /* Wait for divider ready status */ 278 while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING) 279 continue; 280 281 /* CLK_SRC_PERIL0 */ 282 clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) | 283 UART3_SEL(15) | UART4_SEL(15); 284 /* 285 * Set CLK_SRC_PERIL0 clocks src to MPLL 286 * src values: 0(XXTI); 1(XusbXTI); 2(SCLK_HDMI24M); 3(SCLK_USBPHY0); 287 * 5(SCLK_HDMIPHY); 6(SCLK_MPLL_USER_T); 7(SCLK_EPLL); 288 * 8(SCLK_VPLL) 289 * 290 * Set all to SCLK_MPLL_USER_T 291 */ 292 set = UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) | UART3_SEL(6) | 293 UART4_SEL(6); 294 295 clrsetbits_le32(&clk->src_peril0, clr, set); 296 297 /* CLK_DIV_PERIL0 */ 298 clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) | 299 UART3_RATIO(15) | UART4_RATIO(15); 300 /* 301 * For MOUTuart0-4: 800MHz 302 * 303 * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7) 304 */ 305 set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) | 306 UART3_RATIO(7) | UART4_RATIO(7); 307 308 clrsetbits_le32(&clk->div_peril0, clr, set); 309 310 while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING) 311 continue; 312 313 /* CLK_DIV_FSYS1 */ 314 clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) | 315 MMC1_PRE_RATIO(255); 316 /* 317 * For MOUTmmc0-3 = 800 MHz (MPLL) 318 * 319 * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7) 320 * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1) 321 * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7) 322 * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1) 323 */ 324 set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) | 325 MMC1_PRE_RATIO(1); 326 327 clrsetbits_le32(&clk->div_fsys1, clr, set); 328 329 /* Wait for divider ready status */ 330 while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING) 331 continue; 332 333 /* CLK_DIV_FSYS2 */ 334 clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) | 335 MMC3_PRE_RATIO(255); 336 /* 337 * For MOUTmmc0-3 = 800 MHz (MPLL) 338 * 339 * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7) 340 * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1) 341 * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7) 342 * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1) 343 */ 344 set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) | 345 MMC3_PRE_RATIO(1); 346 347 clrsetbits_le32(&clk->div_fsys2, clr, set); 348 349 /* Wait for divider ready status */ 350 while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING) 351 continue; 352 353 /* CLK_DIV_FSYS3 */ 354 clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255); 355 /* 356 * For MOUTmmc4 = 800 MHz (MPLL) 357 * 358 * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7) 359 * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0) 360 */ 361 set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0); 362 363 clrsetbits_le32(&clk->div_fsys3, clr, set); 364 365 /* Wait for divider ready status */ 366 while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING) 367 continue; 368 369 return; 370} 371 372static void board_gpio_init(void) 373{ 374 /* eMMC Reset Pin */ 375 gpio_request(EXYNOS4X12_GPIO_K12, "eMMC Reset"); 376 377 gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1)); 378 gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE); 379 gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X); 380 381 /* Enable FAN (Odroid U3) */ 382 gpio_request(EXYNOS4X12_GPIO_D00, "FAN Control"); 383 384 gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP); 385 gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X); 386 gpio_direction_output(EXYNOS4X12_GPIO_D00, 1); 387 388 /* OTG Vbus output (Odroid U3+) */ 389 gpio_request(EXYNOS4X12_GPIO_L20, "OTG Vbus"); 390 391 gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE); 392 gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X); 393 gpio_direction_output(EXYNOS4X12_GPIO_L20, 0); 394 395 /* OTG INT (Odroid U3+) */ 396 gpio_request(EXYNOS4X12_GPIO_X31, "OTG INT"); 397 398 gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP); 399 gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X); 400 gpio_direction_input(EXYNOS4X12_GPIO_X31); 401 402 /* Blue LED (Odroid X2/U2/U3) */ 403 gpio_request(EXYNOS4X12_GPIO_C10, "Blue LED"); 404 405 gpio_direction_output(EXYNOS4X12_GPIO_C10, 0); 406 407#ifdef CONFIG_CMD_USB 408 /* USB3503A Reference frequency */ 409 gpio_request(EXYNOS4X12_GPIO_X30, "USB3503A RefFreq"); 410 411 /* USB3503A Connect */ 412 gpio_request(EXYNOS4X12_GPIO_X34, "USB3503A Connect"); 413 414 /* USB3503A Reset */ 415 gpio_request(EXYNOS4X12_GPIO_X35, "USB3503A Reset"); 416#endif 417} 418 419int exynos_early_init_f(void) 420{ 421 board_clock_init(); 422 423 return 0; 424} 425 426void exynos_init(void) 427{ 428 board_gpio_init(); 429} 430 431int exynos_power_init(void) 432{ 433 const char *mmc_regulators[] = { 434 "VDDQ_EMMC_1.8V", 435 "VDDQ_EMMC_2.8V", 436 "TFLASH_2.8V", 437 NULL, 438 }; 439 440 if (regulator_list_autoset(mmc_regulators, NULL, true)) 441 pr_err("Unable to init all mmc regulators\n"); 442 443 return 0; 444} 445 446#ifdef CONFIG_USB_GADGET 447static int s5pc210_phy_control(int on) 448{ 449 struct udevice *dev; 450 int ret; 451 452 ret = regulator_get_by_platname("VDD_UOTG_3.0V", &dev); 453 if (ret) { 454 pr_err("Regulator get error: %d\n", ret); 455 return ret; 456 } 457 458 if (on) 459 return regulator_set_mode(dev, OPMODE_ON); 460 else 461 return regulator_set_mode(dev, OPMODE_LPM); 462} 463 464struct dwc2_plat_otg_data s5pc210_otg_data = { 465 .phy_control = s5pc210_phy_control, 466 .regs_phy = EXYNOS4X12_USBPHY_BASE, 467 .regs_otg = EXYNOS4X12_USBOTG_BASE, 468 .usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL, 469 .usb_flags = PHY0_SLEEP, 470}; 471#endif 472 473#if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB) 474 475static void set_usb3503_ref_clk(void) 476{ 477#ifdef CONFIG_BOARD_TYPES 478 /* 479 * gpx3-0 chooses primary (low) or secondary (high) reference clock 480 * frequencies table. The choice of clock is done through hard-wired 481 * REF_SEL pins. 482 * The Odroid Us have reference clock at 24 MHz (00 entry from secondary 483 * table) and Odroid Xs have it at 26 MHz (01 entry from primary table). 484 */ 485 if (gd->board_type == ODROID_TYPE_U3) 486 gpio_direction_output(EXYNOS4X12_GPIO_X30, 0); 487 else 488 gpio_direction_output(EXYNOS4X12_GPIO_X30, 1); 489#else 490 /* Choose Odroid Xs frequency without board types */ 491 gpio_direction_output(EXYNOS4X12_GPIO_X30, 1); 492#endif /* CONFIG_BOARD_TYPES */ 493} 494 495int board_usb_init(int index, enum usb_init_type init) 496{ 497#ifdef CONFIG_CMD_USB 498 struct udevice *dev; 499 int ret; 500 501 set_usb3503_ref_clk(); 502 503 /* Disconnect, Reset, Connect */ 504 gpio_direction_output(EXYNOS4X12_GPIO_X34, 0); 505 gpio_direction_output(EXYNOS4X12_GPIO_X35, 0); 506 gpio_direction_output(EXYNOS4X12_GPIO_X35, 1); 507 gpio_direction_output(EXYNOS4X12_GPIO_X34, 1); 508 509 /* Power off and on BUCK8 for LAN9730 */ 510 debug("LAN9730 - Turning power buck 8 OFF and ON.\n"); 511 512 ret = regulator_get_by_platname("VCC_P3V3_2.85V", &dev); 513 if (ret) { 514 pr_err("Regulator get error: %d\n", ret); 515 return ret; 516 } 517 518 ret = regulator_set_enable(dev, true); 519 if (ret) { 520 pr_err("Regulator %s enable setting error: %d\n", dev->name, ret); 521 return ret; 522 } 523 524 ret = regulator_set_value(dev, 750000); 525 if (ret) { 526 pr_err("Regulator %s value setting error: %d\n", dev->name, ret); 527 return ret; 528 } 529 530 ret = regulator_set_value(dev, 3300000); 531 if (ret) { 532 pr_err("Regulator %s value setting error: %d\n", dev->name, ret); 533 return ret; 534 } 535#endif 536 debug("USB_udc_probe\n"); 537 return dwc2_udc_probe(&s5pc210_otg_data); 538} 539#endif 540