1// SPDX-License-Identifier: GPL-2.0 2/* 3 * board/renesas/lager/lager_spl.c 4 * 5 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> 6 */ 7 8#include <cpu_func.h> 9#include <init.h> 10#include <malloc.h> 11#include <dm/platform_data/serial_sh.h> 12#include <asm/processor.h> 13#include <asm/mach-types.h> 14#include <asm/io.h> 15#include <linux/bitops.h> 16#include <linux/errno.h> 17#include <asm/arch/sys_proto.h> 18#include <asm/gpio.h> 19#include <asm/arch/renesas.h> 20#include <asm/arch/rcar-mstp.h> 21 22#include <spl.h> 23 24#define TMU0_MSTP125 BIT(25) 25#define SCIF0_MSTP721 BIT(21) 26#define QSPI_MSTP917 BIT(17) 27 28#define SD2CKCR 0xE615026C 29#define SD_97500KHZ 0x7 30 31struct reg_config { 32 u16 off; 33 u32 val; 34}; 35 36static void dbsc_wait(u16 reg) 37{ 38 static const u32 dbsc3_0_base = DBSC3_0_BASE; 39 40 while (!(readl(dbsc3_0_base + reg) & BIT(0))) 41 ; 42} 43 44static void spl_init_sys(void) 45{ 46 u32 r0 = 0; 47 48 writel(0xa5a5a500, 0xe6020004); 49 writel(0xa5a5a500, 0xe6030004); 50 51 asm volatile( 52 /* ICIALLU - Invalidate I$ to PoU */ 53 "mcr 15, 0, %0, cr7, cr5, 0 \n" 54 /* BPIALL - Invalidate branch predictors */ 55 "mcr 15, 0, %0, cr7, cr5, 6 \n" 56 /* Set SCTLR[IZ] */ 57 "mrc 15, 0, %0, cr1, cr0, 0 \n" 58 "orr %0, #0x1800 \n" 59 "mcr 15, 0, %0, cr1, cr0, 0 \n" 60 "isb sy \n" 61 :"=r"(r0)); 62} 63 64static void spl_init_pfc(void) 65{ 66 static const struct reg_config pfc_with_unlock[] = { 67 { 0x0090, 0x00000000 }, 68 { 0x0094, 0x00000000 }, 69 { 0x0098, 0xc0000000 }, 70 { 0x0020, 0x00000000 }, 71 { 0x0024, 0x00000000 }, 72 { 0x0028, 0x00000000 }, 73 { 0x002c, 0x20000000 }, 74 { 0x0030, 0x00001249 }, 75 { 0x0034, 0x00000278 }, 76 { 0x0038, 0x00000841 }, 77 { 0x003c, 0x00000000 }, 78 { 0x0040, 0x00000000 }, 79 { 0x0044, 0x10000000 }, 80 { 0x0048, 0x00000001 }, 81 { 0x004c, 0x0004aab0 }, 82 { 0x0050, 0x37301b00 }, 83 { 0x0054, 0x00048da3 }, 84 { 0x0058, 0x089044a1 }, 85 { 0x005c, 0x2a3a55b4 }, 86 { 0x0160, 0x00000003 }, 87 { 0x0004, 0xffffffff }, 88 { 0x0008, 0x2aef3fff }, 89 { 0x000c, 0x3fffffff }, 90 { 0x0010, 0xff7fc07f }, 91 { 0x0014, 0x7f3ff3f8 }, 92 { 0x0018, 0x1cfdfff7 }, 93 }; 94 95 static const struct reg_config pfc_without_unlock[] = { 96 { 0x0100, 0x1fffffff }, 97 { 0x0104, 0xffff0318 }, 98 { 0x0108, 0x387fffe1 }, 99 { 0x010c, 0x00803f80 }, 100 { 0x0110, 0x1520009f }, 101 { 0x0114, 0x00000000 }, 102 { 0x0118, 0x00000000 }, 103 }; 104 105 static const u32 pfc_base = 0xe6060000; 106 107 unsigned int i; 108 109 for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) { 110 writel(~pfc_with_unlock[i].val, pfc_base); 111 writel(pfc_with_unlock[i].val, 112 pfc_base | pfc_with_unlock[i].off); 113 } 114 115 for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++) 116 writel(pfc_without_unlock[i].val, 117 pfc_base | pfc_without_unlock[i].off); 118} 119 120static void spl_init_gpio(void) 121{ 122 static const u16 gpio_offs[] = { 123 0x1000, 0x3000, 0x4000, 0x5000 124 }; 125 126 static const struct reg_config gpio_set[] = { 127 { 0x4000, 0x00c00000 }, 128 { 0x5000, 0x63020000 }, 129 }; 130 131 static const struct reg_config gpio_clr[] = { 132 { 0x1000, 0x00000000 }, 133 { 0x3000, 0x00000000 }, 134 { 0x4000, 0x00c00000 }, 135 { 0x5000, 0xe3020000 }, 136 }; 137 138 static const u32 gpio_base = 0xe6050000; 139 140 unsigned int i; 141 142 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) 143 writel(0, gpio_base | 0x20 | gpio_offs[i]); 144 145 for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) 146 writel(0, gpio_base | 0x00 | gpio_offs[i]); 147 148 for (i = 0; i < ARRAY_SIZE(gpio_set); i++) 149 writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off); 150 151 for (i = 0; i < ARRAY_SIZE(gpio_clr); i++) 152 writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off); 153} 154 155static void spl_init_lbsc(void) 156{ 157 static const struct reg_config lbsc_config[] = { 158 { 0x00, 0x00000020 }, 159 { 0x08, 0x00002020 }, 160 { 0x30, 0x02150326 }, 161 { 0x38, 0x077f077f }, 162 }; 163 164 static const u16 lbsc_offs[] = { 165 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180 166 }; 167 168 static const u32 lbsc_base = 0xfec00200; 169 170 unsigned int i; 171 172 for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) { 173 writel(lbsc_config[i].val, 174 lbsc_base | lbsc_config[i].off); 175 writel(lbsc_config[i].val, 176 lbsc_base | (lbsc_config[i].off + 4)); 177 } 178 179 for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++) 180 writel(0, lbsc_base | lbsc_offs[i]); 181} 182 183static void spl_init_dbsc(void) 184{ 185 static const struct reg_config dbsc_config1[] = { 186 { 0x0018, 0x21000000 }, 187 { 0x0018, 0x11000000 }, 188 { 0x0018, 0x10000000 }, 189 { 0x0280, 0x0000a55a }, 190 { 0x0290, 0x00000001 }, 191 { 0x02a0, 0x80000000 }, 192 { 0x0290, 0x00000004 }, 193 }; 194 195 static const struct reg_config dbsc_config4[] = { 196 { 0x0290, 0x00000010 }, 197 { 0x02a0, 0xf004649b }, 198 { 0x0290, 0x0000000f }, 199 { 0x02a0, 0x00181ee4 }, 200 { 0x0290, 0x00000060 }, 201 { 0x02a0, 0x330657b2 }, 202 { 0x0290, 0x00000001 }, 203 { 0x02a0, 0x00000071 }, 204 { 0x0020, 0x00000007 }, 205 { 0x0024, 0x10030a02 }, 206 { 0x0030, 0x00000001 }, 207 { 0x00b0, 0x00000000 }, 208 { 0x0040, 0x0000000b }, 209 { 0x0044, 0x00000008 }, 210 { 0x0048, 0x00000000 }, 211 { 0x0050, 0x0000000b }, 212 { 0x0054, 0x000c000b }, 213 { 0x0058, 0x00000027 }, 214 { 0x005c, 0x0000001c }, 215 { 0x0060, 0x00000005 }, 216 { 0x0064, 0x00000018 }, 217 { 0x0068, 0x00000008 }, 218 { 0x006c, 0x0000000c }, 219 { 0x0070, 0x00000009 }, 220 { 0x0074, 0x00000012 }, 221 { 0x0078, 0x000000d0 }, 222 { 0x007c, 0x00140005 }, 223 { 0x0080, 0x00050004 }, 224 { 0x0084, 0x70233005 }, 225 { 0x0088, 0x000c0000 }, 226 { 0x008c, 0x00000300 }, 227 { 0x0090, 0x00000040 }, 228 { 0x0100, 0x00000001 }, 229 { 0x00c0, 0x00020001 }, 230 { 0x00c8, 0x20082008 }, 231 { 0x0380, 0x00020002 }, 232 { 0x0390, 0x0000000f }, 233 }; 234 235 static const struct reg_config dbsc_config5[] = { 236 { 0x0244, 0x00000011 }, 237 { 0x0290, 0x00000006 }, 238 { 0x02a0, 0x0005c000 }, 239 { 0x0290, 0x00000003 }, 240 { 0x02a0, 0x0300c481 }, 241 { 0x0290, 0x00000023 }, 242 { 0x02a0, 0x00fdb6c0 }, 243 { 0x0290, 0x00000011 }, 244 { 0x02a0, 0x1000040b }, 245 { 0x0290, 0x00000012 }, 246 { 0x02a0, 0x9d5cbb66 }, 247 { 0x0290, 0x00000013 }, 248 { 0x02a0, 0x1a868300 }, 249 { 0x0290, 0x00000014 }, 250 { 0x02a0, 0x300214d8 }, 251 { 0x0290, 0x00000015 }, 252 { 0x02a0, 0x00000d70 }, 253 { 0x0290, 0x00000016 }, 254 { 0x02a0, 0x00000006 }, 255 { 0x0290, 0x00000017 }, 256 { 0x02a0, 0x00000018 }, 257 { 0x0290, 0x0000001a }, 258 { 0x02a0, 0x910035c7 }, 259 { 0x0290, 0x00000004 }, 260 }; 261 262 static const struct reg_config dbsc_config6[] = { 263 { 0x0290, 0x00000001 }, 264 { 0x02a0, 0x00000181 }, 265 { 0x0018, 0x11000000 }, 266 { 0x0290, 0x00000004 }, 267 }; 268 269 static const struct reg_config dbsc_config7[] = { 270 { 0x0290, 0x00000001 }, 271 { 0x02a0, 0x0000fe01 }, 272 { 0x0290, 0x00000004 }, 273 }; 274 275 static const struct reg_config dbsc_config8[] = { 276 { 0x0304, 0x00000000 }, 277 { 0x00f4, 0x01004c20 }, 278 { 0x00f8, 0x014000aa }, 279 { 0x00e0, 0x00000140 }, 280 { 0x00e4, 0x00081860 }, 281 { 0x00e8, 0x00010000 }, 282 { 0x0014, 0x00000001 }, 283 { 0x0010, 0x00000001 }, 284 { 0x0280, 0x00000000 }, 285 }; 286 287 static const u32 dbsc3_0_base = DBSC3_0_BASE; 288 unsigned int i; 289 290 for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) 291 writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off); 292 293 dbsc_wait(0x2a0); 294 295 for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) 296 writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off); 297 298 dbsc_wait(0x240); 299 300 for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) 301 writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off); 302 303 dbsc_wait(0x2a0); 304 305 for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) 306 writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off); 307 308 dbsc_wait(0x2a0); 309 310 for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) 311 writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off); 312 313 dbsc_wait(0x2a0); 314 315 for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) 316 writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off); 317 318} 319 320static void spl_init_qspi(void) 321{ 322 mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917); 323 324 static const u32 qspi_base = 0xe6b10000; 325 326 writeb(0x08, qspi_base + 0x00); 327 writeb(0x00, qspi_base + 0x01); 328 writeb(0x06, qspi_base + 0x02); 329 writeb(0x01, qspi_base + 0x0a); 330 writeb(0x00, qspi_base + 0x0b); 331 writeb(0x00, qspi_base + 0x0c); 332 writeb(0x00, qspi_base + 0x0d); 333 writeb(0x00, qspi_base + 0x0e); 334 335 writew(0xe080, qspi_base + 0x10); 336 337 writeb(0xc0, qspi_base + 0x18); 338 writeb(0x00, qspi_base + 0x18); 339 writeb(0x00, qspi_base + 0x08); 340 writeb(0x48, qspi_base + 0x00); 341} 342 343void board_init_f(ulong dummy) 344{ 345 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 346 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); 347 348 /* 349 * SD0 clock is set to 97.5MHz by default. 350 * Set SD2 to the 97.5MHz as well. 351 */ 352 writel(SD_97500KHZ, SD2CKCR); 353 354 spl_init_sys(); 355 spl_init_pfc(); 356 spl_init_gpio(); 357 spl_init_lbsc(); 358 spl_init_dbsc(); 359 spl_init_qspi(); 360} 361 362void spl_board_init(void) 363{ 364 /* UART clocks enabled and gd valid - init serial console */ 365 preloader_console_init(); 366} 367 368void board_boot_order(u32 *spl_boot_list) 369{ 370 const u32 jtag_magic = 0x1337c0de; 371 const u32 load_magic = 0xb33fc0de; 372 373 /* 374 * If JTAG probe sets special word at 0xe6300020, then it must 375 * put U-Boot into RAM and SPL will start it from RAM. 376 */ 377 if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) { 378 printf("JTAG boot detected!\n"); 379 380 while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic) 381 ; 382 383 spl_boot_list[0] = BOOT_DEVICE_RAM; 384 spl_boot_list[1] = BOOT_DEVICE_NONE; 385 386 return; 387 } 388 389 /* Boot from SPI NOR with YMODEM UART fallback. */ 390 spl_boot_list[0] = BOOT_DEVICE_SPI; 391 spl_boot_list[1] = BOOT_DEVICE_UART; 392 spl_boot_list[2] = BOOT_DEVICE_NONE; 393} 394 395void reset_cpu(void) 396{ 397} 398