1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2023, Phytium Technology Co., Ltd.
4 * lixinde          <lixinde@phytium.com.cn>
5 * weichangzheng    <weichangzheng@phytium.com.cn>
6 */
7
8#ifndef _FT_PE2201_H
9#define _FT_PE2201_H
10
11/* SMCCC ID */
12#define CPU_SVC_VERSION             0xC2000F00
13#define CPU_GET_RST_SOURCE          0xC2000F01
14#define CPU_INIT_PLL                0xC2000F02
15#define CPU_INIT_PCIE               0xC2000F03
16#define CPU_INIT_MEM                0xC2000F04
17#define CPU_INIT_SEC_SVC            0xC2000F05
18
19/* CPU RESET */
20#define CPU_RESET_POWER_ON          0x1
21#define CPU_RESET_PLL               0x4
22#define CPU_RESET_WATCH_DOG         0x8
23
24/* PLL */
25#define PARAMETER_PLL_MAGIC         0x54460020
26
27/* PCIE */
28#define PARAMETER_PCIE_MAGIC        0x54460021
29#define CFG_INDEPENDENT_TREE        0x0
30#define PCI_PEU0                    0x1
31#define PCI_PEU1                    0x1
32#define PEU1_OFFSET                 16
33#define PEU_C_OFFSET_MODE           16
34#define PEU_C_OFFSET_SPEED          0
35#define X1X1X1X1                    0x2
36#define X1X1                        0x0
37#define EP_MODE                     0x0
38#define RC_MODE                     0x1
39#define GEN3                        3
40
41/* DDR */
42#define PARAMETER_MCU_MAGIC         0x54460024
43#define PARAM_MCU_VERSION           0x3
44#define PARAM_MCU_SIZE              0x100
45#define PARAM_CH_ENABLE             0x1
46
47#define RDIMM_TYPE                  0x1
48#define UDIMM_TYPE                  0x2
49#define LPDDR4_TYPE                 0x10
50#define DIMM_X8                     0x1
51#define DIMM_X16                    0x2
52#define NO_MIRROR                   0x0
53#define NO_ECC_TYPE                 0
54#define DDR4_TYPE                   0xC
55
56/* SEC */
57#define PARAMETER_COMMON_MAGIC      0x54460013
58
59void ddr_init(void);
60void sec_init(void);
61void check_reset(void);
62void pcie_init(void);
63
64#endif /* _FT_PE2201_H */
65