1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (C) 2021 Oleh Kravchenko <oleg@kaa.org.ua>
3
4#include <asm/arch-mx6/clock.h>
5#include <asm/arch/sys_proto.h>
6#include <asm/global_data.h>
7#include <asm/mach-imx/boot_mode.h>
8#include <common.h>
9#include <env.h>
10
11DECLARE_GLOBAL_DATA_PTR;
12
13int dram_init(void)
14{
15	gd->ram_size = imx_ddr_size();
16
17	return 0;
18}
19
20int board_early_init_f(void)
21{
22	return 0;
23}
24
25static int setup_fec_clock(void)
26{
27	if (IS_ENABLED(CONFIG_FEC_MXC) && !IS_ENABLED(CONFIG_CLK_IMX6Q)) {
28		struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
29		int ret;
30
31		/*
32		 * Use 50M anatop loopback REF_CLK1 for ENET1,
33		 * clear gpr1[13], set gpr1[17].
34		 */
35		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
36				IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
37
38		ret = enable_fec_anatop_clock(0, ENET_50MHZ);
39		if (ret)
40			return ret;
41
42		if (!IS_ENABLED(CONFIG_EV_IMX280_NANO_X_MB)) {
43			/*
44			 * Use 50M anatop loopback REF_CLK2 for ENET2,
45			 * clear gpr1[14], set gpr1[18].
46			 */
47			clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
48					IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
49
50			ret = enable_fec_anatop_clock(1, ENET_50MHZ);
51			if (ret)
52				return ret;
53		}
54
55		enable_enet_clk(1);
56	}
57
58	return 0;
59}
60
61int board_init(void)
62{
63	/* Address of boot parameters */
64	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
65
66	return setup_fec_clock();
67}
68
69int board_late_init(void)
70{
71	if (IS_ENABLED(CONFIG_CMD_BMODE))
72		add_board_boot_modes(NULL);
73
74	if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
75		const char *model;
76
77		model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
78		if (model)
79			env_set("board_name", model);
80	}
81
82	if (is_boot_from_usb()) {
83		env_set("bootcmd", "run bootcmd_mfg");
84		env_set("bootdelay", "0");
85	}
86
87	return 0;
88}
89