1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2013
4 * NVIDIA Corporation <www.nvidia.com>
5 */
6
7#include <common.h>
8#include <log.h>
9#include <asm/io.h>
10#include <asm/arch-tegra/tegra_i2c.h>
11#include <linux/delay.h>
12
13/* AS3722-PMIC-specific early init regs */
14
15#define AS3722_I2C_ADDR		0x80
16
17#define AS3722_SD0VOLTAGE_REG	0x00	/* CPU */
18#define AS3722_SD1VOLTAGE_REG	0x01	/* CORE, already set by OTP */
19#define AS3722_SD6VOLTAGE_REG	0x06	/* GPU */
20#define AS3722_SDCONTROL_REG	0x4D
21
22#define AS3722_LDO2VOLTAGE_REG	0x12	/* VPP_FUSE */
23#define AS3722_LDO6VOLTAGE_REG	0x16	/* VDD_SDMMC */
24#define AS3722_LDCONTROL_REG	0x4E
25
26#if defined(CONFIG_TARGET_VENICE2)
27#define AS3722_SD0VOLTAGE_DATA	(0x2800 | AS3722_SD0VOLTAGE_REG)
28#else /* TK1 or Nyan-Big */
29#define AS3722_SD0VOLTAGE_DATA	(0x3C00 | AS3722_SD0VOLTAGE_REG)
30#endif
31#define AS3722_SD0CONTROL_DATA	(0x0100 | AS3722_SDCONTROL_REG)
32
33#if defined(CONFIG_TARGET_JETSON_TK1) || defined(CONFIG_TARGET_CEI_TK1_SOM)
34#define AS3722_SD1VOLTAGE_DATA	(0x2800 | AS3722_SD1VOLTAGE_REG)
35#define AS3722_SD1CONTROL_DATA	(0x0200 | AS3722_SDCONTROL_REG)
36#endif
37
38#define AS3722_SD6CONTROL_DATA	(0x4000 | AS3722_SDCONTROL_REG)
39#define AS3722_SD6VOLTAGE_DATA	(0x2800 | AS3722_SD6VOLTAGE_REG)
40
41#define AS3722_LDO2CONTROL_DATA	(0x0400 | AS3722_LDCONTROL_REG)
42#define AS3722_LDO2VOLTAGE_DATA	(0x1000 | AS3722_LDO2VOLTAGE_REG)
43
44#define AS3722_LDO6CONTROL_DATA	(0x4000 | AS3722_LDCONTROL_REG)
45#define AS3722_LDO6VOLTAGE_DATA	(0x3F00 | AS3722_LDO6VOLTAGE_REG)
46
47/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
48
49void pmic_enable_cpu_vdd(void)
50{
51	debug("%s entry\n", __func__);
52
53#ifdef AS3722_SD1VOLTAGE_DATA
54	/* Set up VDD_CORE, for boards where OTP is incorrect*/
55	debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
56	/* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
57	tegra_i2c_ll_write(AS3722_I2C_ADDR,
58			   AS3722_SD1VOLTAGE_DATA);
59	/*
60	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
61	 * tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
62	 */
63	udelay(10 * 1000);
64#endif
65
66	debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
67	/*
68	 * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
69	 * First set VDD to 1.0V, then enable the VDD regulator.
70	 */
71	tegra_i2c_ll_write(AS3722_I2C_ADDR,
72			   AS3722_SD0VOLTAGE_DATA);
73	/*
74	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
75	 * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
76	 */
77	udelay(10 * 1000);
78
79	debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
80	/*
81	 * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
82	 * First set VDD to 1.0V, then enable the VDD regulator.
83	 */
84	tegra_i2c_ll_write(AS3722_I2C_ADDR,
85			   AS3722_SD6VOLTAGE_DATA);
86	/*
87	 * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
88	 * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
89	 */
90	udelay(10 * 1000);
91
92	debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
93	/*
94	 * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
95	 * First set VDD to 1.2V, then enable the VDD regulator.
96	 */
97	tegra_i2c_ll_write(AS3722_I2C_ADDR,
98			   AS3722_LDO2VOLTAGE_DATA);
99	/*
100	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
101	 * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
102	 */
103	udelay(10 * 1000);
104
105	debug("%s: Set VDD_SDMMC to 3.3V via AS3722 reg 0x16/4E\n", __func__);
106	/*
107	 * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
108	 * First set it to bypass 3.3V straight thru, then enable the regulator
109	 *
110	 * NOTE: We do this early because doing it later seems to hose the CPU
111	 * power rail/partition startup. Need to debug.
112	 */
113	tegra_i2c_ll_write(AS3722_I2C_ADDR,
114			   AS3722_LDO6VOLTAGE_DATA);
115	/*
116	 * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
117	 * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
118	 */
119	udelay(10 * 1000);
120}
121