1/*
2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier:	GPL-2.0+
5 *
6 * Refer docs/README.imxmage for more details about how-to configure
7 * and create imximage boot image
8 *
9 * The syntax is taken as close as possible with the kwbimage
10 */
11
12#include <config.h>
13
14/* image version */
15
16IMAGE_VERSION 2
17
18/*
19 * Boot Device : sd
20 */
21
22BOOT_FROM	sd
23
24/*
25 * Secure boot support
26 */
27#ifdef CONFIG_IMX_HAB
28CSF CONFIG_CSF_SIZE
29#endif
30
31/*
32 * Device Configuration Data (DCD)
33 *
34 * Each entry must have the format:
35 * Addr-type           Address        Value
36 *
37 * where:
38 *	Addr-type register length (1,2 or 4 bytes)
39 *	Address	  absolute address of the register
40 *	value	  value to be stored in the register
41 */
42
43/* Enable OCRAM EPDC */
44DATA 4 0x30340004 0x4F400005
45
46/* =============================================================================
47 * DDR Controller Registers
48 * =============================================================================
49 * Memory type:           DDR3
50 * Manufacturer:          ISSI
51 * Device Part Number:    IS43TR16256AL-125KBL
52 * Clock Freq.:           533MHz
53 * Density per CS in Gb:  4
54 * Chip Selects used:     1
55 * Number of Banks:       8
56 * Row address:          15
57 * Column address:       10
58 * Data bus width:       16
59 * ROW-BANK interleave:  ENABLED
60 * =============================================================================
61 */
62
63DATA 4 0x30391000 0x00000002    // deassert presetn
64DATA 4 0x307A0000 0x01041001    // DDRC_MSTR
65DATA 4 0x307A0064 0x00400046    // DDRC_RFSHTMG
66DATA 4 0x307a0490 0x00000001    // DDRC_PCTRL_0
67DATA 4 0x307A00D4 0x00690000    // DDRC_INIT1
68DATA 4 0x307A00D0 0x00020083    // DDRC_INIT0
69DATA 4 0x307A00DC 0x09300004    // DDRC_INIT3
70DATA 4 0x307A00E0 0x04080000    // DDRC_INIT4
71DATA 4 0x307A00E4 0x00100004    // DDRC_INIT5
72DATA 4 0x307A00F4 0x0000033F    // DDRC_RANKCTL
73DATA 4 0x307A0100 0x090B1109    // DDRC_DRAMTMG0
74DATA 4 0x307A0104 0x0007020D    // DDRC_DRAMTMG1
75DATA 4 0x307A0108 0x03040407    // DDRC_DRAMTMG2
76DATA 4 0x307A010C 0x00002006    // DDRC_DRAMTMG3
77DATA 4 0x307A0110 0x04020205    // DDRC_DRAMTMG4
78DATA 4 0x307A0114 0x03030202    // DDRC_DRAMTMG5
79DATA 4 0x307A0120 0x00000803    // DDRC_DRAMTMG8
80DATA 4 0x307A0180 0x00800020    // DDRC_ZQCTL0
81DATA 4 0x307A0190 0x02098204    // DDRC_DFITMG0
82DATA 4 0x307A0194 0x00030303    // DDRC_DFITMG1
83DATA 4 0x307A01A0 0x80400003    // DDRC_DFIUPD0
84DATA 4 0x307A01A4 0x00100020    // DDRC_DFIUPD1
85DATA 4 0x307A01A8 0x80100004    // DDRC_DFIUPD2
86DATA 4 0x307A0200 0x00000015    // DDRC_ADDRMAP0
87DATA 4 0x307A0204 0x00070707    // DDRC_ADDRMAP1
88DATA 4 0x307A0210 0x00000F0F    // DDRC_ADDRMAP4
89DATA 4 0x307A0214 0x06060606    // DDRC_ADDRMAP5
90DATA 4 0x307A0218 0x0F060606    // DDRC_ADDRMAP6
91DATA 4 0x307A0240 0x06000604    // DDRC_ODTCFG
92DATA 4 0x307A0244 0x00000001    // DDRC_ODTMAP
93
94
95/* =============================================================================
96 * PHY Control Register
97 * =============================================================================
98 */
99
100DATA 4 0x30391000 0x00000000    // deassert presetn
101DATA 4 0x30790000 0x17420F40    // DDR_PHY_PHY_CON0
102DATA 4 0x30790004 0x10210100    // DDR_PHY_PHY_CON1
103DATA 4 0x30790010 0x00060807    // DDR_PHY_PHY_CON4
104DATA 4 0x307900B0 0x1010007E    // DDR_PHY_MDLL_CON0
105DATA 4 0x3079009C 0x00000D6E    // DDR_PHY_DRVDS_CON0
106DATA 4 0x30790030 0x08080808    // DDR_PHY_OFFSET_WR_CON0
107DATA 4 0x30790020 0x08080808    // DDR_PHY_OFFSET_RD_CON0
108DATA 4 0x30790050 0x01000010    // DDR_PHY_OFFSETD_CON0
109DATA 4 0x30790050 0x00000010    // DDR_PHY_OFFSETD_CON0
110DATA 4 0x30790018 0x0000000F    // DDR_PHY_LP_CON0
111DATA 4 0x307900C0 0x0E407304    // DDR_PHY_ZQ_CON0 - Start Manual ZQ
112DATA 4 0x307900C0 0x0E447304
113DATA 4 0x307900C0 0x0E447306
114DATA 4 0x307900C0 0x0E447304    // <= NOTE: Depending on JTAG device used, may need ~ 7 us pause at this point.
115DATA 4 0x307900C0 0x0E407304    // DDR_PHY_ZQ_CON0 - End Manual ZQ
116
117
118/* =============================================================================
119 * Final Initialization start sequence
120 * =============================================================================
121 */
122
123DATA 4 0x30384130 0x00000000    // Disable Clock
124DATA 4 0x30340020 0x00000178    // IOMUX_GRP_GRP8 - Start input to PHY
125DATA 4 0x30384130 0x00000002    // Enable Clock
126/* <= NOTE: Depending on JTAG device used, may need ~ 250 us pause at this point. */
127