1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Microsemi Corporation 4 */ 5 6#include <common.h> 7#include <image.h> 8#include <init.h> 9#include <log.h> 10#include <asm/global_data.h> 11#include <asm/io.h> 12#include <asm/addrspace.h> 13#include <asm/types.h> 14#include <spi.h> 15#include <led.h> 16#include <wait_bit.h> 17#include <miiphy.h> 18#include <linux/bitops.h> 19#include <linux/printk.h> 20 21DECLARE_GLOBAL_DATA_PTR; 22 23enum { 24 BOARD_TYPE_PCB120 = 0xAABBCC00, 25 BOARD_TYPE_PCB123, 26}; 27 28void mscc_switch_reset(bool enter) 29{ 30 /* Nasty workaround to avoid GPIO19 (DDR!) being reset */ 31 mscc_gpio_set_alternate(19, 2); 32 33 debug("applying SwC reset\n"); 34 35 writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET); 36 writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST); 37 38 if (wait_for_bit_le32(BASE_DEVCPU_GCB + PERF_SOFT_RST, 39 PERF_SOFT_RST_SOFT_CHIP_RST, false, 5000, false)) 40 pr_err("Tiemout while waiting for switch reset\n"); 41 42 /* 43 * Reset GPIO19 mode back as regular GPIO, output, high (DDR 44 * not reset) (Order is important) 45 */ 46 setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19)); 47 writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET); 48 mscc_gpio_set_alternate(19, 0); 49} 50 51int board_phy_config(struct phy_device *phydev) 52{ 53 if (gd->board_type == BOARD_TYPE_PCB123) 54 return 0; 55 56 phy_write(phydev, 0, 31, 0x10); 57 phy_write(phydev, 0, 18, 0x80F0); 58 while (phy_read(phydev, 0, 18) & 0x8000) 59 ; 60 phy_write(phydev, 0, 31, 0); 61 62 return 0; 63} 64 65void board_debug_uart_init(void) 66{ 67 /* too early for the pinctrl driver, so configure the UART pins here */ 68 mscc_gpio_set_alternate(6, 1); 69 mscc_gpio_set_alternate(7, 1); 70} 71 72int board_early_init_r(void) 73{ 74 /* Prepare SPI controller to be used in master mode */ 75 writel(0, BASE_CFG + ICPU_SW_MODE); 76 clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL, 77 ICPU_GENERAL_CTRL_IF_SI_OWNER_M, 78 ICPU_GENERAL_CTRL_IF_SI_OWNER(2)); 79 80 /* Address of boot parameters */ 81 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE; 82 83 return 0; 84} 85 86static void do_board_detect(void) 87{ 88 u16 dummy = 0; 89 90 /* Enable MIIM */ 91 mscc_gpio_set_alternate(14, 1); 92 mscc_gpio_set_alternate(15, 1); 93 if (mscc_phy_rd(1, 0, 0, &dummy) == 0) 94 gd->board_type = BOARD_TYPE_PCB120; 95 else 96 gd->board_type = BOARD_TYPE_PCB123; 97} 98 99#if defined(CONFIG_MULTI_DTB_FIT) 100int board_fit_config_name_match(const char *name) 101{ 102 if (gd->board_type == BOARD_TYPE_PCB120 && 103 strcmp(name, "ocelot_pcb120") == 0) 104 return 0; 105 106 if (gd->board_type == BOARD_TYPE_PCB123 && 107 strcmp(name, "ocelot_pcb123") == 0) 108 return 0; 109 110 return -1; 111} 112#endif 113 114#if defined(CONFIG_DTB_RESELECT) 115int embedded_dtb_select(void) 116{ 117 do_board_detect(); 118 fdtdec_setup(); 119 120 return 0; 121} 122#endif 123