1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> 4 */ 5 6#include <config.h> 7#include <gt64120.h> 8#include <msc01.h> 9#include <pci.h> 10 11#include <asm/addrspace.h> 12#include <asm/asm.h> 13#include <asm/regdef.h> 14#include <asm/malta.h> 15#include <asm/mipsregs.h> 16 17#ifdef CONFIG_SYS_BIG_ENDIAN 18#define CPU_TO_GT32(_x) ((_x)) 19#else 20#define CPU_TO_GT32(_x) ( \ 21 (((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \ 22 (((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24)) 23#endif 24 25 .text 26 .set noreorder 27 28 .globl lowlevel_init 29lowlevel_init: 30 /* detect the core card */ 31 PTR_LI t0, CKSEG1ADDR(MALTA_REVISION) 32 lw t0, 0(t0) 33 srl t0, t0, MALTA_REVISION_CORID_SHF 34 andi t0, t0, (MALTA_REVISION_CORID_MSK >> \ 35 MALTA_REVISION_CORID_SHF) 36 37 /* core cards using the gt64120 system controller */ 38 li t1, MALTA_REVISION_CORID_CORE_LV 39 beq t0, t1, _gt64120 40 41 /* core cards using the MSC01 system controller */ 42 li t1, MALTA_REVISION_CORID_CORE_FPGA6 43 beq t0, t1, _msc01 44 nop 45 46 /* unknown system controller */ 47 b . 48 nop 49 50 /* 51 * Load BAR registers of GT64120 as done by YAMON 52 * 53 * based on a patch sent by Antony Pavlov <antonynpavlov@gmail.com> 54 * to the barebox mailing list. 55 * The subject of the original patch: 56 * 'MIPS: qemu-malta: add YAMON-style GT64120 memory map' 57 * URL: 58 * http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html 59 * 60 * based on write_bootloader() in qemu.git/hw/mips_malta.c 61 * see GT64120 manual and qemu.git/hw/gt64xxx.c for details 62 */ 63_gt64120: 64 /* move GT64120 registers from 0x14000000 to 0x1be00000 */ 65 PTR_LI t1, CKSEG1ADDR(GT_DEF_BASE) 66 li t0, CPU_TO_GT32(0xdf000000) 67 sw t0, GT_ISD_OFS(t1) 68 69 /* setup MEM-to-PCI0 mapping */ 70 PTR_LI t1, CKSEG1ADDR(MALTA_GT_BASE) 71 72 /* setup PCI0 io window to 0x18000000-0x181fffff */ 73 li t0, CPU_TO_GT32(0xc0000000) 74 sw t0, GT_PCI0IOLD_OFS(t1) 75 li t0, CPU_TO_GT32(0x40000000) 76 sw t0, GT_PCI0IOHD_OFS(t1) 77 78 /* setup PCI0 mem windows */ 79 li t0, CPU_TO_GT32(0x80000000) 80 sw t0, GT_PCI0M0LD_OFS(t1) 81 li t0, CPU_TO_GT32(0x3f000000) 82 sw t0, GT_PCI0M0HD_OFS(t1) 83 84 li t0, CPU_TO_GT32(0xc1000000) 85 sw t0, GT_PCI0M1LD_OFS(t1) 86 li t0, CPU_TO_GT32(0x5e000000) 87 sw t0, GT_PCI0M1HD_OFS(t1) 88 89 jr ra 90 nop 91 92 /* 93 * 94 */ 95_msc01: 96 /* setup peripheral bus controller clock divide */ 97 PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PBC_BASE) 98 li t1, 0x1 << MSC01_PBC_CLKCFG_SHF 99 sw t1, MSC01_PBC_CLKCFG_OFS(t0) 100 101 /* tweak peripheral bus controller timings */ 102 li t1, (0x1 << MSC01_PBC_CS0TIM_CDT_SHF) | \ 103 (0x1 << MSC01_PBC_CS0TIM_CAT_SHF) 104 sw t1, MSC01_PBC_CS0TIM_OFS(t0) 105 li t1, (0x0 << MSC01_PBC_CS0RW_RDT_SHF) | \ 106 (0x2 << MSC01_PBC_CS0RW_RAT_SHF) | \ 107 (0x0 << MSC01_PBC_CS0RW_WDT_SHF) | \ 108 (0x2 << MSC01_PBC_CS0RW_WAT_SHF) 109 sw t1, MSC01_PBC_CS0RW_OFS(t0) 110 lw t1, MSC01_PBC_CS0CFG_OFS(t0) 111 li t2, MSC01_PBC_CS0CFG_DTYP_MSK 112 and t1, t2 113 ori t1, (0x0 << MSC01_PBC_CS0CFG_ADM_SHF) | \ 114 (0x3 << MSC01_PBC_CS0CFG_WSIDLE_SHF) | \ 115 (0x10 << MSC01_PBC_CS0CFG_WS_SHF) 116 sw t1, MSC01_PBC_CS0CFG_OFS(t0) 117 118 /* setup basic address decode */ 119 PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE) 120 li t1, 0x0 121 li t2, -CFG_SYS_SDRAM_SIZE 122 sw t1, MSC01_BIU_MCBAS1L_OFS(t0) 123 sw t2, MSC01_BIU_MCMSK1L_OFS(t0) 124 sw t1, MSC01_BIU_MCBAS2L_OFS(t0) 125 sw t2, MSC01_BIU_MCMSK2L_OFS(t0) 126 127 /* initialise IP1 - unused */ 128 li t1, MALTA_MSC01_IP1_BASE 129 li t2, -MALTA_MSC01_IP1_SIZE 130 sw t1, MSC01_BIU_IP1BAS1L_OFS(t0) 131 sw t2, MSC01_BIU_IP1MSK1L_OFS(t0) 132 sw t1, MSC01_BIU_IP1BAS2L_OFS(t0) 133 sw t2, MSC01_BIU_IP1MSK2L_OFS(t0) 134 135 /* initialise IP2 - PCI */ 136 li t1, MALTA_MSC01_IP2_BASE1 137 li t2, -MALTA_MSC01_IP2_SIZE1 138 sw t1, MSC01_BIU_IP2BAS1L_OFS(t0) 139 sw t2, MSC01_BIU_IP2MSK1L_OFS(t0) 140 li t1, MALTA_MSC01_IP2_BASE2 141 li t2, -MALTA_MSC01_IP2_SIZE2 142 sw t1, MSC01_BIU_IP2BAS2L_OFS(t0) 143 sw t2, MSC01_BIU_IP2MSK2L_OFS(t0) 144 145 /* initialise IP3 - peripheral bus controller */ 146 li t1, MALTA_MSC01_IP3_BASE 147 li t2, -MALTA_MSC01_IP3_SIZE 148 sw t1, MSC01_BIU_IP3BAS1L_OFS(t0) 149 sw t2, MSC01_BIU_IP3MSK1L_OFS(t0) 150 sw t1, MSC01_BIU_IP3BAS2L_OFS(t0) 151 sw t2, MSC01_BIU_IP3MSK2L_OFS(t0) 152 153 /* setup PCI memory */ 154 PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PCI_BASE) 155 li t1, MALTA_MSC01_PCIMEM_BASE 156 li t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK 157 li t3, MALTA_MSC01_PCIMEM_MAP 158 sw t1, MSC01_PCI_SC2PMBASL_OFS(t0) 159 sw t2, MSC01_PCI_SC2PMMSKL_OFS(t0) 160 sw t3, MSC01_PCI_SC2PMMAPL_OFS(t0) 161 162 /* setup PCI I/O */ 163 li t1, MALTA_MSC01_PCIIO_BASE 164 li t2, (-MALTA_MSC01_PCIIO_SIZE) & MSC01_PCI_SC2PIOMSKL_MSK_MSK 165 li t3, MALTA_MSC01_PCIIO_MAP 166 sw t1, MSC01_PCI_SC2PIOBASL_OFS(t0) 167 sw t2, MSC01_PCI_SC2PIOMSKL_OFS(t0) 168 sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0) 169 170 /* setup PCI_BAR0 memory window */ 171 li t1, -CFG_SYS_SDRAM_SIZE 172 sw t1, MSC01_PCI_BAR0_OFS(t0) 173 174 /* setup PCI to SysCon/CPU translation */ 175 sw t1, MSC01_PCI_P2SCMSKL_OFS(t0) 176 sw zero, MSC01_PCI_P2SCMAPL_OFS(t0) 177 178 /* setup PCI vendor & device IDs */ 179 li t1, (PCI_VENDOR_ID_MIPS << MSC01_PCI_HEAD0_VENDORID_SHF) | \ 180 (PCI_DEVICE_ID_MIPS_MSC01 << MSC01_PCI_HEAD0_DEVICEID_SHF) 181 sw t1, MSC01_PCI_HEAD0_OFS(t0) 182 183 /* setup PCI subsystem vendor & device IDs */ 184 sw t1, MSC01_PCI_HEAD11_OFS(t0) 185 186 /* setup PCI class, revision */ 187 li t1, (PCI_CLASS_BRIDGE_HOST << MSC01_PCI_HEAD2_CLASS_SHF) | \ 188 (0x1 << MSC01_PCI_HEAD2_REV_SHF) 189 sw t1, MSC01_PCI_HEAD2_OFS(t0) 190 191 /* ensure a sane setup */ 192 sw zero, MSC01_PCI_HEAD3_OFS(t0) 193 sw zero, MSC01_PCI_HEAD4_OFS(t0) 194 sw zero, MSC01_PCI_HEAD5_OFS(t0) 195 sw zero, MSC01_PCI_HEAD6_OFS(t0) 196 sw zero, MSC01_PCI_HEAD7_OFS(t0) 197 sw zero, MSC01_PCI_HEAD8_OFS(t0) 198 sw zero, MSC01_PCI_HEAD9_OFS(t0) 199 sw zero, MSC01_PCI_HEAD10_OFS(t0) 200 sw zero, MSC01_PCI_HEAD12_OFS(t0) 201 sw zero, MSC01_PCI_HEAD13_OFS(t0) 202 sw zero, MSC01_PCI_HEAD14_OFS(t0) 203 sw zero, MSC01_PCI_HEAD15_OFS(t0) 204 205 /* setup PCI command register */ 206 li t1, (PCI_COMMAND_FAST_BACK | \ 207 PCI_COMMAND_SERR | \ 208 PCI_COMMAND_PARITY | \ 209 PCI_COMMAND_MASTER | \ 210 PCI_COMMAND_MEMORY) 211 sw t1, MSC01_PCI_HEAD1_OFS(t0) 212 213 /* setup PCI byte swapping */ 214#ifdef CONFIG_SYS_BIG_ENDIAN 215 li t1, (0x1 << MSC01_PCI_SWAP_BAR0_BSWAP_SHF) | \ 216 (0x1 << MSC01_PCI_SWAP_IO_BSWAP_SHF) 217 sw t1, MSC01_PCI_SWAP_OFS(t0) 218#else 219 sw zero, MSC01_PCI_SWAP_OFS(t0) 220#endif 221 222 /* enable PCI host configuration cycles */ 223 lw t1, MSC01_PCI_CFG_OFS(t0) 224 li t2, MSC01_PCI_CFG_RA_MSK | \ 225 MSC01_PCI_CFG_G_MSK | \ 226 MSC01_PCI_CFG_EN_MSK 227 or t1, t1, t2 228 sw t1, MSC01_PCI_CFG_OFS(t0) 229 230 jr ra 231 nop 232