1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2015 Stefan Roese <sr@denx.de> 4 * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc> 5 */ 6 7#include <common.h> 8#include <command.h> 9#include <dm.h> 10#include <event.h> 11#include <init.h> 12#include <miiphy.h> 13#include <net.h> 14#include <tpm-v1.h> 15#include <asm/global_data.h> 16#include <asm/io.h> 17#include <asm/arch/cpu.h> 18#include <asm-generic/gpio.h> 19#include <linux/delay.h> 20 21#include "../drivers/ddr/marvell/a38x/ddr3_init.h" 22#include "../arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.h" 23 24#include "keyprogram.h" 25#include "dt_helpers.h" 26#include "hydra.h" 27#include "ihs_phys.h" 28 29DECLARE_GLOBAL_DATA_PTR; 30 31#define DB_GP_88F68XX_GPP_OUT_ENA_LOW 0x7fffffff 32#define DB_GP_88F68XX_GPP_OUT_ENA_MID 0xffffefff 33 34#define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0 35#define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x00001000 36#define DB_GP_88F68XX_GPP_POL_LOW 0x0 37#define DB_GP_88F68XX_GPP_POL_MID 0x0 38 39/* 40 * Define the DDR layout / topology here in the board file. This will 41 * be used by the DDR3 init code in the SPL U-Boot version to configure 42 * the DDR3 controller. 43 */ 44static struct mv_ddr_topology_map ddr_topology_map = { 45 DEBUG_LEVEL_ERROR, 46 0x1, /* active interfaces */ 47 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ 48 { { { {0x1, 0, 0, 0}, 49 {0x1, 0, 0, 0}, 50 {0x1, 0, 0, 0}, 51 {0x1, 0, 0, 0}, 52 {0x1, 0, 0, 0} }, 53 SPEED_BIN_DDR_1600K, /* speed_bin */ 54 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */ 55 MV_DDR_DIE_CAP_4GBIT, /* mem_size */ 56 MV_DDR_FREQ_533, /* frequency */ 57 0, 0, /* cas_wl cas_l */ 58 MV_DDR_TEMP_LOW, /* temperature */ 59 MV_DDR_TIM_DEFAULT} }, /* timing */ 60 BUS_MASK_32BIT, /* Busses mask */ 61 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ 62 NOT_COMBINED, /* ddr twin-die combined */ 63 { {0} }, /* raw spd data */ 64 {0} /* timing parameters */ 65 66}; 67 68static struct serdes_map serdes_topology_map[] = { 69 {SGMII0, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 70 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 71 /* SATA tx polarity is inverted */ 72 {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 1}, 73 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 74 {DEFAULT_SERDES, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 75 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0} 76}; 77 78int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) 79{ 80 *serdes_map_array = serdes_topology_map; 81 *count = ARRAY_SIZE(serdes_topology_map); 82 return 0; 83} 84 85void spl_board_init(void) 86{ 87#ifdef CONFIG_SPL_BUILD 88 uint k; 89 struct gpio_desc gpio = {}; 90 91 /* Enable PCIe link 2 */ 92 setbits_32(MVEBU_REGISTER(0x18204), BIT(2)); 93 mdelay(10); 94 95 if (!request_gpio_by_name(&gpio, "pca9698@22", 31, "fpga-program-gpio")) { 96 /* prepare FPGA reconfiguration */ 97 dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT); 98 dm_gpio_set_value(&gpio, 0); 99 100 /* give lunatic PCIe clock some time to stabilize */ 101 mdelay(500); 102 103 /* start FPGA reconfiguration */ 104 dm_gpio_set_dir_flags(&gpio, GPIOD_IS_IN); 105 } 106 107 /* wait for FPGA done */ 108 if (!request_gpio_by_name(&gpio, "pca9698@22", 19, "fpga-done-gpio")) { 109 for (k = 0; k < 20; ++k) { 110 if (dm_gpio_get_value(&gpio)) { 111 printf("FPGA done after %u rounds\n", k); 112 break; 113 } 114 mdelay(100); 115 } 116 } 117 118 /* disable FPGA reset */ 119 if (!request_gpio_by_name(&gpio, "gpio@18100", 6, "cpu-to-fpga-reset")) { 120 dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT); 121 dm_gpio_set_value(&gpio, 1); 122 } 123 124 /* wait for FPGA ready */ 125 if (!request_gpio_by_name(&gpio, "pca9698@22", 27, "fpga-ready-gpio")) { 126 for (k = 0; k < 2; ++k) { 127 if (!dm_gpio_get_value(&gpio)) 128 break; 129 mdelay(100); 130 } 131 } 132#endif 133} 134 135struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) 136{ 137 return &ddr_topology_map; 138} 139 140int board_early_init_f(void) 141{ 142#ifdef CONFIG_SPL_BUILD 143 /* Configure MPP */ 144 writel(0x00111111, MVEBU_MPP_BASE + 0x00); 145 writel(0x40040000, MVEBU_MPP_BASE + 0x04); 146 writel(0x00466444, MVEBU_MPP_BASE + 0x08); 147 writel(0x00043300, MVEBU_MPP_BASE + 0x0c); 148 writel(0x44400000, MVEBU_MPP_BASE + 0x10); 149 writel(0x20000334, MVEBU_MPP_BASE + 0x14); 150 writel(0x40000000, MVEBU_MPP_BASE + 0x18); 151 writel(0x00004444, MVEBU_MPP_BASE + 0x1c); 152 153 /* Set GPP Out value */ 154 writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); 155 writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); 156 157 /* Set GPP Polarity */ 158 writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); 159 writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); 160 161 /* Set GPP Out Enable */ 162 writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); 163 writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); 164#endif 165 166 return 0; 167} 168 169int board_init(void) 170{ 171 /* Address of boot parameters */ 172 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 173 174 return 0; 175} 176 177#ifndef CONFIG_SPL_BUILD 178void init_host_phys(struct mii_dev *bus) 179{ 180 uint k; 181 182 for (k = 0; k < 2; ++k) { 183 struct phy_device *phydev; 184 185 phydev = phy_find_by_mask(bus, 1 << k); 186 187 if (phydev) { 188 phydev->interface = PHY_INTERFACE_MODE_SGMII; 189 phy_config(phydev); 190 } 191 } 192} 193 194int ccdc_eth_init(void) 195{ 196 uint k; 197 uint octo_phy_mask = 0; 198 int ret; 199 struct mii_dev *bus; 200 201 /* Init SoC's phys */ 202 bus = miiphy_get_dev_by_name("ethernet@34000"); 203 204 if (bus) 205 init_host_phys(bus); 206 207 bus = miiphy_get_dev_by_name("ethernet@70000"); 208 209 if (bus) 210 init_host_phys(bus); 211 212 /* Init octo phys */ 213 octo_phy_mask = calculate_octo_phy_mask(); 214 215 printf("IHS PHYS: %08x", octo_phy_mask); 216 217 ret = init_octo_phys(octo_phy_mask); 218 219 if (ret) 220 return ret; 221 222 printf("\n"); 223 224 if (!get_fpga()) { 225 puts("fpga was NULL\n"); 226 return 1; 227 } 228 229 /* reset all FPGA-QSGMII instances */ 230 for (k = 0; k < 80; ++k) 231 writel(1 << 31, get_fpga()->qsgmii_port_state[k]); 232 233 udelay(100); 234 235 for (k = 0; k < 80; ++k) 236 writel(0, get_fpga()->qsgmii_port_state[k]); 237 return 0; 238} 239 240#endif 241 242int board_late_init(void) 243{ 244#ifndef CONFIG_SPL_BUILD 245 hydra_initialize(); 246#endif 247 return 0; 248} 249 250int board_fix_fdt(void *rw_fdt_blob) 251{ 252 struct udevice *bus = NULL; 253 uint k; 254 char name[64]; 255 int err; 256 257 err = uclass_get_device_by_name(UCLASS_I2C, "i2c@11000", &bus); 258 259 if (err) { 260 printf("Could not get I2C bus.\n"); 261 return err; 262 } 263 264 for (k = 0x21; k <= 0x26; k++) { 265 snprintf(name, 64, 266 "/soc/internal-regs/i2c@11000/pca9698@%02x", k); 267 268 if (!dm_i2c_simple_probe(bus, k)) 269 fdt_disable_by_ofname(rw_fdt_blob, name); 270 } 271 272 return 0; 273} 274 275#ifndef CONFIG_SPL_BUILD 276static int last_stage_init(void) 277{ 278 struct udevice *tpm; 279 int ret; 280 281 if (IS_ENABLED(CONFIG_SPL_BUILD)) 282 return 0; 283 ccdc_eth_init(); 284 285 ret = uclass_first_device_err(UCLASS_TPM, &tpm); 286 if (ret) { 287 printf("Could not find TPM (ret=%d)\n", ret); 288 return ret; 289 } 290 291 if (ret || tpm_init(tpm) || tpm1_startup(tpm, TPM_ST_CLEAR) || 292 tpm1_continue_self_test(tpm)) { 293 return 1; 294 } 295 296 mdelay(37); 297 298 flush_keys(tpm); 299 load_and_run_keyprog(tpm); 300 301 return 0; 302} 303EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init); 304#endif 305