1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2014 Gateworks Corporation 4 * Author: Tim Harvey <tharvey@gateworks.com> 5 */ 6 7#include <common.h> 8#include <env.h> 9#include <gsc.h> 10#include <hang.h> 11#include <i2c.h> 12#include <init.h> 13#include <spl.h> 14#include <asm/arch/crm_regs.h> 15#include <asm/arch/mx6-ddr.h> 16#include <asm/arch/mx6-pins.h> 17#include <asm/arch/sys_proto.h> 18#include <asm/mach-imx/mxc_i2c.h> 19#include <linux/delay.h> 20#include <power/mp5416.h> 21#include <power/pmic.h> 22#include <power/pfuze100_pmic.h> 23#include <power/ltc3676_pmic.h> 24 25#include "common.h" 26 27#define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ 28#define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */ 29#define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */ 30 31/* configure MX6Q/DUAL mmdc DDR io registers */ 32struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { 33 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ 34 .dram_sdclk_0 = 0x00020030, 35 .dram_sdclk_1 = 0x00020030, 36 .dram_cas = 0x00020030, 37 .dram_ras = 0x00020030, 38 .dram_reset = 0x00020030, 39 /* SDCKE[0:1]: 100k pull-up */ 40 .dram_sdcke0 = 0x00003000, 41 .dram_sdcke1 = 0x00003000, 42 /* SDBA2: pull-up disabled */ 43 .dram_sdba2 = 0x00000000, 44 /* SDODT[0:1]: 100k pull-up, 40 ohm */ 45 .dram_sdodt0 = 0x00003030, 46 .dram_sdodt1 = 0x00003030, 47 /* SDQS[0:7]: Differential input, 40 ohm */ 48 .dram_sdqs0 = 0x00000030, 49 .dram_sdqs1 = 0x00000030, 50 .dram_sdqs2 = 0x00000030, 51 .dram_sdqs3 = 0x00000030, 52 .dram_sdqs4 = 0x00000030, 53 .dram_sdqs5 = 0x00000030, 54 .dram_sdqs6 = 0x00000030, 55 .dram_sdqs7 = 0x00000030, 56 57 /* DQM[0:7]: Differential input, 40 ohm */ 58 .dram_dqm0 = 0x00020030, 59 .dram_dqm1 = 0x00020030, 60 .dram_dqm2 = 0x00020030, 61 .dram_dqm3 = 0x00020030, 62 .dram_dqm4 = 0x00020030, 63 .dram_dqm5 = 0x00020030, 64 .dram_dqm6 = 0x00020030, 65 .dram_dqm7 = 0x00020030, 66}; 67 68/* configure MX6Q/DUAL mmdc GRP io registers */ 69struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { 70 /* DDR3 */ 71 .grp_ddr_type = 0x000c0000, 72 .grp_ddrmode_ctl = 0x00020000, 73 /* disable DDR pullups */ 74 .grp_ddrpke = 0x00000000, 75 /* ADDR[00:16], SDBA[0:1]: 40 ohm */ 76 .grp_addds = 0x00000030, 77 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ 78 .grp_ctlds = 0x00000030, 79 /* DATA[00:63]: Differential input, 40 ohm */ 80 .grp_ddrmode = 0x00020000, 81 .grp_b0ds = 0x00000030, 82 .grp_b1ds = 0x00000030, 83 .grp_b2ds = 0x00000030, 84 .grp_b3ds = 0x00000030, 85 .grp_b4ds = 0x00000030, 86 .grp_b5ds = 0x00000030, 87 .grp_b6ds = 0x00000030, 88 .grp_b7ds = 0x00000030, 89}; 90 91/* configure MX6SOLO/DUALLITE mmdc DDR io registers */ 92struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { 93 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ 94 .dram_sdclk_0 = 0x00020030, 95 .dram_sdclk_1 = 0x00020030, 96 .dram_cas = 0x00020030, 97 .dram_ras = 0x00020030, 98 .dram_reset = 0x00020030, 99 /* SDCKE[0:1]: 100k pull-up */ 100 .dram_sdcke0 = 0x00003000, 101 .dram_sdcke1 = 0x00003000, 102 /* SDBA2: pull-up disabled */ 103 .dram_sdba2 = 0x00000000, 104 /* SDODT[0:1]: 100k pull-up, 40 ohm */ 105 .dram_sdodt0 = 0x00003030, 106 .dram_sdodt1 = 0x00003030, 107 /* SDQS[0:7]: Differential input, 40 ohm */ 108 .dram_sdqs0 = 0x00000030, 109 .dram_sdqs1 = 0x00000030, 110 .dram_sdqs2 = 0x00000030, 111 .dram_sdqs3 = 0x00000030, 112 .dram_sdqs4 = 0x00000030, 113 .dram_sdqs5 = 0x00000030, 114 .dram_sdqs6 = 0x00000030, 115 .dram_sdqs7 = 0x00000030, 116 117 /* DQM[0:7]: Differential input, 40 ohm */ 118 .dram_dqm0 = 0x00020030, 119 .dram_dqm1 = 0x00020030, 120 .dram_dqm2 = 0x00020030, 121 .dram_dqm3 = 0x00020030, 122 .dram_dqm4 = 0x00020030, 123 .dram_dqm5 = 0x00020030, 124 .dram_dqm6 = 0x00020030, 125 .dram_dqm7 = 0x00020030, 126}; 127 128/* configure MX6SOLO/DUALLITE mmdc GRP io registers */ 129struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { 130 /* DDR3 */ 131 .grp_ddr_type = 0x000c0000, 132 /* SDQS[0:7]: Differential input, 40 ohm */ 133 .grp_ddrmode_ctl = 0x00020000, 134 /* disable DDR pullups */ 135 .grp_ddrpke = 0x00000000, 136 /* ADDR[00:16], SDBA[0:1]: 40 ohm */ 137 .grp_addds = 0x00000030, 138 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ 139 .grp_ctlds = 0x00000030, 140 /* DATA[00:63]: Differential input, 40 ohm */ 141 .grp_ddrmode = 0x00020000, 142 .grp_b0ds = 0x00000030, 143 .grp_b1ds = 0x00000030, 144 .grp_b2ds = 0x00000030, 145 .grp_b3ds = 0x00000030, 146 .grp_b4ds = 0x00000030, 147 .grp_b5ds = 0x00000030, 148 .grp_b6ds = 0x00000030, 149 .grp_b7ds = 0x00000030, 150}; 151 152/* MT41K64M16JT-125 (1Gb density) */ 153static struct mx6_ddr3_cfg mt41k64m16jt_125 = { 154 .mem_speed = 1600, 155 .density = 1, 156 .width = 16, 157 .banks = 8, 158 .rowaddr = 13, 159 .coladdr = 10, 160 .pagesz = 2, 161 .trcd = 1375, 162 .trcmin = 4875, 163 .trasmin = 3500, 164}; 165 166/* MT41K128M16JT-125 (2Gb density) */ 167static struct mx6_ddr3_cfg mt41k128m16jt_125 = { 168 .mem_speed = 1600, 169 .density = 2, 170 .width = 16, 171 .banks = 8, 172 .rowaddr = 14, 173 .coladdr = 10, 174 .pagesz = 2, 175 .trcd = 1375, 176 .trcmin = 4875, 177 .trasmin = 3500, 178}; 179 180/* MT41K256M16HA-125 (4Gb density) */ 181static struct mx6_ddr3_cfg mt41k256m16ha_125 = { 182 .mem_speed = 1600, 183 .density = 4, 184 .width = 16, 185 .banks = 8, 186 .rowaddr = 15, 187 .coladdr = 10, 188 .pagesz = 2, 189 .trcd = 1375, 190 .trcmin = 4875, 191 .trasmin = 3500, 192}; 193 194/* MT41K512M16HA-125 (8Gb density) */ 195static struct mx6_ddr3_cfg mt41k512m16ha_125 = { 196 .mem_speed = 1600, 197 .density = 8, 198 .width = 16, 199 .banks = 8, 200 .rowaddr = 16, 201 .coladdr = 10, 202 .pagesz = 2, 203 .trcd = 1375, 204 .trcmin = 4875, 205 .trasmin = 3500, 206}; 207 208/* 209 * calibration - these are the various CPU/DDR3 combinations we support 210 */ 211static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = { 212 /* write leveling calibration determine */ 213 .p0_mpwldectrl0 = 0x004C004E, 214 .p0_mpwldectrl1 = 0x00440044, 215 /* Read DQS Gating calibration */ 216 .p0_mpdgctrl0 = 0x42440247, 217 .p0_mpdgctrl1 = 0x02310232, 218 /* Read Calibration: DQS delay relative to DQ read access */ 219 .p0_mprddlctl = 0x45424746, 220 /* Write Calibration: DQ/DM delay relative to DQS write access */ 221 .p0_mpwrdlctl = 0x33382C31, 222}; 223 224/* TODO: update with calibrated values */ 225static struct mx6_mmdc_calibration mx6dq_64x64_mmdc_calib = { 226 /* write leveling calibration determine */ 227 .p0_mpwldectrl0 = 0x00190017, 228 .p0_mpwldectrl1 = 0x00140026, 229 .p1_mpwldectrl0 = 0x0021001C, 230 .p1_mpwldectrl1 = 0x0011001D, 231 /* Read DQS Gating calibration */ 232 .p0_mpdgctrl0 = 0x43380347, 233 .p0_mpdgctrl1 = 0x433C034D, 234 .p1_mpdgctrl0 = 0x032C0324, 235 .p1_mpdgctrl1 = 0x03310232, 236 /* Read Calibration: DQS delay relative to DQ read access */ 237 .p0_mprddlctl = 0x3C313539, 238 .p1_mprddlctl = 0x37343141, 239 /* Write Calibration: DQ/DM delay relative to DQS write access */ 240 .p0_mpwrdlctl = 0x36393C39, 241 .p1_mpwrdlctl = 0x42344438, 242}; 243 244/* TODO: update with calibrated values */ 245static struct mx6_mmdc_calibration mx6sdl_64x64_mmdc_calib = { 246 /* write leveling calibration determine */ 247 .p0_mpwldectrl0 = 0x003C003C, 248 .p0_mpwldectrl1 = 0x001F002A, 249 .p1_mpwldectrl0 = 0x00330038, 250 .p1_mpwldectrl1 = 0x0022003F, 251 /* Read DQS Gating calibration */ 252 .p0_mpdgctrl0 = 0x42410244, 253 .p0_mpdgctrl1 = 0x4234023A, 254 .p1_mpdgctrl0 = 0x022D022D, 255 .p1_mpdgctrl1 = 0x021C0228, 256 /* Read Calibration: DQS delay relative to DQ read access */ 257 .p0_mprddlctl = 0x484A4C4B, 258 .p1_mprddlctl = 0x4B4D4E4B, 259 /* Write Calibration: DQ/DM delay relative to DQS write access */ 260 .p0_mpwrdlctl = 0x33342B32, 261 .p1_mpwrdlctl = 0x3933332B, 262}; 263 264static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = { 265 /* write leveling calibration determine */ 266 .p0_mpwldectrl0 = 0x001B0016, 267 .p0_mpwldectrl1 = 0x000C000E, 268 /* Read DQS Gating calibration */ 269 .p0_mpdgctrl0 = 0x4324033A, 270 .p0_mpdgctrl1 = 0x00000000, 271 /* Read Calibration: DQS delay relative to DQ read access */ 272 .p0_mprddlctl = 0x40403438, 273 /* Write Calibration: DQ/DM delay relative to DQS write access */ 274 .p0_mpwrdlctl = 0x40403D36, 275}; 276 277static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = { 278 /* write leveling calibration determine */ 279 .p0_mpwldectrl0 = 0x00420043, 280 .p0_mpwldectrl1 = 0x0016001A, 281 /* Read DQS Gating calibration */ 282 .p0_mpdgctrl0 = 0x4238023B, 283 .p0_mpdgctrl1 = 0x00000000, 284 /* Read Calibration: DQS delay relative to DQ read access */ 285 .p0_mprddlctl = 0x40404849, 286 /* Write Calibration: DQ/DM delay relative to DQS write access */ 287 .p0_mpwrdlctl = 0x40402E2F, 288}; 289 290static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = { 291 /* write leveling calibration determine */ 292 .p0_mpwldectrl0 = 0x00190017, 293 .p0_mpwldectrl1 = 0x00140026, 294 /* Read DQS Gating calibration */ 295 .p0_mpdgctrl0 = 0x43380347, 296 .p0_mpdgctrl1 = 0x433C034D, 297 /* Read Calibration: DQS delay relative to DQ read access */ 298 .p0_mprddlctl = 0x3C313539, 299 /* Write Calibration: DQ/DM delay relative to DQS write access */ 300 .p0_mpwrdlctl = 0x36393C39, 301}; 302 303static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = { 304 /* write leveling calibration determine */ 305 .p0_mpwldectrl0 = 0x003C003C, 306 .p0_mpwldectrl1 = 0x001F002A, 307 /* Read DQS Gating calibration */ 308 .p0_mpdgctrl0 = 0x42410244, 309 .p0_mpdgctrl1 = 0x4234023A, 310 /* Read Calibration: DQS delay relative to DQ read access */ 311 .p0_mprddlctl = 0x484A4C4B, 312 /* Write Calibration: DQ/DM delay relative to DQS write access */ 313 .p0_mpwrdlctl = 0x33342B32, 314}; 315 316static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = { 317 /* write leveling calibration determine */ 318 .p0_mpwldectrl0 = 0x00190017, 319 .p0_mpwldectrl1 = 0x00140026, 320 .p1_mpwldectrl0 = 0x0021001C, 321 .p1_mpwldectrl1 = 0x0011001D, 322 /* Read DQS Gating calibration */ 323 .p0_mpdgctrl0 = 0x43380347, 324 .p0_mpdgctrl1 = 0x433C034D, 325 .p1_mpdgctrl0 = 0x032C0324, 326 .p1_mpdgctrl1 = 0x03310232, 327 /* Read Calibration: DQS delay relative to DQ read access */ 328 .p0_mprddlctl = 0x3C313539, 329 .p1_mprddlctl = 0x37343141, 330 /* Write Calibration: DQ/DM delay relative to DQS write access */ 331 .p0_mpwrdlctl = 0x36393C39, 332 .p1_mpwrdlctl = 0x42344438, 333}; 334 335static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = { 336 /* write leveling calibration determine */ 337 .p0_mpwldectrl0 = 0x003C003C, 338 .p0_mpwldectrl1 = 0x001F002A, 339 .p1_mpwldectrl0 = 0x00330038, 340 .p1_mpwldectrl1 = 0x0022003F, 341 /* Read DQS Gating calibration */ 342 .p0_mpdgctrl0 = 0x42410244, 343 .p0_mpdgctrl1 = 0x4234023A, 344 .p1_mpdgctrl0 = 0x022D022D, 345 .p1_mpdgctrl1 = 0x021C0228, 346 /* Read Calibration: DQS delay relative to DQ read access */ 347 .p0_mprddlctl = 0x484A4C4B, 348 .p1_mprddlctl = 0x4B4D4E4B, 349 /* Write Calibration: DQ/DM delay relative to DQS write access */ 350 .p0_mpwrdlctl = 0x33342B32, 351 .p1_mpwrdlctl = 0x3933332B, 352}; 353 354static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = { 355 /* write leveling calibration determine */ 356 .p0_mpwldectrl0 = 0x001E001A, 357 .p0_mpwldectrl1 = 0x0026001F, 358 /* Read DQS Gating calibration */ 359 .p0_mpdgctrl0 = 0x43370349, 360 .p0_mpdgctrl1 = 0x032D0327, 361 /* Read Calibration: DQS delay relative to DQ read access */ 362 .p0_mprddlctl = 0x3D303639, 363 /* Write Calibration: DQ/DM delay relative to DQS write access */ 364 .p0_mpwrdlctl = 0x32363934, 365}; 366 367static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = { 368 /* write leveling calibration determine */ 369 .p0_mpwldectrl0 = 0X00480047, 370 .p0_mpwldectrl1 = 0X003D003F, 371 /* Read DQS Gating calibration */ 372 .p0_mpdgctrl0 = 0X423E0241, 373 .p0_mpdgctrl1 = 0X022B022C, 374 /* Read Calibration: DQS delay relative to DQ read access */ 375 .p0_mprddlctl = 0X49454A4A, 376 /* Write Calibration: DQ/DM delay relative to DQS write access */ 377 .p0_mpwrdlctl = 0X2E372C32, 378}; 379 380static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = { 381 /* write leveling calibration determine */ 382 .p0_mpwldectrl0 = 0X00220021, 383 .p0_mpwldectrl1 = 0X00200030, 384 .p1_mpwldectrl0 = 0X002D0027, 385 .p1_mpwldectrl1 = 0X00150026, 386 /* Read DQS Gating calibration */ 387 .p0_mpdgctrl0 = 0x43330342, 388 .p0_mpdgctrl1 = 0x0339034A, 389 .p1_mpdgctrl0 = 0x032F0325, 390 .p1_mpdgctrl1 = 0x032F022E, 391 /* Read Calibration: DQS delay relative to DQ read access */ 392 .p0_mprddlctl = 0X3A2E3437, 393 .p1_mprddlctl = 0X35312F3F, 394 /* Write Calibration: DQ/DM delay relative to DQS write access */ 395 .p0_mpwrdlctl = 0X33363B37, 396 .p1_mpwrdlctl = 0X40304239, 397}; 398 399static struct mx6_mmdc_calibration mx6sdl_256x64_mmdc_calib = { 400 /* write leveling calibration determine */ 401 .p0_mpwldectrl0 = 0x0048004A, 402 .p0_mpwldectrl1 = 0x003F004A, 403 .p1_mpwldectrl0 = 0x001E0028, 404 .p1_mpwldectrl1 = 0x002C0043, 405 /* Read DQS Gating calibration */ 406 .p0_mpdgctrl0 = 0x02250219, 407 .p0_mpdgctrl1 = 0x01790202, 408 .p1_mpdgctrl0 = 0x02080208, 409 .p1_mpdgctrl1 = 0x016C0175, 410 /* Read Calibration: DQS delay relative to DQ read access */ 411 .p0_mprddlctl = 0x4A4C4D4C, 412 .p1_mprddlctl = 0x494C4A48, 413 /* Write Calibration: DQ/DM delay relative to DQS write access */ 414 .p0_mpwrdlctl = 0x403F3437, 415 .p1_mpwrdlctl = 0x383A3930, 416}; 417 418static struct mx6_mmdc_calibration mx6sdl_256x64x2_mmdc_calib = { 419 /* write leveling calibration determine */ 420 .p0_mpwldectrl0 = 0x001F003F, 421 .p0_mpwldectrl1 = 0x001F001F, 422 .p1_mpwldectrl0 = 0x001F004E, 423 .p1_mpwldectrl1 = 0x0059001F, 424 /* Read DQS Gating calibration */ 425 .p0_mpdgctrl0 = 0x42220225, 426 .p0_mpdgctrl1 = 0x0213021F, 427 .p1_mpdgctrl0 = 0x022C0242, 428 .p1_mpdgctrl1 = 0x022C0244, 429 /* Read Calibration: DQS delay relative to DQ read access */ 430 .p0_mprddlctl = 0x474A4C4A, 431 .p1_mprddlctl = 0x48494C45, 432 /* Write Calibration: DQ/DM delay relative to DQS write access */ 433 .p0_mpwrdlctl = 0x3F3F3F36, 434 .p1_mpwrdlctl = 0x3F36363F, 435}; 436 437static struct mx6_mmdc_calibration mx6sdl_128x64x2_mmdc_calib = { 438 /* write leveling calibration determine */ 439 .p0_mpwldectrl0 = 0x001F003F, 440 .p0_mpwldectrl1 = 0x001F001F, 441 .p1_mpwldectrl0 = 0x001F004E, 442 .p1_mpwldectrl1 = 0x0059001F, 443 /* Read DQS Gating calibration */ 444 .p0_mpdgctrl0 = 0x42220225, 445 .p0_mpdgctrl1 = 0x0213021F, 446 .p1_mpdgctrl0 = 0x022C0242, 447 .p1_mpdgctrl1 = 0x022C0244, 448 /* Read Calibration: DQS delay relative to DQ read access */ 449 .p0_mprddlctl = 0x474A4C4A, 450 .p1_mprddlctl = 0x48494C45, 451 /* Write Calibration: DQ/DM delay relative to DQS write access */ 452 .p0_mpwrdlctl = 0x3F3F3F36, 453 .p1_mpwrdlctl = 0x3F36363F, 454}; 455 456static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = { 457 /* write leveling calibration determine */ 458 .p0_mpwldectrl0 = 0x002A0025, 459 .p0_mpwldectrl1 = 0x003A002A, 460 /* Read DQS Gating calibration */ 461 .p0_mpdgctrl0 = 0x43430356, 462 .p0_mpdgctrl1 = 0x033C0335, 463 /* Read Calibration: DQS delay relative to DQ read access */ 464 .p0_mprddlctl = 0x4B373F42, 465 /* Write Calibration: DQ/DM delay relative to DQS write access */ 466 .p0_mpwrdlctl = 0x303E3C36, 467}; 468 469static struct mx6_mmdc_calibration mx6dq_512x64_mmdc_calib = { 470 /* write leveling calibration determine */ 471 .p0_mpwldectrl0 = 0x00230020, 472 .p0_mpwldectrl1 = 0x002F002A, 473 .p1_mpwldectrl0 = 0x001D0027, 474 .p1_mpwldectrl1 = 0x00100023, 475 /* Read DQS Gating calibration */ 476 .p0_mpdgctrl0 = 0x03250339, 477 .p0_mpdgctrl1 = 0x031C0316, 478 .p1_mpdgctrl0 = 0x03210331, 479 .p1_mpdgctrl1 = 0x031C025A, 480 /* Read Calibration: DQS delay relative to DQ read access */ 481 .p0_mprddlctl = 0x40373C40, 482 .p1_mprddlctl = 0x3A373646, 483 /* Write Calibration: DQ/DM delay relative to DQS write access */ 484 .p0_mpwrdlctl = 0x2E353933, 485 .p1_mpwrdlctl = 0x3C2F3F35, 486}; 487 488static void spl_dram_init(int width, int size_mb, int board_model) 489{ 490 struct mx6_ddr3_cfg *mem = NULL; 491 struct mx6_mmdc_calibration *calib = NULL; 492 struct mx6_ddr_sysinfo sysinfo = { 493 /* width of data bus:0=16,1=32,2=64 */ 494 .dsize = width/32, 495 /* config for full 4GB range so that get_mem_size() works */ 496 .cs_density = 32, /* 32Gb per CS */ 497 /* single chip select */ 498 .ncs = 1, 499 .cs1_mirror = 0, 500 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ 501#ifdef RTT_NOM_120OHM 502 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ 503#else 504 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ 505#endif 506 .walat = 1, /* Write additional latency */ 507 .ralat = 5, /* Read additional latency */ 508 .mif3_mode = 3, /* Command prediction working mode */ 509 .bi_on = 1, /* Bank interleaving enabled */ 510 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 511 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 512 .pd_fast_exit = 1, /* enable precharge power-down fast exit */ 513 .ddr_type = DDR_TYPE_DDR3, 514 .refsel = 1, /* Refresh cycles at 32KHz */ 515 .refr = 7, /* 8 refresh commands per refresh cycle */ 516 }; 517 518 /* 519 * MMDC Calibration requires the following data: 520 * mx6_mmdc_calibration - board-specific calibration (routing delays) 521 * these calibration values depend on board routing, SoC, and DDR 522 * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc) 523 * mx6_ddr_cfg - chip specific timing/layout details 524 */ 525 if (width == 16 && size_mb == 128) { 526 mem = &mt41k64m16jt_125; 527 if (is_cpu_type(MXC_CPU_MX6Q)) 528 ; 529 else 530 calib = &mx6sdl_64x16_mmdc_calib; 531 debug("1gB density\n"); 532 } else if (width == 16 && size_mb == 256) { 533 /* 1x 2Gb density chip - same calib as 2x 2Gb */ 534 mem = &mt41k128m16jt_125; 535 if (is_cpu_type(MXC_CPU_MX6Q)) 536 calib = &mx6dq_128x32_mmdc_calib; 537 else 538 calib = &mx6sdl_128x32_mmdc_calib; 539 debug("2gB density\n"); 540 } else if (width == 16 && size_mb == 512) { 541 mem = &mt41k256m16ha_125; 542 if (is_cpu_type(MXC_CPU_MX6Q)) 543 calib = &mx6dq_256x16_mmdc_calib; 544 else 545 calib = &mx6sdl_256x16_mmdc_calib; 546 debug("4gB density\n"); 547 } else if (width == 16 && size_mb == 1024) { 548 mem = &mt41k512m16ha_125; 549 if (is_cpu_type(MXC_CPU_MX6Q)) 550 calib = &mx6dq_512x32_mmdc_calib; 551 debug("8gB density\n"); 552 } else if (width == 32 && size_mb == 256) { 553 /* Same calib as width==16, size==128 */ 554 mem = &mt41k64m16jt_125; 555 if (is_cpu_type(MXC_CPU_MX6Q)) 556 ; 557 else 558 calib = &mx6sdl_64x16_mmdc_calib; 559 debug("1gB density\n"); 560 } else if (width == 32 && size_mb == 512) { 561 mem = &mt41k128m16jt_125; 562 if (is_cpu_type(MXC_CPU_MX6Q)) 563 calib = &mx6dq_128x32_mmdc_calib; 564 else 565 calib = &mx6sdl_128x32_mmdc_calib; 566 debug("2gB density\n"); 567 } else if (width == 32 && size_mb == 1024) { 568 mem = &mt41k256m16ha_125; 569 if (is_cpu_type(MXC_CPU_MX6Q)) 570 calib = &mx6dq_256x32_mmdc_calib; 571 else 572 calib = &mx6sdl_256x32_mmdc_calib; 573 debug("4gB density\n"); 574 } else if (width == 32 && size_mb == 2048) { 575 mem = &mt41k512m16ha_125; 576 if (is_cpu_type(MXC_CPU_MX6Q)) 577 calib = &mx6dq_512x32_mmdc_calib; 578 debug("8gB density\n"); 579 } else if (width == 64 && size_mb == 512) { 580 mem = &mt41k64m16jt_125; 581 debug("1gB density\n"); 582 if (is_cpu_type(MXC_CPU_MX6Q)) 583 calib = &mx6dq_64x64_mmdc_calib; 584 else 585 calib = &mx6sdl_64x64_mmdc_calib; 586 } else if (width == 64 && size_mb == 1024) { 587 mem = &mt41k128m16jt_125; 588 if (is_cpu_type(MXC_CPU_MX6Q)) 589 calib = &mx6dq_128x64_mmdc_calib; 590 else 591 calib = &mx6sdl_128x64_mmdc_calib; 592 debug("2gB density\n"); 593 } else if (width == 64 && size_mb == 2048) { 594 switch(board_model) { 595 case GW5905: 596 /* 8xMT41K128M16 (2GiB) fly-by mirrored 2-chipsels */ 597 mem = &mt41k128m16jt_125; 598 debug("2gB density - 2 chipsel\n"); 599 if (!is_cpu_type(MXC_CPU_MX6Q)) { 600 calib = &mx6sdl_128x64x2_mmdc_calib; 601 sysinfo.ncs = 2; 602 sysinfo.cs_density = 10; /* CS0_END=39 */ 603 sysinfo.cs1_mirror = 1; /* mirror enabled */ 604 } 605 break; 606 default: 607 mem = &mt41k256m16ha_125; 608 if (is_cpu_type(MXC_CPU_MX6Q)) 609 calib = &mx6dq_256x64_mmdc_calib; 610 else 611 calib = &mx6sdl_256x64_mmdc_calib; 612 debug("4gB density\n"); 613 break; 614 } 615 } else if (width == 64 && size_mb == 4096) { 616 switch(board_model) { 617 case GW5903: 618 /* 8xMT41K256M16 (4GiB) fly-by mirrored 2-chipsels */ 619 mem = &mt41k256m16ha_125; 620 debug("4gB density - 2 chipsel\n"); 621 if (!is_cpu_type(MXC_CPU_MX6Q)) { 622 calib = &mx6sdl_256x64x2_mmdc_calib; 623 sysinfo.ncs = 2; 624 sysinfo.cs_density = 18; /* CS0_END=71 */ 625 sysinfo.cs1_mirror = 1; /* mirror enabled */ 626 } 627 break; 628 default: 629 mem = &mt41k512m16ha_125; 630 if (is_cpu_type(MXC_CPU_MX6Q)) 631 calib = &mx6dq_512x64_mmdc_calib; 632 debug("8gB density\n"); 633 break; 634 } 635 } 636 637 if (!(mem && calib)) { 638 puts("Error: Invalid Calibration/Board Configuration\n"); 639 printf("MEM : %s\n", mem ? "OKAY" : "NULL"); 640 printf("CALIB : %s\n", calib ? "OKAY" : "NULL"); 641 printf("CPUTYPE: %s\n", 642 is_cpu_type(MXC_CPU_MX6Q) ? "IMX6Q" : "IMX6DL"); 643 printf("SIZE_MB: %d\n", size_mb); 644 printf("WIDTH : %d\n", width); 645 hang(); 646 } 647 648 if (is_cpu_type(MXC_CPU_MX6Q)) 649 mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, 650 &mx6dq_grp_ioregs); 651 else 652 mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, 653 &mx6sdl_grp_ioregs); 654 mx6_dram_cfg(&sysinfo, calib, mem); 655} 656 657static void ccgr_init(void) 658{ 659 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 660 661 writel(0x00C03F3F, &ccm->CCGR0); 662 writel(0x0030FC03, &ccm->CCGR1); 663 writel(0x0FFFC000, &ccm->CCGR2); 664 writel(0x3FF00000, &ccm->CCGR3); 665 writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */ 666 writel(0x0F0000C3, &ccm->CCGR5); 667 writel(0x000003FF, &ccm->CCGR6); 668} 669 670/* UART2: Serial Console */ 671static const iomux_v3_cfg_t uart2_pads[] = { 672 IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 673 IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 674}; 675 676void setup_iomux_uart(void) 677{ 678 SETUP_IOMUX_PADS(uart2_pads); 679} 680 681/* 682 * I2C pad configs: 683 * I2C1: GSC 684 * I2C2: PMIC,PCIe Switch,Clock,Mezz 685 * I2C3: Multimedia/Expansion 686 */ 687static struct i2c_pads_info mx6q_i2c_pad_info[] = { 688 { 689 .scl = { 690 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC, 691 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC, 692 .gp = IMX_GPIO_NR(3, 21) 693 }, 694 .sda = { 695 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC, 696 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC, 697 .gp = IMX_GPIO_NR(3, 28) 698 } 699 }, { 700 .scl = { 701 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC, 702 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC, 703 .gp = IMX_GPIO_NR(4, 12) 704 }, 705 .sda = { 706 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, 707 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC, 708 .gp = IMX_GPIO_NR(4, 13) 709 } 710 }, { 711 .scl = { 712 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC, 713 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC, 714 .gp = IMX_GPIO_NR(1, 3) 715 }, 716 .sda = { 717 .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC, 718 .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC, 719 .gp = IMX_GPIO_NR(1, 6) 720 } 721 } 722}; 723 724static struct i2c_pads_info mx6dl_i2c_pad_info[] = { 725 { 726 .scl = { 727 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC, 728 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC, 729 .gp = IMX_GPIO_NR(3, 21) 730 }, 731 .sda = { 732 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC, 733 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC, 734 .gp = IMX_GPIO_NR(3, 28) 735 } 736 }, { 737 .scl = { 738 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC, 739 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC, 740 .gp = IMX_GPIO_NR(4, 12) 741 }, 742 .sda = { 743 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC, 744 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC, 745 .gp = IMX_GPIO_NR(4, 13) 746 } 747 }, { 748 .scl = { 749 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC, 750 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC, 751 .gp = IMX_GPIO_NR(1, 3) 752 }, 753 .sda = { 754 .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC, 755 .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC, 756 .gp = IMX_GPIO_NR(1, 6) 757 } 758 } 759}; 760 761static void setup_ventana_i2c(int i2c) 762{ 763 struct i2c_pads_info *p; 764 765 if (is_cpu_type(MXC_CPU_MX6Q)) 766 p = &mx6q_i2c_pad_info[i2c]; 767 else 768 p = &mx6dl_i2c_pad_info[i2c]; 769 770 setup_i2c(i2c, CONFIG_SYS_I2C_SPEED, 0x7f, p); 771} 772 773/* setup board specific PMIC */ 774void setup_pmic(void) 775{ 776 struct pmic *p; 777 const int i2c_pmic = 1; 778 u32 reg; 779 char rev; 780 int i; 781 782 /* determine board revision */ 783 rev = 'A'; 784 for (i = sizeof(ventana_info.model) - 1; i > 0; i--) { 785 if (ventana_info.model[i] >= 'A') { 786 rev = ventana_info.model[i]; 787 break; 788 } 789 } 790 791 i2c_set_bus_num(i2c_pmic); 792 793 /* configure PFUZE100 PMIC */ 794 if (!i2c_probe(CFG_POWER_PFUZE100_I2C_ADDR)) { 795 debug("probed PFUZE100@0x%x\n", CFG_POWER_PFUZE100_I2C_ADDR); 796 power_pfuze100_init(i2c_pmic); 797 p = pmic_get("PFUZE100"); 798 if (p && !pmic_probe(p)) { 799 pmic_reg_read(p, PFUZE100_DEVICEID, ®); 800 printf("PMIC: PFUZE100 ID=0x%02x\n", reg); 801 802 /* Set VGEN1 to 1.5V and enable */ 803 pmic_reg_read(p, PFUZE100_VGEN1VOL, ®); 804 reg &= ~(LDO_VOL_MASK); 805 reg |= (LDOA_1_50V | LDO_EN); 806 pmic_reg_write(p, PFUZE100_VGEN1VOL, reg); 807 808 /* Set SWBST to 5.0V and enable */ 809 pmic_reg_read(p, PFUZE100_SWBSTCON1, ®); 810 reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK); 811 reg |= (SWBST_5_00V | (SWBST_MODE_AUTO << SWBST_MODE_SHIFT)); 812 pmic_reg_write(p, PFUZE100_SWBSTCON1, reg); 813 814 if (board_type == GW54xx && (rev == 'G')) { 815 /* Disable VGEN5 */ 816 pmic_reg_write(p, PFUZE100_VGEN5VOL, 0); 817 818 /* Set VGEN6 to 2.5V and enable */ 819 pmic_reg_read(p, PFUZE100_VGEN6VOL, ®); 820 reg &= ~(LDO_VOL_MASK); 821 reg |= (LDOB_2_50V | LDO_EN); 822 pmic_reg_write(p, PFUZE100_VGEN6VOL, reg); 823 } 824 } 825 826 /* put all switchers in continuous mode */ 827 pmic_reg_read(p, PFUZE100_SW1ABMODE, ®); 828 reg &= ~(SW_MODE_MASK); 829 reg |= PWM_PWM; 830 pmic_reg_write(p, PFUZE100_SW1ABMODE, reg); 831 832 pmic_reg_read(p, PFUZE100_SW2MODE, ®); 833 reg &= ~(SW_MODE_MASK); 834 reg |= PWM_PWM; 835 pmic_reg_write(p, PFUZE100_SW2MODE, reg); 836 837 pmic_reg_read(p, PFUZE100_SW3AMODE, ®); 838 reg &= ~(SW_MODE_MASK); 839 reg |= PWM_PWM; 840 pmic_reg_write(p, PFUZE100_SW3AMODE, reg); 841 842 pmic_reg_read(p, PFUZE100_SW3BMODE, ®); 843 reg &= ~(SW_MODE_MASK); 844 reg |= PWM_PWM; 845 pmic_reg_write(p, PFUZE100_SW3BMODE, reg); 846 847 pmic_reg_read(p, PFUZE100_SW4MODE, ®); 848 reg &= ~(SW_MODE_MASK); 849 reg |= PWM_PWM; 850 pmic_reg_write(p, PFUZE100_SW4MODE, reg); 851 } 852 853 /* configure LTC3676 PMIC */ 854 else if (!i2c_probe(CFG_POWER_LTC3676_I2C_ADDR)) { 855 debug("probed LTC3676@0x%x\n", CFG_POWER_LTC3676_I2C_ADDR); 856 power_ltc3676_init(i2c_pmic); 857 p = pmic_get("LTC3676_PMIC"); 858 if (!p || pmic_probe(p)) 859 return; 860 puts("PMIC: LTC3676\n"); 861 /* 862 * set board-specific scalar for max CPU frequency 863 * per CPU based on the LDO enabled Operating Ranges 864 * defined in the respective IMX6DQ and IMX6SDL 865 * datasheets. The voltage resulting from the R1/R2 866 * feedback inputs on Ventana is 1308mV. Note that this 867 * is a bit shy of the Vmin of 1350mV in the datasheet 868 * for LDO enabled mode but is as high as we can go. 869 */ 870 switch (board_type) { 871 case GW560x: 872 /* mask PGOOD during SW3 transition */ 873 pmic_reg_write(p, LTC3676_DVB3B, 874 0x1f | LTC3676_PGOOD_MASK); 875 /* set SW3 (VDD_ARM) */ 876 pmic_reg_write(p, LTC3676_DVB3A, 0x1f); 877 break; 878 case GW5903: 879 /* mask PGOOD during SW3 transition */ 880 pmic_reg_write(p, LTC3676_DVB3B, 881 0x1f | LTC3676_PGOOD_MASK); 882 /* set SW3 (VDD_ARM) */ 883 pmic_reg_write(p, LTC3676_DVB3A, 0x1f); 884 885 /* mask PGOOD during SW4 transition */ 886 pmic_reg_write(p, LTC3676_DVB4B, 887 0x1f | LTC3676_PGOOD_MASK); 888 /* set SW4 (VDD_SOC) */ 889 pmic_reg_write(p, LTC3676_DVB4A, 0x1f); 890 break; 891 case GW5905: 892 /* mask PGOOD during SW1 transition */ 893 pmic_reg_write(p, LTC3676_DVB1B, 894 0x1f | LTC3676_PGOOD_MASK); 895 /* set SW1 (VDD_ARM) */ 896 pmic_reg_write(p, LTC3676_DVB1A, 0x1f); 897 898 /* mask PGOOD during SW3 transition */ 899 pmic_reg_write(p, LTC3676_DVB3B, 900 0x1f | LTC3676_PGOOD_MASK); 901 /* set SW3 (VDD_SOC) */ 902 pmic_reg_write(p, LTC3676_DVB3A, 0x1f); 903 break; 904 default: 905 /* mask PGOOD during SW1 transition */ 906 pmic_reg_write(p, LTC3676_DVB1B, 907 0x1f | LTC3676_PGOOD_MASK); 908 /* set SW1 (VDD_SOC) */ 909 pmic_reg_write(p, LTC3676_DVB1A, 0x1f); 910 911 /* mask PGOOD during SW3 transition */ 912 pmic_reg_write(p, LTC3676_DVB3B, 913 0x1f | LTC3676_PGOOD_MASK); 914 /* set SW3 (VDD_ARM) */ 915 pmic_reg_write(p, LTC3676_DVB3A, 0x1f); 916 } 917 918 /* put all switchers in continuous mode */ 919 pmic_reg_write(p, LTC3676_BUCK1, 0xc0); 920 pmic_reg_write(p, LTC3676_BUCK2, 0xc0); 921 pmic_reg_write(p, LTC3676_BUCK3, 0xc0); 922 pmic_reg_write(p, LTC3676_BUCK4, 0xc0); 923 } 924 925 /* configure MP5416 PMIC */ 926 else if (!i2c_probe(0x69)) { 927 puts("PMIC: MP5416\n"); 928 switch (board_type) { 929 case GW5910: 930 /* SW1: VDD_ARM 1.2V -> (1.275 to 1.475) */ 931 reg = MP5416_VSET_EN | MP5416_VSET_SW1_SVAL(1475000); 932 i2c_write(0x69, MP5416_VSET_SW1, 1, (uint8_t *)®, 1); 933 /* SW4: VDD_SOC 1.2V -> (1.350 to 1.475) */ 934 reg = MP5416_VSET_EN | MP5416_VSET_SW4_SVAL(1475000); 935 i2c_write(0x69, MP5416_VSET_SW4, 1, (uint8_t *)®, 1); 936 break; 937 } 938 } 939} 940 941/* 942 * called from C runtime startup code (arch/arm/lib/crt0.S:_main) 943 * - we have a stack and a place to store GD, both in SRAM 944 * - no variable global data is available 945 */ 946void board_init_f(ulong dummy) 947{ 948 struct ventana_board_info ventana_info; 949 int board_model; 950 951 /* setup clock gating */ 952 ccgr_init(); 953 954 /* setup AIPS and disable watchdog */ 955 arch_cpu_init(); 956 957 /* setup AXI */ 958 gpr_init(); 959 960 /* iomux and setup of uart/i2c */ 961 setup_iomux_uart(); 962 setup_ventana_i2c(0); 963 setup_ventana_i2c(1); 964 965 /* setup GP timer */ 966 timer_init(); 967 968 /* UART clocks enabled and gd valid - init serial console */ 969 preloader_console_init(); 970 971 /* 972 * On a board with a missing/depleted backup battery for GSC, the 973 * board may be ready to probe the GSC before its firmware is 974 * running. We will wait here indefinately for the GSC/EEPROM. 975 */ 976 while (1) { 977 if (!i2c_set_bus_num(BOARD_EEPROM_BUSNO) && 978 !i2c_probe(BOARD_EEPROM_ADDR)) 979 break; 980 mdelay(1); 981 } 982 983 /* read/validate EEPROM info to determine board model and SDRAM cfg */ 984 board_model = read_eeprom(&ventana_info); 985 986 /* configure model-specific gpio */ 987 setup_iomux_gpio(board_model); 988 989 /* provide some some default: 32bit 128MB */ 990 if (GW_UNKNOWN == board_model) 991 hang(); 992 993 /* configure MMDC for SDRAM width/size and per-model calibration */ 994 spl_dram_init(8 << ventana_info.sdram_width, 995 16 << ventana_info.sdram_size, 996 board_model); 997} 998 999void board_boot_order(u32 *spl_boot_list) 1000{ 1001 spl_boot_list[0] = spl_boot_device(); 1002 switch (spl_boot_list[0]) { 1003 case BOOT_DEVICE_NAND: 1004 spl_boot_list[1] = BOOT_DEVICE_MMC1; 1005 spl_boot_list[2] = BOOT_DEVICE_UART; 1006 break; 1007 case BOOT_DEVICE_MMC1: 1008 spl_boot_list[1] = BOOT_DEVICE_UART; 1009 break; 1010 } 1011} 1012 1013/* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */ 1014/* its our chance to print info about boot device */ 1015void spl_board_init(void) 1016{ 1017 u32 boot_device; 1018 1019 /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */ 1020 boot_device = spl_boot_device(); 1021 1022 /* read eeprom again now that we have gd */ 1023 board_type = read_eeprom(&ventana_info); 1024 if (board_type == GW_UNKNOWN) 1025 hang(); 1026 1027 switch (boot_device) { 1028 case BOOT_DEVICE_MMC1: 1029 puts("Booting from MMC\n"); 1030 break; 1031 case BOOT_DEVICE_NAND: 1032 puts("Booting from NAND\n"); 1033 break; 1034 case BOOT_DEVICE_SATA: 1035 puts("Booting from SATA\n"); 1036 break; 1037 default: 1038 puts("Unknown boot device\n"); 1039 } 1040 1041 /* PMIC init */ 1042 setup_pmic(); 1043} 1044 1045#ifdef CONFIG_SPL_OS_BOOT 1046/* return 1 if we wish to boot to uboot vs os (falcon mode) */ 1047int spl_start_uboot(void) 1048{ 1049 unsigned char ret = 1; 1050 1051 debug("%s\n", __func__); 1052#ifdef CONFIG_SPL_ENV_SUPPORT 1053 env_init(); 1054 env_load(); 1055 debug("boot_os=%s\n", env_get("boot_os")); 1056 if (env_get_yesno("boot_os") == 1) 1057 ret = 0; 1058#else 1059 /* use i2c-0:0x50:0x00 for falcon boot mode (0=linux, else uboot) */ 1060 i2c_set_bus_num(0); 1061 gsc_i2c_read(0x50, 0x0, 1, &ret, 1); 1062#endif 1063 if (!ret) 1064 gsc_boot_wd_disable(); 1065 1066 debug("%s booting %s\n", __func__, ret ? "uboot" : "linux"); 1067 return ret; 1068} 1069#endif 1070